1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * wm8955.c -- WM8955 ALSA SoC Audio driver 4 * 5 * Copyright 2009 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/init.h> 13#include <linux/delay.h> 14#include <linux/pm.h> 15#include <linux/i2c.h> 16#include <linux/regmap.h> 17#include <linux/regulator/consumer.h> 18#include <linux/slab.h> 19#include <sound/core.h> 20#include <sound/pcm.h> 21#include <sound/pcm_params.h> 22#include <sound/soc.h> 23#include <sound/initval.h> 24#include <sound/tlv.h> 25#include <sound/wm8955.h> 26 27#include "wm8955.h" 28 29#define WM8955_NUM_SUPPLIES 4 30static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = { 31 "DCVDD", 32 "DBVDD", 33 "HPVDD", 34 "AVDD", 35}; 36 37/* codec private data */ 38struct wm8955_priv { 39 struct regmap *regmap; 40 41 unsigned int mclk_rate; 42 43 int deemph; 44 int fs; 45 46 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES]; 47}; 48 49static const struct reg_default wm8955_reg_defaults[] = { 50 { 2, 0x0079 }, /* R2 - LOUT1 volume */ 51 { 3, 0x0079 }, /* R3 - ROUT1 volume */ 52 { 5, 0x0008 }, /* R5 - DAC Control */ 53 { 7, 0x000A }, /* R7 - Audio Interface */ 54 { 8, 0x0000 }, /* R8 - Sample Rate */ 55 { 10, 0x00FF }, /* R10 - Left DAC volume */ 56 { 11, 0x00FF }, /* R11 - Right DAC volume */ 57 { 12, 0x000F }, /* R12 - Bass control */ 58 { 13, 0x000F }, /* R13 - Treble control */ 59 { 23, 0x00C1 }, /* R23 - Additional control (1) */ 60 { 24, 0x0000 }, /* R24 - Additional control (2) */ 61 { 25, 0x0000 }, /* R25 - Power Management (1) */ 62 { 26, 0x0000 }, /* R26 - Power Management (2) */ 63 { 27, 0x0000 }, /* R27 - Additional Control (3) */ 64 { 34, 0x0050 }, /* R34 - Left out Mix (1) */ 65 { 35, 0x0050 }, /* R35 - Left out Mix (2) */ 66 { 36, 0x0050 }, /* R36 - Right out Mix (1) */ 67 { 37, 0x0050 }, /* R37 - Right Out Mix (2) */ 68 { 38, 0x0050 }, /* R38 - Mono out Mix (1) */ 69 { 39, 0x0050 }, /* R39 - Mono out Mix (2) */ 70 { 40, 0x0079 }, /* R40 - LOUT2 volume */ 71 { 41, 0x0079 }, /* R41 - ROUT2 volume */ 72 { 42, 0x0079 }, /* R42 - MONOOUT volume */ 73 { 43, 0x0000 }, /* R43 - Clocking / PLL */ 74 { 44, 0x0103 }, /* R44 - PLL Control 1 */ 75 { 45, 0x0024 }, /* R45 - PLL Control 2 */ 76 { 46, 0x01BA }, /* R46 - PLL Control 3 */ 77 { 59, 0x0000 }, /* R59 - PLL Control 4 */ 78}; 79 80static bool wm8955_writeable(struct device *dev, unsigned int reg) 81{ 82 switch (reg) { 83 case WM8955_LOUT1_VOLUME: 84 case WM8955_ROUT1_VOLUME: 85 case WM8955_DAC_CONTROL: 86 case WM8955_AUDIO_INTERFACE: 87 case WM8955_SAMPLE_RATE: 88 case WM8955_LEFT_DAC_VOLUME: 89 case WM8955_RIGHT_DAC_VOLUME: 90 case WM8955_BASS_CONTROL: 91 case WM8955_TREBLE_CONTROL: 92 case WM8955_RESET: 93 case WM8955_ADDITIONAL_CONTROL_1: 94 case WM8955_ADDITIONAL_CONTROL_2: 95 case WM8955_POWER_MANAGEMENT_1: 96 case WM8955_POWER_MANAGEMENT_2: 97 case WM8955_ADDITIONAL_CONTROL_3: 98 case WM8955_LEFT_OUT_MIX_1: 99 case WM8955_LEFT_OUT_MIX_2: 100 case WM8955_RIGHT_OUT_MIX_1: 101 case WM8955_RIGHT_OUT_MIX_2: 102 case WM8955_MONO_OUT_MIX_1: 103 case WM8955_MONO_OUT_MIX_2: 104 case WM8955_LOUT2_VOLUME: 105 case WM8955_ROUT2_VOLUME: 106 case WM8955_MONOOUT_VOLUME: 107 case WM8955_CLOCKING_PLL: 108 case WM8955_PLL_CONTROL_1: 109 case WM8955_PLL_CONTROL_2: 110 case WM8955_PLL_CONTROL_3: 111 case WM8955_PLL_CONTROL_4: 112 return true; 113 default: 114 return false; 115 } 116} 117 118static bool wm8955_volatile(struct device *dev, unsigned int reg) 119{ 120 switch (reg) { 121 case WM8955_RESET: 122 return true; 123 default: 124 return false; 125 } 126} 127 128static int wm8955_reset(struct snd_soc_component *component) 129{ 130 return snd_soc_component_write(component, WM8955_RESET, 0); 131} 132 133struct pll_factors { 134 int n; 135 int k; 136 int outdiv; 137}; 138 139/* The size in bits of the FLL divide multiplied by 10 140 * to allow rounding later */ 141#define FIXED_FLL_SIZE ((1 << 22) * 10) 142 143static int wm8955_pll_factors(struct device *dev, 144 int Fref, int Fout, struct pll_factors *pll) 145{ 146 u64 Kpart; 147 unsigned int K, Ndiv, Nmod, target; 148 149 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout); 150 151 /* The oscilator should run at should be 90-100MHz, and 152 * there's a divide by 4 plus an optional divide by 2 in the 153 * output path to generate the system clock. The clock table 154 * is sortd so we should always generate a suitable target. */ 155 target = Fout * 4; 156 if (target < 90000000) { 157 pll->outdiv = 1; 158 target *= 2; 159 } else { 160 pll->outdiv = 0; 161 } 162 163 WARN_ON(target < 90000000 || target > 100000000); 164 165 dev_dbg(dev, "Fvco=%dHz\n", target); 166 167 /* Now, calculate N.K */ 168 Ndiv = target / Fref; 169 170 pll->n = Ndiv; 171 Nmod = target % Fref; 172 dev_dbg(dev, "Nmod=%d\n", Nmod); 173 174 /* Calculate fractional part - scale up so we can round. */ 175 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 176 177 do_div(Kpart, Fref); 178 179 K = Kpart & 0xFFFFFFFF; 180 181 if ((K % 10) >= 5) 182 K += 5; 183 184 /* Move down to proper range now rounding is done */ 185 pll->k = K / 10; 186 187 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); 188 189 return 0; 190} 191 192/* Lookup table specifying SRATE (table 25 in datasheet); some of the 193 * output frequencies have been rounded to the standard frequencies 194 * they are intended to match where the error is slight. */ 195static struct { 196 int mclk; 197 int fs; 198 int usb; 199 int sr; 200} clock_cfgs[] = { 201 { 18432000, 8000, 0, 3, }, 202 { 18432000, 12000, 0, 9, }, 203 { 18432000, 16000, 0, 11, }, 204 { 18432000, 24000, 0, 29, }, 205 { 18432000, 32000, 0, 13, }, 206 { 18432000, 48000, 0, 1, }, 207 { 18432000, 96000, 0, 15, }, 208 209 { 16934400, 8018, 0, 19, }, 210 { 16934400, 11025, 0, 25, }, 211 { 16934400, 22050, 0, 27, }, 212 { 16934400, 44100, 0, 17, }, 213 { 16934400, 88200, 0, 31, }, 214 215 { 12000000, 8000, 1, 2, }, 216 { 12000000, 11025, 1, 25, }, 217 { 12000000, 12000, 1, 8, }, 218 { 12000000, 16000, 1, 10, }, 219 { 12000000, 22050, 1, 27, }, 220 { 12000000, 24000, 1, 28, }, 221 { 12000000, 32000, 1, 12, }, 222 { 12000000, 44100, 1, 17, }, 223 { 12000000, 48000, 1, 0, }, 224 { 12000000, 88200, 1, 31, }, 225 { 12000000, 96000, 1, 14, }, 226 227 { 12288000, 8000, 0, 2, }, 228 { 12288000, 12000, 0, 8, }, 229 { 12288000, 16000, 0, 10, }, 230 { 12288000, 24000, 0, 28, }, 231 { 12288000, 32000, 0, 12, }, 232 { 12288000, 48000, 0, 0, }, 233 { 12288000, 96000, 0, 14, }, 234 235 { 12289600, 8018, 0, 18, }, 236 { 12289600, 11025, 0, 24, }, 237 { 12289600, 22050, 0, 26, }, 238 { 11289600, 44100, 0, 16, }, 239 { 11289600, 88200, 0, 31, }, 240}; 241 242static int wm8955_configure_clocking(struct snd_soc_component *component) 243{ 244 struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); 245 int i, ret, val; 246 int clocking = 0; 247 int srate = 0; 248 int sr = -1; 249 struct pll_factors pll; 250 251 /* If we're not running a sample rate currently just pick one */ 252 if (wm8955->fs == 0) 253 wm8955->fs = 8000; 254 255 /* Can we generate an exact output? */ 256 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) { 257 if (wm8955->fs != clock_cfgs[i].fs) 258 continue; 259 sr = i; 260 261 if (wm8955->mclk_rate == clock_cfgs[i].mclk) 262 break; 263 } 264 265 /* We should never get here with an unsupported sample rate */ 266 if (sr == -1) { 267 dev_err(component->dev, "Sample rate %dHz unsupported\n", 268 wm8955->fs); 269 WARN_ON(sr == -1); 270 return -EINVAL; 271 } 272 273 if (i == ARRAY_SIZE(clock_cfgs)) { 274 /* If we can't generate the right clock from MCLK then 275 * we should configure the PLL to supply us with an 276 * appropriate clock. 277 */ 278 clocking |= WM8955_MCLKSEL; 279 280 /* Use the last divider configuration we saw for the 281 * sample rate. */ 282 ret = wm8955_pll_factors(component->dev, wm8955->mclk_rate, 283 clock_cfgs[sr].mclk, &pll); 284 if (ret != 0) { 285 dev_err(component->dev, 286 "Unable to generate %dHz from %dHz MCLK\n", 287 wm8955->fs, wm8955->mclk_rate); 288 return -EINVAL; 289 } 290 291 snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_1, 292 WM8955_N_MASK | WM8955_K_21_18_MASK, 293 (pll.n << WM8955_N_SHIFT) | 294 pll.k >> 18); 295 snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_2, 296 WM8955_K_17_9_MASK, 297 (pll.k >> 9) & WM8955_K_17_9_MASK); 298 snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_3, 299 WM8955_K_8_0_MASK, 300 pll.k & WM8955_K_8_0_MASK); 301 if (pll.k) 302 snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4, 303 WM8955_KEN, WM8955_KEN); 304 else 305 snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4, 306 WM8955_KEN, 0); 307 308 if (pll.outdiv) 309 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2; 310 else 311 val = WM8955_PLL_RB; 312 313 /* Now start the PLL running */ 314 snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, 315 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val); 316 snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, 317 WM8955_PLLEN, WM8955_PLLEN); 318 } 319 320 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT); 321 322 snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE, 323 WM8955_USB | WM8955_SR_MASK, srate); 324 snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, 325 WM8955_MCLKSEL, clocking); 326 327 return 0; 328} 329 330static int wm8955_sysclk(struct snd_soc_dapm_widget *w, 331 struct snd_kcontrol *kcontrol, int event) 332{ 333 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 334 int ret = 0; 335 336 /* Always disable the clocks - if we're doing reconfiguration this 337 * avoids misclocking. 338 */ 339 snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, 340 WM8955_DIGENB, 0); 341 snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, 342 WM8955_PLL_RB | WM8955_PLLEN, 0); 343 344 switch (event) { 345 case SND_SOC_DAPM_POST_PMD: 346 break; 347 case SND_SOC_DAPM_PRE_PMU: 348 ret = wm8955_configure_clocking(component); 349 break; 350 default: 351 ret = -EINVAL; 352 break; 353 } 354 355 return ret; 356} 357 358static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 359 360static int wm8955_set_deemph(struct snd_soc_component *component) 361{ 362 struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); 363 int val, i, best; 364 365 /* If we're using deemphasis select the nearest available sample 366 * rate. 367 */ 368 if (wm8955->deemph) { 369 best = 1; 370 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 371 if (abs(deemph_settings[i] - wm8955->fs) < 372 abs(deemph_settings[best] - wm8955->fs)) 373 best = i; 374 } 375 376 val = best << WM8955_DEEMPH_SHIFT; 377 } else { 378 val = 0; 379 } 380 381 dev_dbg(component->dev, "Set deemphasis %d\n", val); 382 383 return snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, 384 WM8955_DEEMPH_MASK, val); 385} 386 387static int wm8955_get_deemph(struct snd_kcontrol *kcontrol, 388 struct snd_ctl_elem_value *ucontrol) 389{ 390 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 391 struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); 392 393 ucontrol->value.integer.value[0] = wm8955->deemph; 394 return 0; 395} 396 397static int wm8955_put_deemph(struct snd_kcontrol *kcontrol, 398 struct snd_ctl_elem_value *ucontrol) 399{ 400 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 401 struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); 402 unsigned int deemph = ucontrol->value.integer.value[0]; 403 404 if (deemph > 1) 405 return -EINVAL; 406 407 wm8955->deemph = deemph; 408 409 return wm8955_set_deemph(component); 410} 411 412static const char *bass_mode_text[] = { 413 "Linear", "Adaptive", 414}; 415 416static SOC_ENUM_SINGLE_DECL(bass_mode, WM8955_BASS_CONTROL, 7, bass_mode_text); 417 418static const char *bass_cutoff_text[] = { 419 "Low", "High" 420}; 421 422static SOC_ENUM_SINGLE_DECL(bass_cutoff, WM8955_BASS_CONTROL, 6, 423 bass_cutoff_text); 424 425static const char *treble_cutoff_text[] = { 426 "High", "Low" 427}; 428 429static SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8955_TREBLE_CONTROL, 2, 430 treble_cutoff_text); 431 432static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); 433static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0); 434static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 435static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0); 436static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 437static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1); 438 439static const struct snd_kcontrol_new wm8955_snd_controls[] = { 440SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME, 441 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv), 442SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1, 443 atten_tlv), 444SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 445 wm8955_get_deemph, wm8955_put_deemph), 446 447SOC_ENUM("Bass Mode", bass_mode), 448SOC_ENUM("Bass Cutoff", bass_cutoff), 449SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1), 450 451SOC_ENUM("Treble Cutoff", treble_cutoff), 452SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv), 453 454SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1, 455 bypass_tlv), 456SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1, 457 bypass_tlv), 458 459SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1, 460 bypass_tlv), 461SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1, 462 bypass_tlv), 463 464/* Not a stereo pair so they line up with the DAPM switches */ 465SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1, 466 mono_tlv), 467SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1, 468 mono_tlv), 469 470SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME, 471 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv), 472SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME, 473 WM8955_ROUT1_VOLUME, 7, 1, 0), 474 475SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME, 476 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv), 477SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME, 478 WM8955_ROUT2_VOLUME, 7, 1, 0), 479 480SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv), 481SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0), 482}; 483 484static const struct snd_kcontrol_new lmixer[] = { 485SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0), 486SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0), 487SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0), 488SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0), 489}; 490 491static const struct snd_kcontrol_new rmixer[] = { 492SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0), 493SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0), 494SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0), 495SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0), 496}; 497 498static const struct snd_kcontrol_new mmixer[] = { 499SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0), 500SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0), 501SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0), 502SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0), 503}; 504 505static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = { 506SND_SOC_DAPM_INPUT("MONOIN-"), 507SND_SOC_DAPM_INPUT("MONOIN+"), 508SND_SOC_DAPM_INPUT("LINEINR"), 509SND_SOC_DAPM_INPUT("LINEINL"), 510 511SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0), 512 513SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk, 514 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 515SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0), 516 517SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0), 518SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0), 519 520SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0), 521SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0), 522SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0), 523SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0), 524SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0), 525SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 526 527/* The names are chosen to make the control names nice */ 528SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0, 529 lmixer, ARRAY_SIZE(lmixer)), 530SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0, 531 rmixer, ARRAY_SIZE(rmixer)), 532SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0, 533 mmixer, ARRAY_SIZE(mmixer)), 534 535SND_SOC_DAPM_OUTPUT("LOUT1"), 536SND_SOC_DAPM_OUTPUT("ROUT1"), 537SND_SOC_DAPM_OUTPUT("LOUT2"), 538SND_SOC_DAPM_OUTPUT("ROUT2"), 539SND_SOC_DAPM_OUTPUT("MONOOUT"), 540SND_SOC_DAPM_OUTPUT("OUT3"), 541}; 542 543static const struct snd_soc_dapm_route wm8955_dapm_routes[] = { 544 { "DACL", NULL, "SYSCLK" }, 545 { "DACR", NULL, "SYSCLK" }, 546 547 { "Mono Input", NULL, "MONOIN-" }, 548 { "Mono Input", NULL, "MONOIN+" }, 549 550 { "Left", "Playback Switch", "DACL" }, 551 { "Left", "Right Playback Switch", "DACR" }, 552 { "Left", "Bypass Switch", "LINEINL" }, 553 { "Left", "Mono Switch", "Mono Input" }, 554 555 { "Right", "Playback Switch", "DACR" }, 556 { "Right", "Left Playback Switch", "DACL" }, 557 { "Right", "Bypass Switch", "LINEINR" }, 558 { "Right", "Mono Switch", "Mono Input" }, 559 560 { "Mono", "Left Playback Switch", "DACL" }, 561 { "Mono", "Right Playback Switch", "DACR" }, 562 { "Mono", "Left Bypass Switch", "LINEINL" }, 563 { "Mono", "Right Bypass Switch", "LINEINR" }, 564 565 { "LOUT1 PGA", NULL, "Left" }, 566 { "LOUT1", NULL, "TSDEN" }, 567 { "LOUT1", NULL, "LOUT1 PGA" }, 568 569 { "ROUT1 PGA", NULL, "Right" }, 570 { "ROUT1", NULL, "TSDEN" }, 571 { "ROUT1", NULL, "ROUT1 PGA" }, 572 573 { "LOUT2 PGA", NULL, "Left" }, 574 { "LOUT2", NULL, "TSDEN" }, 575 { "LOUT2", NULL, "LOUT2 PGA" }, 576 577 { "ROUT2 PGA", NULL, "Right" }, 578 { "ROUT2", NULL, "TSDEN" }, 579 { "ROUT2", NULL, "ROUT2 PGA" }, 580 581 { "MOUT PGA", NULL, "Mono" }, 582 { "MONOOUT", NULL, "MOUT PGA" }, 583 584 /* OUT3 not currently implemented */ 585 { "OUT3", NULL, "OUT3 PGA" }, 586}; 587 588static int wm8955_hw_params(struct snd_pcm_substream *substream, 589 struct snd_pcm_hw_params *params, 590 struct snd_soc_dai *dai) 591{ 592 struct snd_soc_component *component = dai->component; 593 struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); 594 int ret; 595 int wl; 596 597 switch (params_width(params)) { 598 case 16: 599 wl = 0; 600 break; 601 case 20: 602 wl = 0x4; 603 break; 604 case 24: 605 wl = 0x8; 606 break; 607 case 32: 608 wl = 0xc; 609 break; 610 default: 611 return -EINVAL; 612 } 613 snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE, 614 WM8955_WL_MASK, wl); 615 616 wm8955->fs = params_rate(params); 617 wm8955_set_deemph(component); 618 619 /* If the chip is clocked then disable the clocks and force a 620 * reconfiguration, otherwise DAPM will power up the 621 * clocks for us later. */ 622 ret = snd_soc_component_read(component, WM8955_POWER_MANAGEMENT_1); 623 if (ret < 0) 624 return ret; 625 if (ret & WM8955_DIGENB) { 626 snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, 627 WM8955_DIGENB, 0); 628 snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, 629 WM8955_PLL_RB | WM8955_PLLEN, 0); 630 631 wm8955_configure_clocking(component); 632 } 633 634 return 0; 635} 636 637 638static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id, 639 unsigned int freq, int dir) 640{ 641 struct snd_soc_component *component = dai->component; 642 struct wm8955_priv *priv = snd_soc_component_get_drvdata(component); 643 int div; 644 645 switch (clk_id) { 646 case WM8955_CLK_MCLK: 647 if (freq > 15000000) { 648 priv->mclk_rate = freq /= 2; 649 div = WM8955_MCLKDIV2; 650 } else { 651 priv->mclk_rate = freq; 652 div = 0; 653 } 654 655 snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE, 656 WM8955_MCLKDIV2, div); 657 break; 658 659 default: 660 return -EINVAL; 661 } 662 663 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 664 665 return 0; 666} 667 668static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 669{ 670 struct snd_soc_component *component = dai->component; 671 u16 aif = 0; 672 673 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 674 case SND_SOC_DAIFMT_CBS_CFS: 675 break; 676 case SND_SOC_DAIFMT_CBM_CFM: 677 aif |= WM8955_MS; 678 break; 679 default: 680 return -EINVAL; 681 } 682 683 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 684 case SND_SOC_DAIFMT_DSP_B: 685 aif |= WM8955_LRP; 686 fallthrough; 687 case SND_SOC_DAIFMT_DSP_A: 688 aif |= 0x3; 689 break; 690 case SND_SOC_DAIFMT_I2S: 691 aif |= 0x2; 692 break; 693 case SND_SOC_DAIFMT_RIGHT_J: 694 break; 695 case SND_SOC_DAIFMT_LEFT_J: 696 aif |= 0x1; 697 break; 698 default: 699 return -EINVAL; 700 } 701 702 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 703 case SND_SOC_DAIFMT_DSP_A: 704 case SND_SOC_DAIFMT_DSP_B: 705 /* frame inversion not valid for DSP modes */ 706 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 707 case SND_SOC_DAIFMT_NB_NF: 708 break; 709 case SND_SOC_DAIFMT_IB_NF: 710 aif |= WM8955_BCLKINV; 711 break; 712 default: 713 return -EINVAL; 714 } 715 break; 716 717 case SND_SOC_DAIFMT_I2S: 718 case SND_SOC_DAIFMT_RIGHT_J: 719 case SND_SOC_DAIFMT_LEFT_J: 720 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 721 case SND_SOC_DAIFMT_NB_NF: 722 break; 723 case SND_SOC_DAIFMT_IB_IF: 724 aif |= WM8955_BCLKINV | WM8955_LRP; 725 break; 726 case SND_SOC_DAIFMT_IB_NF: 727 aif |= WM8955_BCLKINV; 728 break; 729 case SND_SOC_DAIFMT_NB_IF: 730 aif |= WM8955_LRP; 731 break; 732 default: 733 return -EINVAL; 734 } 735 break; 736 default: 737 return -EINVAL; 738 } 739 740 snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE, 741 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV | 742 WM8955_LRP, aif); 743 744 return 0; 745} 746 747 748static int wm8955_mute(struct snd_soc_dai *codec_dai, int mute, int direction) 749{ 750 struct snd_soc_component *component = codec_dai->component; 751 int val; 752 753 if (mute) 754 val = WM8955_DACMU; 755 else 756 val = 0; 757 758 snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, WM8955_DACMU, val); 759 760 return 0; 761} 762 763static int wm8955_set_bias_level(struct snd_soc_component *component, 764 enum snd_soc_bias_level level) 765{ 766 struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); 767 int ret; 768 769 switch (level) { 770 case SND_SOC_BIAS_ON: 771 break; 772 773 case SND_SOC_BIAS_PREPARE: 774 /* VMID resistance 2*50k */ 775 snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, 776 WM8955_VMIDSEL_MASK, 777 0x1 << WM8955_VMIDSEL_SHIFT); 778 779 /* Default bias current */ 780 snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1, 781 WM8955_VSEL_MASK, 782 0x2 << WM8955_VSEL_SHIFT); 783 break; 784 785 case SND_SOC_BIAS_STANDBY: 786 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 787 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), 788 wm8955->supplies); 789 if (ret != 0) { 790 dev_err(component->dev, 791 "Failed to enable supplies: %d\n", 792 ret); 793 return ret; 794 } 795 796 regcache_sync(wm8955->regmap); 797 798 /* Enable VREF and VMID */ 799 snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, 800 WM8955_VREF | 801 WM8955_VMIDSEL_MASK, 802 WM8955_VREF | 803 0x3 << WM8955_VREF_SHIFT); 804 805 /* Let VMID ramp */ 806 msleep(500); 807 808 /* High resistance VROI to maintain outputs */ 809 snd_soc_component_update_bits(component, 810 WM8955_ADDITIONAL_CONTROL_3, 811 WM8955_VROI, WM8955_VROI); 812 } 813 814 /* Maintain VMID with 2*250k */ 815 snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, 816 WM8955_VMIDSEL_MASK, 817 0x2 << WM8955_VMIDSEL_SHIFT); 818 819 /* Minimum bias current */ 820 snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1, 821 WM8955_VSEL_MASK, 0); 822 break; 823 824 case SND_SOC_BIAS_OFF: 825 /* Low resistance VROI to help discharge */ 826 snd_soc_component_update_bits(component, 827 WM8955_ADDITIONAL_CONTROL_3, 828 WM8955_VROI, 0); 829 830 /* Turn off VMID and VREF */ 831 snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, 832 WM8955_VREF | 833 WM8955_VMIDSEL_MASK, 0); 834 835 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), 836 wm8955->supplies); 837 break; 838 } 839 return 0; 840} 841 842#define WM8955_RATES SNDRV_PCM_RATE_8000_96000 843 844#define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 845 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 846 847static const struct snd_soc_dai_ops wm8955_dai_ops = { 848 .set_sysclk = wm8955_set_sysclk, 849 .set_fmt = wm8955_set_fmt, 850 .hw_params = wm8955_hw_params, 851 .mute_stream = wm8955_mute, 852 .no_capture_mute = 1, 853}; 854 855static struct snd_soc_dai_driver wm8955_dai = { 856 .name = "wm8955-hifi", 857 .playback = { 858 .stream_name = "Playback", 859 .channels_min = 2, 860 .channels_max = 2, 861 .rates = WM8955_RATES, 862 .formats = WM8955_FORMATS, 863 }, 864 .ops = &wm8955_dai_ops, 865}; 866 867static int wm8955_probe(struct snd_soc_component *component) 868{ 869 struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); 870 struct wm8955_pdata *pdata = dev_get_platdata(component->dev); 871 int ret, i; 872 873 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++) 874 wm8955->supplies[i].supply = wm8955_supply_names[i]; 875 876 ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8955->supplies), 877 wm8955->supplies); 878 if (ret != 0) { 879 dev_err(component->dev, "Failed to request supplies: %d\n", ret); 880 return ret; 881 } 882 883 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), 884 wm8955->supplies); 885 if (ret != 0) { 886 dev_err(component->dev, "Failed to enable supplies: %d\n", ret); 887 return ret; 888 } 889 890 ret = wm8955_reset(component); 891 if (ret < 0) { 892 dev_err(component->dev, "Failed to issue reset: %d\n", ret); 893 goto err_enable; 894 } 895 896 /* Change some default settings - latch VU and enable ZC */ 897 snd_soc_component_update_bits(component, WM8955_LEFT_DAC_VOLUME, 898 WM8955_LDVU, WM8955_LDVU); 899 snd_soc_component_update_bits(component, WM8955_RIGHT_DAC_VOLUME, 900 WM8955_RDVU, WM8955_RDVU); 901 snd_soc_component_update_bits(component, WM8955_LOUT1_VOLUME, 902 WM8955_LO1VU | WM8955_LO1ZC, 903 WM8955_LO1VU | WM8955_LO1ZC); 904 snd_soc_component_update_bits(component, WM8955_ROUT1_VOLUME, 905 WM8955_RO1VU | WM8955_RO1ZC, 906 WM8955_RO1VU | WM8955_RO1ZC); 907 snd_soc_component_update_bits(component, WM8955_LOUT2_VOLUME, 908 WM8955_LO2VU | WM8955_LO2ZC, 909 WM8955_LO2VU | WM8955_LO2ZC); 910 snd_soc_component_update_bits(component, WM8955_ROUT2_VOLUME, 911 WM8955_RO2VU | WM8955_RO2ZC, 912 WM8955_RO2VU | WM8955_RO2ZC); 913 snd_soc_component_update_bits(component, WM8955_MONOOUT_VOLUME, 914 WM8955_MOZC, WM8955_MOZC); 915 916 /* Also enable adaptive bass boost by default */ 917 snd_soc_component_update_bits(component, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB); 918 919 /* Set platform data values */ 920 if (pdata) { 921 if (pdata->out2_speaker) 922 snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_2, 923 WM8955_ROUT2INV, WM8955_ROUT2INV); 924 925 if (pdata->monoin_diff) 926 snd_soc_component_update_bits(component, WM8955_MONO_OUT_MIX_1, 927 WM8955_DMEN, WM8955_DMEN); 928 } 929 930 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY); 931 932 /* Bias level configuration will have done an extra enable */ 933 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); 934 935 return 0; 936 937err_enable: 938 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); 939 return ret; 940} 941 942static const struct snd_soc_component_driver soc_component_dev_wm8955 = { 943 .probe = wm8955_probe, 944 .set_bias_level = wm8955_set_bias_level, 945 .controls = wm8955_snd_controls, 946 .num_controls = ARRAY_SIZE(wm8955_snd_controls), 947 .dapm_widgets = wm8955_dapm_widgets, 948 .num_dapm_widgets = ARRAY_SIZE(wm8955_dapm_widgets), 949 .dapm_routes = wm8955_dapm_routes, 950 .num_dapm_routes = ARRAY_SIZE(wm8955_dapm_routes), 951 .suspend_bias_off = 1, 952 .idle_bias_on = 1, 953 .use_pmdown_time = 1, 954 .endianness = 1, 955}; 956 957static const struct regmap_config wm8955_regmap = { 958 .reg_bits = 7, 959 .val_bits = 9, 960 961 .max_register = WM8955_MAX_REGISTER, 962 .volatile_reg = wm8955_volatile, 963 .writeable_reg = wm8955_writeable, 964 965 .cache_type = REGCACHE_MAPLE, 966 .reg_defaults = wm8955_reg_defaults, 967 .num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults), 968}; 969 970static int wm8955_i2c_probe(struct i2c_client *i2c) 971{ 972 struct wm8955_priv *wm8955; 973 int ret; 974 975 wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv), 976 GFP_KERNEL); 977 if (wm8955 == NULL) 978 return -ENOMEM; 979 980 wm8955->regmap = devm_regmap_init_i2c(i2c, &wm8955_regmap); 981 if (IS_ERR(wm8955->regmap)) { 982 ret = PTR_ERR(wm8955->regmap); 983 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 984 ret); 985 return ret; 986 } 987 988 i2c_set_clientdata(i2c, wm8955); 989 990 ret = devm_snd_soc_register_component(&i2c->dev, 991 &soc_component_dev_wm8955, &wm8955_dai, 1); 992 993 return ret; 994} 995 996static const struct i2c_device_id wm8955_i2c_id[] = { 997 { "wm8955", 0 }, 998 { } 999}; 1000MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id); 1001 1002static struct i2c_driver wm8955_i2c_driver = { 1003 .driver = { 1004 .name = "wm8955", 1005 }, 1006 .probe = wm8955_i2c_probe, 1007 .id_table = wm8955_i2c_id, 1008}; 1009 1010module_i2c_driver(wm8955_i2c_driver); 1011 1012MODULE_DESCRIPTION("ASoC WM8955 driver"); 1013MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1014MODULE_LICENSE("GPL"); 1015