1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * rt5677.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9#include <linux/delay.h> 10#include <linux/firmware.h> 11#include <linux/fs.h> 12#include <linux/i2c.h> 13#include <linux/init.h> 14#include <linux/interrupt.h> 15#include <linux/irqdomain.h> 16#include <linux/irq.h> 17#include <linux/module.h> 18#include <linux/moduleparam.h> 19#include <linux/platform_device.h> 20#include <linux/pm.h> 21#include <linux/property.h> 22#include <linux/regmap.h> 23#include <linux/spi/spi.h> 24#include <linux/workqueue.h> 25#include <sound/core.h> 26#include <sound/pcm.h> 27#include <sound/pcm_params.h> 28#include <sound/soc.h> 29#include <sound/soc-dapm.h> 30#include <sound/initval.h> 31#include <sound/tlv.h> 32 33#include "rl6231.h" 34#include "rt5677.h" 35#include "rt5677-spi.h" 36 37#define RT5677_DEVICE_ID 0x6327 38 39/* Register controlling boot vector */ 40#define RT5677_DSP_BOOT_VECTOR 0x1801f090 41#define RT5677_MODEL_ADDR 0x5FFC9800 42 43#define RT5677_PR_RANGE_BASE (0xff + 1) 44#define RT5677_PR_SPACING 0x100 45 46#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 47 48static const struct regmap_range_cfg rt5677_ranges[] = { 49 { 50 .name = "PR", 51 .range_min = RT5677_PR_BASE, 52 .range_max = RT5677_PR_BASE + 0xfd, 53 .selector_reg = RT5677_PRIV_INDEX, 54 .selector_mask = 0xff, 55 .selector_shift = 0x0, 56 .window_start = RT5677_PRIV_DATA, 57 .window_len = 0x1, 58 }, 59}; 60 61static const struct reg_sequence init_list[] = { 62 {RT5677_ASRC_12, 0x0018}, 63 {RT5677_PR_BASE + 0x3d, 0x364d}, 64 {RT5677_PR_BASE + 0x17, 0x4fc0}, 65 {RT5677_PR_BASE + 0x13, 0x0312}, 66 {RT5677_PR_BASE + 0x1e, 0x0000}, 67 {RT5677_PR_BASE + 0x12, 0x0eaa}, 68 {RT5677_PR_BASE + 0x14, 0x018a}, 69 {RT5677_PR_BASE + 0x15, 0x0490}, 70 {RT5677_PR_BASE + 0x38, 0x0f71}, 71 {RT5677_PR_BASE + 0x39, 0x0f71}, 72}; 73#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 74 75static const struct reg_default rt5677_reg[] = { 76 {RT5677_RESET , 0x0000}, 77 {RT5677_LOUT1 , 0xa800}, 78 {RT5677_IN1 , 0x0000}, 79 {RT5677_MICBIAS , 0x0000}, 80 {RT5677_SLIMBUS_PARAM , 0x0000}, 81 {RT5677_SLIMBUS_RX , 0x0000}, 82 {RT5677_SLIMBUS_CTRL , 0x0000}, 83 {RT5677_SIDETONE_CTRL , 0x000b}, 84 {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, 85 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, 86 {RT5677_DAC4_DIG_VOL , 0xafaf}, 87 {RT5677_DAC3_DIG_VOL , 0xafaf}, 88 {RT5677_DAC1_DIG_VOL , 0xafaf}, 89 {RT5677_DAC2_DIG_VOL , 0xafaf}, 90 {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, 91 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, 92 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, 93 {RT5677_STO1_2_ADC_BST , 0x0000}, 94 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, 95 {RT5677_ADC_BST_CTRL2 , 0x0000}, 96 {RT5677_STO3_4_ADC_BST , 0x0000}, 97 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, 98 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, 99 {RT5677_STO4_ADC_MIXER , 0xd4c0}, 100 {RT5677_STO3_ADC_MIXER , 0xd4c0}, 101 {RT5677_STO2_ADC_MIXER , 0xd4c0}, 102 {RT5677_STO1_ADC_MIXER , 0xd4c0}, 103 {RT5677_MONO_ADC_MIXER , 0xd4d1}, 104 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, 105 {RT5677_STO1_DAC_MIXER , 0xaaaa}, 106 {RT5677_MONO_DAC_MIXER , 0xaaaa}, 107 {RT5677_DD1_MIXER , 0xaaaa}, 108 {RT5677_DD2_MIXER , 0xaaaa}, 109 {RT5677_IF3_DATA , 0x0000}, 110 {RT5677_IF4_DATA , 0x0000}, 111 {RT5677_PDM_OUT_CTRL , 0x8888}, 112 {RT5677_PDM_DATA_CTRL1 , 0x0000}, 113 {RT5677_PDM_DATA_CTRL2 , 0x0000}, 114 {RT5677_PDM1_DATA_CTRL2 , 0x0000}, 115 {RT5677_PDM1_DATA_CTRL3 , 0x0000}, 116 {RT5677_PDM1_DATA_CTRL4 , 0x0000}, 117 {RT5677_PDM2_DATA_CTRL2 , 0x0000}, 118 {RT5677_PDM2_DATA_CTRL3 , 0x0000}, 119 {RT5677_PDM2_DATA_CTRL4 , 0x0000}, 120 {RT5677_TDM1_CTRL1 , 0x0300}, 121 {RT5677_TDM1_CTRL2 , 0x0000}, 122 {RT5677_TDM1_CTRL3 , 0x4000}, 123 {RT5677_TDM1_CTRL4 , 0x0123}, 124 {RT5677_TDM1_CTRL5 , 0x4567}, 125 {RT5677_TDM2_CTRL1 , 0x0300}, 126 {RT5677_TDM2_CTRL2 , 0x0000}, 127 {RT5677_TDM2_CTRL3 , 0x4000}, 128 {RT5677_TDM2_CTRL4 , 0x0123}, 129 {RT5677_TDM2_CTRL5 , 0x4567}, 130 {RT5677_I2C_MASTER_CTRL1 , 0x0001}, 131 {RT5677_I2C_MASTER_CTRL2 , 0x0000}, 132 {RT5677_I2C_MASTER_CTRL3 , 0x0000}, 133 {RT5677_I2C_MASTER_CTRL4 , 0x0000}, 134 {RT5677_I2C_MASTER_CTRL5 , 0x0000}, 135 {RT5677_I2C_MASTER_CTRL6 , 0x0000}, 136 {RT5677_I2C_MASTER_CTRL7 , 0x0000}, 137 {RT5677_I2C_MASTER_CTRL8 , 0x0000}, 138 {RT5677_DMIC_CTRL1 , 0x1505}, 139 {RT5677_DMIC_CTRL2 , 0x0055}, 140 {RT5677_HAP_GENE_CTRL1 , 0x0111}, 141 {RT5677_HAP_GENE_CTRL2 , 0x0064}, 142 {RT5677_HAP_GENE_CTRL3 , 0xef0e}, 143 {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, 144 {RT5677_HAP_GENE_CTRL5 , 0xef0e}, 145 {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, 146 {RT5677_HAP_GENE_CTRL7 , 0xef0e}, 147 {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, 148 {RT5677_HAP_GENE_CTRL9 , 0xf000}, 149 {RT5677_HAP_GENE_CTRL10 , 0x0000}, 150 {RT5677_PWR_DIG1 , 0x0000}, 151 {RT5677_PWR_DIG2 , 0x0000}, 152 {RT5677_PWR_ANLG1 , 0x0055}, 153 {RT5677_PWR_ANLG2 , 0x0000}, 154 {RT5677_PWR_DSP1 , 0x0001}, 155 {RT5677_PWR_DSP_ST , 0x0000}, 156 {RT5677_PWR_DSP2 , 0x0000}, 157 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, 158 {RT5677_PRIV_INDEX , 0x0000}, 159 {RT5677_PRIV_DATA , 0x0000}, 160 {RT5677_I2S4_SDP , 0x8000}, 161 {RT5677_I2S1_SDP , 0x8000}, 162 {RT5677_I2S2_SDP , 0x8000}, 163 {RT5677_I2S3_SDP , 0x8000}, 164 {RT5677_CLK_TREE_CTRL1 , 0x1111}, 165 {RT5677_CLK_TREE_CTRL2 , 0x1111}, 166 {RT5677_CLK_TREE_CTRL3 , 0x0000}, 167 {RT5677_PLL1_CTRL1 , 0x0000}, 168 {RT5677_PLL1_CTRL2 , 0x0000}, 169 {RT5677_PLL2_CTRL1 , 0x0c60}, 170 {RT5677_PLL2_CTRL2 , 0x2000}, 171 {RT5677_GLB_CLK1 , 0x0000}, 172 {RT5677_GLB_CLK2 , 0x0000}, 173 {RT5677_ASRC_1 , 0x0000}, 174 {RT5677_ASRC_2 , 0x0000}, 175 {RT5677_ASRC_3 , 0x0000}, 176 {RT5677_ASRC_4 , 0x0000}, 177 {RT5677_ASRC_5 , 0x0000}, 178 {RT5677_ASRC_6 , 0x0000}, 179 {RT5677_ASRC_7 , 0x0000}, 180 {RT5677_ASRC_8 , 0x0000}, 181 {RT5677_ASRC_9 , 0x0000}, 182 {RT5677_ASRC_10 , 0x0000}, 183 {RT5677_ASRC_11 , 0x0000}, 184 {RT5677_ASRC_12 , 0x0018}, 185 {RT5677_ASRC_13 , 0x0000}, 186 {RT5677_ASRC_14 , 0x0000}, 187 {RT5677_ASRC_15 , 0x0000}, 188 {RT5677_ASRC_16 , 0x0000}, 189 {RT5677_ASRC_17 , 0x0000}, 190 {RT5677_ASRC_18 , 0x0000}, 191 {RT5677_ASRC_19 , 0x0000}, 192 {RT5677_ASRC_20 , 0x0000}, 193 {RT5677_ASRC_21 , 0x000c}, 194 {RT5677_ASRC_22 , 0x0000}, 195 {RT5677_ASRC_23 , 0x0000}, 196 {RT5677_VAD_CTRL1 , 0x2184}, 197 {RT5677_VAD_CTRL2 , 0x010a}, 198 {RT5677_VAD_CTRL3 , 0x0aea}, 199 {RT5677_VAD_CTRL4 , 0x000c}, 200 {RT5677_VAD_CTRL5 , 0x0000}, 201 {RT5677_DSP_INB_CTRL1 , 0x0000}, 202 {RT5677_DSP_INB_CTRL2 , 0x0000}, 203 {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, 204 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, 205 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, 206 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, 207 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, 208 {RT5677_ADC_EQ_CTRL1 , 0x6000}, 209 {RT5677_ADC_EQ_CTRL2 , 0x0000}, 210 {RT5677_EQ_CTRL1 , 0xc000}, 211 {RT5677_EQ_CTRL2 , 0x0000}, 212 {RT5677_EQ_CTRL3 , 0x0000}, 213 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, 214 {RT5677_JD_CTRL1 , 0x0000}, 215 {RT5677_JD_CTRL2 , 0x0000}, 216 {RT5677_JD_CTRL3 , 0x0000}, 217 {RT5677_IRQ_CTRL1 , 0x0000}, 218 {RT5677_IRQ_CTRL2 , 0x0000}, 219 {RT5677_GPIO_ST , 0x0000}, 220 {RT5677_GPIO_CTRL1 , 0x0000}, 221 {RT5677_GPIO_CTRL2 , 0x0000}, 222 {RT5677_GPIO_CTRL3 , 0x0000}, 223 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, 224 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, 225 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, 226 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, 227 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, 228 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, 229 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, 230 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, 231 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, 232 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, 233 {RT5677_MB_DRC_CTRL1 , 0x0f20}, 234 {RT5677_DRC1_CTRL1 , 0x001f}, 235 {RT5677_DRC1_CTRL2 , 0x020c}, 236 {RT5677_DRC1_CTRL3 , 0x1f00}, 237 {RT5677_DRC1_CTRL4 , 0x0000}, 238 {RT5677_DRC1_CTRL5 , 0x0000}, 239 {RT5677_DRC1_CTRL6 , 0x0029}, 240 {RT5677_DRC2_CTRL1 , 0x001f}, 241 {RT5677_DRC2_CTRL2 , 0x020c}, 242 {RT5677_DRC2_CTRL3 , 0x1f00}, 243 {RT5677_DRC2_CTRL4 , 0x0000}, 244 {RT5677_DRC2_CTRL5 , 0x0000}, 245 {RT5677_DRC2_CTRL6 , 0x0029}, 246 {RT5677_DRC1_HL_CTRL1 , 0x8000}, 247 {RT5677_DRC1_HL_CTRL2 , 0x0200}, 248 {RT5677_DRC2_HL_CTRL1 , 0x8000}, 249 {RT5677_DRC2_HL_CTRL2 , 0x0200}, 250 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, 251 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, 252 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, 253 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, 254 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, 255 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, 256 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, 257 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, 258 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, 259 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, 260 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, 261 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, 262 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, 263 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, 264 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, 265 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, 266 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, 267 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, 268 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, 269 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, 270 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, 271 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, 272 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, 273 {RT5677_DIG_MISC , 0x0000}, 274 {RT5677_GEN_CTRL1 , 0x0000}, 275 {RT5677_GEN_CTRL2 , 0x0000}, 276 {RT5677_VENDOR_ID , 0x0000}, 277 {RT5677_VENDOR_ID1 , 0x10ec}, 278 {RT5677_VENDOR_ID2 , 0x6327}, 279}; 280 281static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 282{ 283 int i; 284 285 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 286 if (reg >= rt5677_ranges[i].range_min && 287 reg <= rt5677_ranges[i].range_max) { 288 return true; 289 } 290 } 291 292 switch (reg) { 293 case RT5677_RESET: 294 case RT5677_SLIMBUS_PARAM: 295 case RT5677_PDM_DATA_CTRL1: 296 case RT5677_PDM_DATA_CTRL2: 297 case RT5677_PDM1_DATA_CTRL4: 298 case RT5677_PDM2_DATA_CTRL4: 299 case RT5677_I2C_MASTER_CTRL1: 300 case RT5677_I2C_MASTER_CTRL7: 301 case RT5677_I2C_MASTER_CTRL8: 302 case RT5677_HAP_GENE_CTRL2: 303 case RT5677_PWR_ANLG2: /* Modified by DSP firmware */ 304 case RT5677_PWR_DSP_ST: 305 case RT5677_PRIV_DATA: 306 case RT5677_ASRC_22: 307 case RT5677_ASRC_23: 308 case RT5677_VAD_CTRL5: 309 case RT5677_ADC_EQ_CTRL1: 310 case RT5677_EQ_CTRL1: 311 case RT5677_IRQ_CTRL1: 312 case RT5677_IRQ_CTRL2: 313 case RT5677_GPIO_ST: 314 case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */ 315 case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */ 316 case RT5677_DSP_INB1_SRC_CTRL4: 317 case RT5677_DSP_INB2_SRC_CTRL4: 318 case RT5677_DSP_INB3_SRC_CTRL4: 319 case RT5677_DSP_OUTB1_SRC_CTRL4: 320 case RT5677_DSP_OUTB2_SRC_CTRL4: 321 case RT5677_VENDOR_ID: 322 case RT5677_VENDOR_ID1: 323 case RT5677_VENDOR_ID2: 324 return true; 325 default: 326 return false; 327 } 328} 329 330static bool rt5677_readable_register(struct device *dev, unsigned int reg) 331{ 332 int i; 333 334 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 335 if (reg >= rt5677_ranges[i].range_min && 336 reg <= rt5677_ranges[i].range_max) { 337 return true; 338 } 339 } 340 341 switch (reg) { 342 case RT5677_RESET: 343 case RT5677_LOUT1: 344 case RT5677_IN1: 345 case RT5677_MICBIAS: 346 case RT5677_SLIMBUS_PARAM: 347 case RT5677_SLIMBUS_RX: 348 case RT5677_SLIMBUS_CTRL: 349 case RT5677_SIDETONE_CTRL: 350 case RT5677_ANA_DAC1_2_3_SRC: 351 case RT5677_IF_DSP_DAC3_4_MIXER: 352 case RT5677_DAC4_DIG_VOL: 353 case RT5677_DAC3_DIG_VOL: 354 case RT5677_DAC1_DIG_VOL: 355 case RT5677_DAC2_DIG_VOL: 356 case RT5677_IF_DSP_DAC2_MIXER: 357 case RT5677_STO1_ADC_DIG_VOL: 358 case RT5677_MONO_ADC_DIG_VOL: 359 case RT5677_STO1_2_ADC_BST: 360 case RT5677_STO2_ADC_DIG_VOL: 361 case RT5677_ADC_BST_CTRL2: 362 case RT5677_STO3_4_ADC_BST: 363 case RT5677_STO3_ADC_DIG_VOL: 364 case RT5677_STO4_ADC_DIG_VOL: 365 case RT5677_STO4_ADC_MIXER: 366 case RT5677_STO3_ADC_MIXER: 367 case RT5677_STO2_ADC_MIXER: 368 case RT5677_STO1_ADC_MIXER: 369 case RT5677_MONO_ADC_MIXER: 370 case RT5677_ADC_IF_DSP_DAC1_MIXER: 371 case RT5677_STO1_DAC_MIXER: 372 case RT5677_MONO_DAC_MIXER: 373 case RT5677_DD1_MIXER: 374 case RT5677_DD2_MIXER: 375 case RT5677_IF3_DATA: 376 case RT5677_IF4_DATA: 377 case RT5677_PDM_OUT_CTRL: 378 case RT5677_PDM_DATA_CTRL1: 379 case RT5677_PDM_DATA_CTRL2: 380 case RT5677_PDM1_DATA_CTRL2: 381 case RT5677_PDM1_DATA_CTRL3: 382 case RT5677_PDM1_DATA_CTRL4: 383 case RT5677_PDM2_DATA_CTRL2: 384 case RT5677_PDM2_DATA_CTRL3: 385 case RT5677_PDM2_DATA_CTRL4: 386 case RT5677_TDM1_CTRL1: 387 case RT5677_TDM1_CTRL2: 388 case RT5677_TDM1_CTRL3: 389 case RT5677_TDM1_CTRL4: 390 case RT5677_TDM1_CTRL5: 391 case RT5677_TDM2_CTRL1: 392 case RT5677_TDM2_CTRL2: 393 case RT5677_TDM2_CTRL3: 394 case RT5677_TDM2_CTRL4: 395 case RT5677_TDM2_CTRL5: 396 case RT5677_I2C_MASTER_CTRL1: 397 case RT5677_I2C_MASTER_CTRL2: 398 case RT5677_I2C_MASTER_CTRL3: 399 case RT5677_I2C_MASTER_CTRL4: 400 case RT5677_I2C_MASTER_CTRL5: 401 case RT5677_I2C_MASTER_CTRL6: 402 case RT5677_I2C_MASTER_CTRL7: 403 case RT5677_I2C_MASTER_CTRL8: 404 case RT5677_DMIC_CTRL1: 405 case RT5677_DMIC_CTRL2: 406 case RT5677_HAP_GENE_CTRL1: 407 case RT5677_HAP_GENE_CTRL2: 408 case RT5677_HAP_GENE_CTRL3: 409 case RT5677_HAP_GENE_CTRL4: 410 case RT5677_HAP_GENE_CTRL5: 411 case RT5677_HAP_GENE_CTRL6: 412 case RT5677_HAP_GENE_CTRL7: 413 case RT5677_HAP_GENE_CTRL8: 414 case RT5677_HAP_GENE_CTRL9: 415 case RT5677_HAP_GENE_CTRL10: 416 case RT5677_PWR_DIG1: 417 case RT5677_PWR_DIG2: 418 case RT5677_PWR_ANLG1: 419 case RT5677_PWR_ANLG2: 420 case RT5677_PWR_DSP1: 421 case RT5677_PWR_DSP_ST: 422 case RT5677_PWR_DSP2: 423 case RT5677_ADC_DAC_HPF_CTRL1: 424 case RT5677_PRIV_INDEX: 425 case RT5677_PRIV_DATA: 426 case RT5677_I2S4_SDP: 427 case RT5677_I2S1_SDP: 428 case RT5677_I2S2_SDP: 429 case RT5677_I2S3_SDP: 430 case RT5677_CLK_TREE_CTRL1: 431 case RT5677_CLK_TREE_CTRL2: 432 case RT5677_CLK_TREE_CTRL3: 433 case RT5677_PLL1_CTRL1: 434 case RT5677_PLL1_CTRL2: 435 case RT5677_PLL2_CTRL1: 436 case RT5677_PLL2_CTRL2: 437 case RT5677_GLB_CLK1: 438 case RT5677_GLB_CLK2: 439 case RT5677_ASRC_1: 440 case RT5677_ASRC_2: 441 case RT5677_ASRC_3: 442 case RT5677_ASRC_4: 443 case RT5677_ASRC_5: 444 case RT5677_ASRC_6: 445 case RT5677_ASRC_7: 446 case RT5677_ASRC_8: 447 case RT5677_ASRC_9: 448 case RT5677_ASRC_10: 449 case RT5677_ASRC_11: 450 case RT5677_ASRC_12: 451 case RT5677_ASRC_13: 452 case RT5677_ASRC_14: 453 case RT5677_ASRC_15: 454 case RT5677_ASRC_16: 455 case RT5677_ASRC_17: 456 case RT5677_ASRC_18: 457 case RT5677_ASRC_19: 458 case RT5677_ASRC_20: 459 case RT5677_ASRC_21: 460 case RT5677_ASRC_22: 461 case RT5677_ASRC_23: 462 case RT5677_VAD_CTRL1: 463 case RT5677_VAD_CTRL2: 464 case RT5677_VAD_CTRL3: 465 case RT5677_VAD_CTRL4: 466 case RT5677_VAD_CTRL5: 467 case RT5677_DSP_INB_CTRL1: 468 case RT5677_DSP_INB_CTRL2: 469 case RT5677_DSP_IN_OUTB_CTRL: 470 case RT5677_DSP_OUTB0_1_DIG_VOL: 471 case RT5677_DSP_OUTB2_3_DIG_VOL: 472 case RT5677_DSP_OUTB4_5_DIG_VOL: 473 case RT5677_DSP_OUTB6_7_DIG_VOL: 474 case RT5677_ADC_EQ_CTRL1: 475 case RT5677_ADC_EQ_CTRL2: 476 case RT5677_EQ_CTRL1: 477 case RT5677_EQ_CTRL2: 478 case RT5677_EQ_CTRL3: 479 case RT5677_SOFT_VOL_ZERO_CROSS1: 480 case RT5677_JD_CTRL1: 481 case RT5677_JD_CTRL2: 482 case RT5677_JD_CTRL3: 483 case RT5677_IRQ_CTRL1: 484 case RT5677_IRQ_CTRL2: 485 case RT5677_GPIO_ST: 486 case RT5677_GPIO_CTRL1: 487 case RT5677_GPIO_CTRL2: 488 case RT5677_GPIO_CTRL3: 489 case RT5677_STO1_ADC_HI_FILTER1: 490 case RT5677_STO1_ADC_HI_FILTER2: 491 case RT5677_MONO_ADC_HI_FILTER1: 492 case RT5677_MONO_ADC_HI_FILTER2: 493 case RT5677_STO2_ADC_HI_FILTER1: 494 case RT5677_STO2_ADC_HI_FILTER2: 495 case RT5677_STO3_ADC_HI_FILTER1: 496 case RT5677_STO3_ADC_HI_FILTER2: 497 case RT5677_STO4_ADC_HI_FILTER1: 498 case RT5677_STO4_ADC_HI_FILTER2: 499 case RT5677_MB_DRC_CTRL1: 500 case RT5677_DRC1_CTRL1: 501 case RT5677_DRC1_CTRL2: 502 case RT5677_DRC1_CTRL3: 503 case RT5677_DRC1_CTRL4: 504 case RT5677_DRC1_CTRL5: 505 case RT5677_DRC1_CTRL6: 506 case RT5677_DRC2_CTRL1: 507 case RT5677_DRC2_CTRL2: 508 case RT5677_DRC2_CTRL3: 509 case RT5677_DRC2_CTRL4: 510 case RT5677_DRC2_CTRL5: 511 case RT5677_DRC2_CTRL6: 512 case RT5677_DRC1_HL_CTRL1: 513 case RT5677_DRC1_HL_CTRL2: 514 case RT5677_DRC2_HL_CTRL1: 515 case RT5677_DRC2_HL_CTRL2: 516 case RT5677_DSP_INB1_SRC_CTRL1: 517 case RT5677_DSP_INB1_SRC_CTRL2: 518 case RT5677_DSP_INB1_SRC_CTRL3: 519 case RT5677_DSP_INB1_SRC_CTRL4: 520 case RT5677_DSP_INB2_SRC_CTRL1: 521 case RT5677_DSP_INB2_SRC_CTRL2: 522 case RT5677_DSP_INB2_SRC_CTRL3: 523 case RT5677_DSP_INB2_SRC_CTRL4: 524 case RT5677_DSP_INB3_SRC_CTRL1: 525 case RT5677_DSP_INB3_SRC_CTRL2: 526 case RT5677_DSP_INB3_SRC_CTRL3: 527 case RT5677_DSP_INB3_SRC_CTRL4: 528 case RT5677_DSP_OUTB1_SRC_CTRL1: 529 case RT5677_DSP_OUTB1_SRC_CTRL2: 530 case RT5677_DSP_OUTB1_SRC_CTRL3: 531 case RT5677_DSP_OUTB1_SRC_CTRL4: 532 case RT5677_DSP_OUTB2_SRC_CTRL1: 533 case RT5677_DSP_OUTB2_SRC_CTRL2: 534 case RT5677_DSP_OUTB2_SRC_CTRL3: 535 case RT5677_DSP_OUTB2_SRC_CTRL4: 536 case RT5677_DSP_OUTB_0123_MIXER_CTRL: 537 case RT5677_DSP_OUTB_45_MIXER_CTRL: 538 case RT5677_DSP_OUTB_67_MIXER_CTRL: 539 case RT5677_DIG_MISC: 540 case RT5677_GEN_CTRL1: 541 case RT5677_GEN_CTRL2: 542 case RT5677_VENDOR_ID: 543 case RT5677_VENDOR_ID1: 544 case RT5677_VENDOR_ID2: 545 return true; 546 default: 547 return false; 548 } 549} 550 551/** 552 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. 553 * @rt5677: Private Data. 554 * @addr: Address index. 555 * @value: Address data. 556 * @opcode: opcode value 557 * 558 * Returns 0 for success or negative error code. 559 */ 560static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, 561 unsigned int addr, unsigned int value, unsigned int opcode) 562{ 563 struct snd_soc_component *component = rt5677->component; 564 int ret; 565 566 mutex_lock(&rt5677->dsp_cmd_lock); 567 568 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 569 addr >> 16); 570 if (ret < 0) { 571 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 572 goto err; 573 } 574 575 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 576 addr & 0xffff); 577 if (ret < 0) { 578 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 579 goto err; 580 } 581 582 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, 583 value >> 16); 584 if (ret < 0) { 585 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); 586 goto err; 587 } 588 589 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, 590 value & 0xffff); 591 if (ret < 0) { 592 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); 593 goto err; 594 } 595 596 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 597 opcode); 598 if (ret < 0) { 599 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 600 goto err; 601 } 602 603err: 604 mutex_unlock(&rt5677->dsp_cmd_lock); 605 606 return ret; 607} 608 609/** 610 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. 611 * @rt5677: Private Data. 612 * @addr: Address index. 613 * @value: Address data. 614 * 615 * 616 * Returns 0 for success or negative error code. 617 */ 618static int rt5677_dsp_mode_i2c_read_addr( 619 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) 620{ 621 struct snd_soc_component *component = rt5677->component; 622 int ret; 623 unsigned int msb, lsb; 624 625 mutex_lock(&rt5677->dsp_cmd_lock); 626 627 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 628 addr >> 16); 629 if (ret < 0) { 630 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 631 goto err; 632 } 633 634 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 635 addr & 0xffff); 636 if (ret < 0) { 637 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 638 goto err; 639 } 640 641 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 642 0x0002); 643 if (ret < 0) { 644 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 645 goto err; 646 } 647 648 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); 649 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); 650 *value = (msb << 16) | lsb; 651 652err: 653 mutex_unlock(&rt5677->dsp_cmd_lock); 654 655 return ret; 656} 657 658/** 659 * rt5677_dsp_mode_i2c_write - Write register on DSP mode. 660 * @rt5677: Private Data. 661 * @reg: Register index. 662 * @value: Register data. 663 * 664 * 665 * Returns 0 for success or negative error code. 666 */ 667static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, 668 unsigned int reg, unsigned int value) 669{ 670 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, 671 value, 0x0001); 672} 673 674/** 675 * rt5677_dsp_mode_i2c_read - Read register on DSP mode. 676 * @rt5677: Private Data 677 * @reg: Register index. 678 * @value: Register data. 679 * 680 * 681 * Returns 0 for success or negative error code. 682 */ 683static int rt5677_dsp_mode_i2c_read( 684 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) 685{ 686 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, 687 value); 688 689 *value &= 0xffff; 690 691 return ret; 692} 693 694static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on) 695{ 696 if (on) { 697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 698 RT5677_PWR_DSP, RT5677_PWR_DSP); 699 rt5677->is_dsp_mode = true; 700 } else { 701 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 702 RT5677_PWR_DSP, 0x0); 703 rt5677->is_dsp_mode = false; 704 } 705} 706 707static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677) 708{ 709 struct snd_soc_dapm_context *dapm = 710 snd_soc_component_get_dapm(rt5677->component); 711 /* Force dapm to sync before we enable the 712 * DSP to prevent write corruption 713 */ 714 snd_soc_dapm_sync(dapm); 715 716 /* DMIC1 power = enabled 717 * DMIC CLK = 256 * fs / 12 718 */ 719 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 720 RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT); 721 722 /* I2S pre divide 2 = /6 (clk_sys2) */ 723 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 724 RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6); 725 726 /* DSP Clock = MCLK1 (bypassed PLL2) */ 727 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, 728 RT5677_DSP_CLK_SRC_BYPASS); 729 730 /* SAD Threshold1 */ 731 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f); 732 /* SAD Threshold2 */ 733 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5); 734 /* SAD Sample Rate Converter = Up 6 (8K to 48K) 735 * SAD Output Sample Rate = Same as I2S 736 * SAD Threshold3 737 */ 738 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4, 739 RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK | 740 RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT); 741 /* Minimum frame level within a pre-determined duration = 32 frames 742 * Bypass ADPCM Encoder/Decoder = Bypass ADPCM 743 * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable 744 * SAD Buffer Over-Writing = enable 745 * SAD Buffer Pop Mode Control = disable 746 * SAD Buffer Push Mode Control = enable 747 * SAD Detector Control = enable 748 * SAD Function Control = enable 749 * SAD Function Reset = normal 750 */ 751 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 752 RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE | 753 RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH | 754 RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC | 755 RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT); 756 757 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it 758 * is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save 759 * power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack 760 * Detection" for more info. 761 */ 762 763 /* Private register, no doc */ 764 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, 765 0x0f00, 0x0100); 766 767 /* LDO2 output = 1.2V 768 * LDO1 output = 1.2V (LDO_IN = 1.8V) 769 */ 770 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 771 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 772 5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT); 773 774 /* Codec core power = power on 775 * LDO1 power = power on 776 */ 777 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 778 RT5677_PWR_CORE | RT5677_PWR_LDO1, 779 RT5677_PWR_CORE | RT5677_PWR_LDO1); 780 781 /* Isolation for DCVDD4 = normal (set during probe) 782 * Isolation for DCVDD2 = normal (set during probe) 783 * Isolation for DSP = normal 784 * Isolation for Band 0~7 = disable 785 * Isolation for InBound 4~10 and OutBound 4~10 = disable 786 */ 787 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 788 RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO | 789 RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO | 790 RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO | 791 RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO | 792 RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO | 793 RT5677_PWR_MLT_ISO); 794 795 /* System Band 0~7 = power on 796 * InBound 4~10 and OutBound 4~10 = power on 797 * DSP = power on 798 * DSP CPU = stop (will be set to "run" after firmware loaded) 799 */ 800 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 801 RT5677_PWR_SR7 | RT5677_PWR_SR6 | 802 RT5677_PWR_SR5 | RT5677_PWR_SR4 | 803 RT5677_PWR_SR3 | RT5677_PWR_SR2 | 804 RT5677_PWR_SR1 | RT5677_PWR_SR0 | 805 RT5677_PWR_MLT | RT5677_PWR_DSP | 806 RT5677_PWR_DSP_CPU); 807 808 return 0; 809} 810 811static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf, 812 unsigned int len) 813{ 814 struct snd_soc_component *component = rt5677->component; 815 Elf32_Ehdr *elf_hdr; 816 Elf32_Phdr *pr_hdr; 817 Elf32_Half i; 818 int ret = 0; 819 820 if (!buf || (len < sizeof(Elf32_Ehdr))) 821 return -ENOMEM; 822 823 elf_hdr = (Elf32_Ehdr *)buf; 824#ifndef EM_XTENSA 825#define EM_XTENSA 94 826#endif 827 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1)) 828 dev_err(component->dev, "Wrong ELF header prefix\n"); 829 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr)) 830 dev_err(component->dev, "Wrong ELF header size\n"); 831 if (elf_hdr->e_machine != EM_XTENSA) 832 dev_err(component->dev, "Wrong DSP code file\n"); 833 834 if (len < elf_hdr->e_phoff) 835 return -ENOMEM; 836 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff); 837 for (i = 0; i < elf_hdr->e_phnum; i++) { 838 /* TODO: handle p_memsz != p_filesz */ 839 if (pr_hdr->p_paddr && pr_hdr->p_filesz) { 840 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n", 841 pr_hdr->p_filesz, pr_hdr->p_paddr); 842 843 ret = rt5677_spi_write(pr_hdr->p_paddr, 844 buf + pr_hdr->p_offset, 845 pr_hdr->p_filesz); 846 if (ret) 847 dev_err(component->dev, "Load firmware failed %d\n", 848 ret); 849 } 850 pr_hdr++; 851 } 852 return ret; 853} 854 855static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677) 856{ 857 const struct firmware *fwp; 858 struct device *dev = rt5677->component->dev; 859 int ret = 0; 860 861 /* Load dsp firmware from rt5677_elf_vad file */ 862 ret = request_firmware(&fwp, "rt5677_elf_vad", dev); 863 if (ret) { 864 dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret); 865 return ret; 866 } 867 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size); 868 869 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size); 870 release_firmware(fwp); 871 return ret; 872} 873 874static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on) 875{ 876 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 877 rt5677->dsp_vad_en_request = on; 878 rt5677->dsp_vad_en = on; 879 880 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) 881 return -ENXIO; 882 883 schedule_delayed_work(&rt5677->dsp_work, 0); 884 return 0; 885} 886 887static void rt5677_dsp_work(struct work_struct *work) 888{ 889 struct rt5677_priv *rt5677 = 890 container_of(work, struct rt5677_priv, dsp_work.work); 891 static bool activity; 892 bool enable = rt5677->dsp_vad_en; 893 int i, val; 894 895 896 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", 897 enable, activity); 898 899 if (enable && !activity) { 900 activity = true; 901 902 /* Before a hotword is detected, GPIO1 pin is configured as IRQ 903 * output so that jack detect works. When a hotword is detected, 904 * the DSP firmware configures the GPIO1 pin as GPIO1 and 905 * drives a 1. rt5677_irq() is called after a rising edge on 906 * the GPIO1 pin, due to either jack detect event or hotword 907 * event, or both. All possible events are checked and handled 908 * in rt5677_irq() where GPIO1 pin is configured back to IRQ 909 * output if a hotword is detected. 910 */ 911 912 rt5677_set_vad_source(rt5677); 913 rt5677_set_dsp_mode(rt5677, true); 914 915#define RT5677_BOOT_RETRY 20 916 for (i = 0; i < RT5677_BOOT_RETRY; i++) { 917 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val); 918 if (val == 0x3ff) 919 break; 920 udelay(500); 921 } 922 if (i == RT5677_BOOT_RETRY && val != 0x3ff) { 923 dev_err(rt5677->component->dev, "DSP Boot Timed Out!"); 924 return; 925 } 926 927 /* Boot the firmware from IRAM instead of SRAM0. */ 928 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 929 0x0009, 0x0003); 930 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 931 0x0019, 0x0003); 932 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 933 0x0009, 0x0003); 934 935 rt5677_load_dsp_from_file(rt5677); 936 937 /* Set DSP CPU to Run */ 938 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 939 RT5677_PWR_DSP_CPU, 0x0); 940 } else if (!enable && activity) { 941 activity = false; 942 943 /* Don't turn off the DSP while handling irqs */ 944 mutex_lock(&rt5677->irq_lock); 945 /* Set DSP CPU to Stop */ 946 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 947 RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU); 948 949 rt5677_set_dsp_mode(rt5677, false); 950 951 /* Disable and clear VAD interrupt */ 952 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); 953 954 /* Set GPIO1 pin back to be IRQ output for jack detect */ 955 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 956 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 957 958 mutex_unlock(&rt5677->irq_lock); 959 } 960} 961 962static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 963static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 964static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 965static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 966 967/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 968static const DECLARE_TLV_DB_RANGE(bst_tlv, 969 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 970 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 971 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 972 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 973 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 974 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 975 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 976); 977 978static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, 979 struct snd_ctl_elem_value *ucontrol) 980{ 981 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 982 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 983 984 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request; 985 986 return 0; 987} 988 989static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, 990 struct snd_ctl_elem_value *ucontrol) 991{ 992 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 993 994 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]); 995 996 return 0; 997} 998 999static const struct snd_kcontrol_new rt5677_snd_controls[] = { 1000 /* OUTPUT Control */ 1001 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 1002 RT5677_LOUT1_L_MUTE_SFT, 1, 1), 1003 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, 1004 RT5677_LOUT2_L_MUTE_SFT, 1, 1), 1005 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, 1006 RT5677_LOUT3_L_MUTE_SFT, 1, 1), 1007 1008 /* DAC Digital Volume */ 1009 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 1010 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1011 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 1012 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1013 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 1014 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1015 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 1016 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1017 1018 /* IN1/IN2 Control */ 1019 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 1020 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), 1021 1022 /* ADC Digital Volume Control */ 1023 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, 1024 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1025 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, 1026 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1027 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, 1028 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1029 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, 1030 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1031 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, 1032 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1033 1034 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 1035 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1036 adc_vol_tlv), 1037 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 1038 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1039 adc_vol_tlv), 1040 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 1041 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1042 adc_vol_tlv), 1043 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 1044 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1045 adc_vol_tlv), 1046 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 1047 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, 1048 adc_vol_tlv), 1049 1050 /* Sidetone Control */ 1051 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, 1052 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), 1053 1054 /* ADC Boost Volume Control */ 1055 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1056 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 1057 adc_bst_tlv), 1058 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1059 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 1060 adc_bst_tlv), 1061 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1062 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 1063 adc_bst_tlv), 1064 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1065 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 1066 adc_bst_tlv), 1067 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 1068 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 1069 adc_bst_tlv), 1070 1071 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, 1072 rt5677_dsp_vad_get, rt5677_dsp_vad_put), 1073}; 1074 1075/** 1076 * set_dmic_clk - Set parameter of dmic. 1077 * 1078 * @w: DAPM widget. 1079 * @kcontrol: The kcontrol of this widget. 1080 * @event: Event id. 1081 * 1082 * Choose dmic clock between 1MHz and 3MHz. 1083 * It is better for clock to approximate 3MHz. 1084 */ 1085static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1086 struct snd_kcontrol *kcontrol, int event) 1087{ 1088 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1089 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1090 int idx, rate; 1091 1092 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, 1093 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT); 1094 idx = rl6231_calc_dmic_clk(rate); 1095 if (idx < 0) 1096 dev_err(component->dev, "Failed to set DMIC clock\n"); 1097 else 1098 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 1099 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); 1100 return idx; 1101} 1102 1103static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 1104 struct snd_soc_dapm_widget *sink) 1105{ 1106 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1107 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1108 unsigned int val; 1109 1110 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); 1111 val &= RT5677_SCLK_SRC_MASK; 1112 if (val == RT5677_SCLK_SRC_PLL1) 1113 return 1; 1114 else 1115 return 0; 1116} 1117 1118static int is_using_asrc(struct snd_soc_dapm_widget *source, 1119 struct snd_soc_dapm_widget *sink) 1120{ 1121 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1122 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1123 unsigned int reg, shift, val; 1124 1125 if (source->reg == RT5677_ASRC_1) { 1126 switch (source->shift) { 1127 case 12: 1128 reg = RT5677_ASRC_4; 1129 shift = 0; 1130 break; 1131 case 13: 1132 reg = RT5677_ASRC_4; 1133 shift = 4; 1134 break; 1135 case 14: 1136 reg = RT5677_ASRC_4; 1137 shift = 8; 1138 break; 1139 case 15: 1140 reg = RT5677_ASRC_4; 1141 shift = 12; 1142 break; 1143 default: 1144 return 0; 1145 } 1146 } else { 1147 switch (source->shift) { 1148 case 0: 1149 reg = RT5677_ASRC_6; 1150 shift = 8; 1151 break; 1152 case 1: 1153 reg = RT5677_ASRC_6; 1154 shift = 12; 1155 break; 1156 case 2: 1157 reg = RT5677_ASRC_5; 1158 shift = 0; 1159 break; 1160 case 3: 1161 reg = RT5677_ASRC_5; 1162 shift = 4; 1163 break; 1164 case 4: 1165 reg = RT5677_ASRC_5; 1166 shift = 8; 1167 break; 1168 case 5: 1169 reg = RT5677_ASRC_5; 1170 shift = 12; 1171 break; 1172 case 12: 1173 reg = RT5677_ASRC_3; 1174 shift = 0; 1175 break; 1176 case 13: 1177 reg = RT5677_ASRC_3; 1178 shift = 4; 1179 break; 1180 case 14: 1181 reg = RT5677_ASRC_3; 1182 shift = 12; 1183 break; 1184 default: 1185 return 0; 1186 } 1187 } 1188 1189 regmap_read(rt5677->regmap, reg, &val); 1190 val = (val >> shift) & 0xf; 1191 1192 switch (val) { 1193 case 1 ... 6: 1194 return 1; 1195 default: 1196 return 0; 1197 } 1198 1199} 1200 1201static int can_use_asrc(struct snd_soc_dapm_widget *source, 1202 struct snd_soc_dapm_widget *sink) 1203{ 1204 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1205 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1206 1207 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) 1208 return 1; 1209 1210 return 0; 1211} 1212 1213/** 1214 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters 1215 * @component: SoC audio component device. 1216 * @filter_mask: mask of filters. 1217 * @clk_src: clock source 1218 * 1219 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can 1220 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1221 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1222 * ASRC function will track i2s clock and generate a corresponding system clock 1223 * for codec. This function provides an API to select the clock source for a 1224 * set of filters specified by the mask. And the codec driver will turn on ASRC 1225 * for these filters if ASRC is selected as their clock source. 1226 */ 1227int rt5677_sel_asrc_clk_src(struct snd_soc_component *component, 1228 unsigned int filter_mask, unsigned int clk_src) 1229{ 1230 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1231 unsigned int asrc3_mask = 0, asrc3_value = 0; 1232 unsigned int asrc4_mask = 0, asrc4_value = 0; 1233 unsigned int asrc5_mask = 0, asrc5_value = 0; 1234 unsigned int asrc6_mask = 0, asrc6_value = 0; 1235 unsigned int asrc7_mask = 0, asrc7_value = 0; 1236 unsigned int asrc8_mask = 0, asrc8_value = 0; 1237 1238 switch (clk_src) { 1239 case RT5677_CLK_SEL_SYS: 1240 case RT5677_CLK_SEL_I2S1_ASRC: 1241 case RT5677_CLK_SEL_I2S2_ASRC: 1242 case RT5677_CLK_SEL_I2S3_ASRC: 1243 case RT5677_CLK_SEL_I2S4_ASRC: 1244 case RT5677_CLK_SEL_I2S5_ASRC: 1245 case RT5677_CLK_SEL_I2S6_ASRC: 1246 case RT5677_CLK_SEL_SYS2: 1247 case RT5677_CLK_SEL_SYS3: 1248 case RT5677_CLK_SEL_SYS4: 1249 case RT5677_CLK_SEL_SYS5: 1250 case RT5677_CLK_SEL_SYS6: 1251 case RT5677_CLK_SEL_SYS7: 1252 break; 1253 1254 default: 1255 return -EINVAL; 1256 } 1257 1258 /* ASRC 3 */ 1259 if (filter_mask & RT5677_DA_STEREO_FILTER) { 1260 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK; 1261 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK) 1262 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT); 1263 } 1264 1265 if (filter_mask & RT5677_DA_MONO2_L_FILTER) { 1266 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK; 1267 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK) 1268 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT); 1269 } 1270 1271 if (filter_mask & RT5677_DA_MONO2_R_FILTER) { 1272 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK; 1273 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK) 1274 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT); 1275 } 1276 1277 if (asrc3_mask) 1278 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, 1279 asrc3_value); 1280 1281 /* ASRC 4 */ 1282 if (filter_mask & RT5677_DA_MONO3_L_FILTER) { 1283 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK; 1284 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK) 1285 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT); 1286 } 1287 1288 if (filter_mask & RT5677_DA_MONO3_R_FILTER) { 1289 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK; 1290 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK) 1291 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT); 1292 } 1293 1294 if (filter_mask & RT5677_DA_MONO4_L_FILTER) { 1295 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK; 1296 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK) 1297 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT); 1298 } 1299 1300 if (filter_mask & RT5677_DA_MONO4_R_FILTER) { 1301 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK; 1302 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK) 1303 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT); 1304 } 1305 1306 if (asrc4_mask) 1307 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, 1308 asrc4_value); 1309 1310 /* ASRC 5 */ 1311 if (filter_mask & RT5677_AD_STEREO1_FILTER) { 1312 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK; 1313 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK) 1314 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT); 1315 } 1316 1317 if (filter_mask & RT5677_AD_STEREO2_FILTER) { 1318 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK; 1319 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK) 1320 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT); 1321 } 1322 1323 if (filter_mask & RT5677_AD_STEREO3_FILTER) { 1324 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK; 1325 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK) 1326 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT); 1327 } 1328 1329 if (filter_mask & RT5677_AD_STEREO4_FILTER) { 1330 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK; 1331 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK) 1332 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT); 1333 } 1334 1335 if (asrc5_mask) 1336 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, 1337 asrc5_value); 1338 1339 /* ASRC 6 */ 1340 if (filter_mask & RT5677_AD_MONO_L_FILTER) { 1341 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK; 1342 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK) 1343 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT); 1344 } 1345 1346 if (filter_mask & RT5677_AD_MONO_R_FILTER) { 1347 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK; 1348 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK) 1349 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT); 1350 } 1351 1352 if (asrc6_mask) 1353 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, 1354 asrc6_value); 1355 1356 /* ASRC 7 */ 1357 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) { 1358 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK; 1359 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK) 1360 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT); 1361 } 1362 1363 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) { 1364 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK; 1365 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK) 1366 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT); 1367 } 1368 1369 if (asrc7_mask) 1370 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, 1371 asrc7_value); 1372 1373 /* ASRC 8 */ 1374 if (filter_mask & RT5677_I2S1_SOURCE) { 1375 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK; 1376 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK) 1377 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); 1378 } 1379 1380 if (filter_mask & RT5677_I2S2_SOURCE) { 1381 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK; 1382 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK) 1383 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); 1384 } 1385 1386 if (filter_mask & RT5677_I2S3_SOURCE) { 1387 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK; 1388 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK) 1389 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); 1390 } 1391 1392 if (filter_mask & RT5677_I2S4_SOURCE) { 1393 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK; 1394 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK) 1395 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); 1396 } 1397 1398 if (asrc8_mask) 1399 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, 1400 asrc8_value); 1401 1402 return 0; 1403} 1404EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src); 1405 1406static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source, 1407 struct snd_soc_dapm_widget *sink) 1408{ 1409 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1410 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1411 unsigned int asrc_setting; 1412 1413 switch (source->shift) { 1414 case 11: 1415 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1416 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >> 1417 RT5677_AD_STO1_CLK_SEL_SFT; 1418 break; 1419 1420 case 10: 1421 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1422 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >> 1423 RT5677_AD_STO2_CLK_SEL_SFT; 1424 break; 1425 1426 case 9: 1427 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1428 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >> 1429 RT5677_AD_STO3_CLK_SEL_SFT; 1430 break; 1431 1432 case 8: 1433 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1434 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >> 1435 RT5677_AD_STO4_CLK_SEL_SFT; 1436 break; 1437 1438 case 7: 1439 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1440 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >> 1441 RT5677_AD_MONOL_CLK_SEL_SFT; 1442 break; 1443 1444 case 6: 1445 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1446 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >> 1447 RT5677_AD_MONOR_CLK_SEL_SFT; 1448 break; 1449 1450 default: 1451 return 0; 1452 } 1453 1454 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC && 1455 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC) 1456 return 1; 1457 1458 return 0; 1459} 1460 1461/* Digital Mixer */ 1462static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 1463 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1464 RT5677_M_STO1_ADC_L1_SFT, 1, 1), 1465 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1466 RT5677_M_STO1_ADC_L2_SFT, 1, 1), 1467}; 1468 1469static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { 1470 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1471 RT5677_M_STO1_ADC_R1_SFT, 1, 1), 1472 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1473 RT5677_M_STO1_ADC_R2_SFT, 1, 1), 1474}; 1475 1476static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { 1477 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1478 RT5677_M_STO2_ADC_L1_SFT, 1, 1), 1479 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1480 RT5677_M_STO2_ADC_L2_SFT, 1, 1), 1481}; 1482 1483static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { 1484 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1485 RT5677_M_STO2_ADC_R1_SFT, 1, 1), 1486 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1487 RT5677_M_STO2_ADC_R2_SFT, 1, 1), 1488}; 1489 1490static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { 1491 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1492 RT5677_M_STO3_ADC_L1_SFT, 1, 1), 1493 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1494 RT5677_M_STO3_ADC_L2_SFT, 1, 1), 1495}; 1496 1497static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { 1498 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1499 RT5677_M_STO3_ADC_R1_SFT, 1, 1), 1500 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1501 RT5677_M_STO3_ADC_R2_SFT, 1, 1), 1502}; 1503 1504static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { 1505 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1506 RT5677_M_STO4_ADC_L1_SFT, 1, 1), 1507 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1508 RT5677_M_STO4_ADC_L2_SFT, 1, 1), 1509}; 1510 1511static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { 1512 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1513 RT5677_M_STO4_ADC_R1_SFT, 1, 1), 1514 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1515 RT5677_M_STO4_ADC_R2_SFT, 1, 1), 1516}; 1517 1518static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { 1519 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1520 RT5677_M_MONO_ADC_L1_SFT, 1, 1), 1521 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1522 RT5677_M_MONO_ADC_L2_SFT, 1, 1), 1523}; 1524 1525static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { 1526 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1527 RT5677_M_MONO_ADC_R1_SFT, 1, 1), 1528 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1529 RT5677_M_MONO_ADC_R2_SFT, 1, 1), 1530}; 1531 1532static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { 1533 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1534 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), 1535 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1536 RT5677_M_DAC1_L_SFT, 1, 1), 1537}; 1538 1539static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { 1540 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1541 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), 1542 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1543 RT5677_M_DAC1_R_SFT, 1, 1), 1544}; 1545 1546static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { 1547 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER, 1548 RT5677_M_ST_DAC1_L_SFT, 1, 1), 1549 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1550 RT5677_M_DAC1_L_STO_L_SFT, 1, 1), 1551 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, 1552 RT5677_M_DAC2_L_STO_L_SFT, 1, 1), 1553 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1554 RT5677_M_DAC1_R_STO_L_SFT, 1, 1), 1555}; 1556 1557static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { 1558 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER, 1559 RT5677_M_ST_DAC1_R_SFT, 1, 1), 1560 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1561 RT5677_M_DAC1_R_STO_R_SFT, 1, 1), 1562 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, 1563 RT5677_M_DAC2_R_STO_R_SFT, 1, 1), 1564 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1565 RT5677_M_DAC1_L_STO_R_SFT, 1, 1), 1566}; 1567 1568static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { 1569 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER, 1570 RT5677_M_ST_DAC2_L_SFT, 1, 1), 1571 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, 1572 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), 1573 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1574 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), 1575 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1576 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), 1577}; 1578 1579static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { 1580 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER, 1581 RT5677_M_ST_DAC2_R_SFT, 1, 1), 1582 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, 1583 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), 1584 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1585 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), 1586 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1587 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), 1588}; 1589 1590static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { 1591 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, 1592 RT5677_M_STO_L_DD1_L_SFT, 1, 1), 1593 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, 1594 RT5677_M_MONO_L_DD1_L_SFT, 1, 1), 1595 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1596 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), 1597 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1598 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), 1599}; 1600 1601static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { 1602 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, 1603 RT5677_M_STO_R_DD1_R_SFT, 1, 1), 1604 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, 1605 RT5677_M_MONO_R_DD1_R_SFT, 1, 1), 1606 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1607 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), 1608 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1609 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), 1610}; 1611 1612static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { 1613 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, 1614 RT5677_M_STO_L_DD2_L_SFT, 1, 1), 1615 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, 1616 RT5677_M_MONO_L_DD2_L_SFT, 1, 1), 1617 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1618 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), 1619 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1620 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), 1621}; 1622 1623static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { 1624 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, 1625 RT5677_M_STO_R_DD2_R_SFT, 1, 1), 1626 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, 1627 RT5677_M_MONO_R_DD2_R_SFT, 1, 1), 1628 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1629 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), 1630 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1631 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), 1632}; 1633 1634static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { 1635 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1636 RT5677_DSP_IB_01_H_SFT, 1, 1), 1637 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1638 RT5677_DSP_IB_23_H_SFT, 1, 1), 1639 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1640 RT5677_DSP_IB_45_H_SFT, 1, 1), 1641 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1642 RT5677_DSP_IB_6_H_SFT, 1, 1), 1643 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1644 RT5677_DSP_IB_7_H_SFT, 1, 1), 1645 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1646 RT5677_DSP_IB_8_H_SFT, 1, 1), 1647 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1648 RT5677_DSP_IB_9_H_SFT, 1, 1), 1649}; 1650 1651static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { 1652 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1653 RT5677_DSP_IB_01_L_SFT, 1, 1), 1654 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1655 RT5677_DSP_IB_23_L_SFT, 1, 1), 1656 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1657 RT5677_DSP_IB_45_L_SFT, 1, 1), 1658 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1659 RT5677_DSP_IB_6_L_SFT, 1, 1), 1660 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1661 RT5677_DSP_IB_7_L_SFT, 1, 1), 1662 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1663 RT5677_DSP_IB_8_L_SFT, 1, 1), 1664 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1665 RT5677_DSP_IB_9_L_SFT, 1, 1), 1666}; 1667 1668static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { 1669 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1670 RT5677_DSP_IB_01_H_SFT, 1, 1), 1671 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1672 RT5677_DSP_IB_23_H_SFT, 1, 1), 1673 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1674 RT5677_DSP_IB_45_H_SFT, 1, 1), 1675 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1676 RT5677_DSP_IB_6_H_SFT, 1, 1), 1677 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1678 RT5677_DSP_IB_7_H_SFT, 1, 1), 1679 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1680 RT5677_DSP_IB_8_H_SFT, 1, 1), 1681 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1682 RT5677_DSP_IB_9_H_SFT, 1, 1), 1683}; 1684 1685static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { 1686 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1687 RT5677_DSP_IB_01_L_SFT, 1, 1), 1688 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1689 RT5677_DSP_IB_23_L_SFT, 1, 1), 1690 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1691 RT5677_DSP_IB_45_L_SFT, 1, 1), 1692 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1693 RT5677_DSP_IB_6_L_SFT, 1, 1), 1694 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1695 RT5677_DSP_IB_7_L_SFT, 1, 1), 1696 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1697 RT5677_DSP_IB_8_L_SFT, 1, 1), 1698 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1699 RT5677_DSP_IB_9_L_SFT, 1, 1), 1700}; 1701 1702static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { 1703 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1704 RT5677_DSP_IB_01_H_SFT, 1, 1), 1705 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1706 RT5677_DSP_IB_23_H_SFT, 1, 1), 1707 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1708 RT5677_DSP_IB_45_H_SFT, 1, 1), 1709 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1710 RT5677_DSP_IB_6_H_SFT, 1, 1), 1711 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1712 RT5677_DSP_IB_7_H_SFT, 1, 1), 1713 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1714 RT5677_DSP_IB_8_H_SFT, 1, 1), 1715 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1716 RT5677_DSP_IB_9_H_SFT, 1, 1), 1717}; 1718 1719static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { 1720 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1721 RT5677_DSP_IB_01_L_SFT, 1, 1), 1722 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1723 RT5677_DSP_IB_23_L_SFT, 1, 1), 1724 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1725 RT5677_DSP_IB_45_L_SFT, 1, 1), 1726 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1727 RT5677_DSP_IB_6_L_SFT, 1, 1), 1728 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1729 RT5677_DSP_IB_7_L_SFT, 1, 1), 1730 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1731 RT5677_DSP_IB_8_L_SFT, 1, 1), 1732 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1733 RT5677_DSP_IB_9_L_SFT, 1, 1), 1734}; 1735 1736 1737/* Mux */ 1738/* DAC1 L/R Source */ /* MX-29 [10:8] */ 1739static const char * const rt5677_dac1_src[] = { 1740 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 1741 "OB 01" 1742}; 1743 1744static SOC_ENUM_SINGLE_DECL( 1745 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1746 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 1747 1748static const struct snd_kcontrol_new rt5677_dac1_mux = 1749 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); 1750 1751/* ADDA1 L/R Source */ /* MX-29 [1:0] */ 1752static const char * const rt5677_adda1_src[] = { 1753 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 1754}; 1755 1756static SOC_ENUM_SINGLE_DECL( 1757 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1758 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 1759 1760static const struct snd_kcontrol_new rt5677_adda1_mux = 1761 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); 1762 1763 1764/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ 1765static const char * const rt5677_dac2l_src[] = { 1766 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 1767 "OB 2", 1768}; 1769 1770static SOC_ENUM_SINGLE_DECL( 1771 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, 1772 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 1773 1774static const struct snd_kcontrol_new rt5677_dac2_l_mux = 1775 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); 1776 1777static const char * const rt5677_dac2r_src[] = { 1778 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 1779 "OB 3", "Haptic Generator", "VAD ADC" 1780}; 1781 1782static SOC_ENUM_SINGLE_DECL( 1783 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, 1784 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 1785 1786static const struct snd_kcontrol_new rt5677_dac2_r_mux = 1787 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); 1788 1789/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ 1790static const char * const rt5677_dac3l_src[] = { 1791 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 1792 "SLB DAC 4", "OB 4" 1793}; 1794 1795static SOC_ENUM_SINGLE_DECL( 1796 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1797 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1798 1799static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1800 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); 1801 1802static const char * const rt5677_dac3r_src[] = { 1803 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1804 "SLB DAC 5", "OB 5" 1805}; 1806 1807static SOC_ENUM_SINGLE_DECL( 1808 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1809 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1810 1811static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1812 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); 1813 1814/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ 1815static const char * const rt5677_dac4l_src[] = { 1816 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1817 "SLB DAC 6", "OB 6" 1818}; 1819 1820static SOC_ENUM_SINGLE_DECL( 1821 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1822 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1823 1824static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1825 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); 1826 1827static const char * const rt5677_dac4r_src[] = { 1828 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1829 "SLB DAC 7", "OB 7" 1830}; 1831 1832static SOC_ENUM_SINGLE_DECL( 1833 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1834 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1835 1836static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1837 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); 1838 1839/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1840static const char * const rt5677_iob_bypass_src[] = { 1841 "Bypass", "Pass SRC" 1842}; 1843 1844static SOC_ENUM_SINGLE_DECL( 1845 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1846 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1847 1848static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1849 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); 1850 1851static SOC_ENUM_SINGLE_DECL( 1852 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1853 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1854 1855static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1856 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); 1857 1858static SOC_ENUM_SINGLE_DECL( 1859 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1860 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1861 1862static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1863 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); 1864 1865static SOC_ENUM_SINGLE_DECL( 1866 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1867 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1868 1869static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1870 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); 1871 1872static SOC_ENUM_SINGLE_DECL( 1873 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1874 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1875 1876static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1877 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1878 1879/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1880static const char * const rt5677_stereo_adc2_src[] = { 1881 "DD MIX1", "DMIC", "Stereo DAC MIX" 1882}; 1883 1884static SOC_ENUM_SINGLE_DECL( 1885 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, 1886 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1887 1888static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1889 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); 1890 1891static SOC_ENUM_SINGLE_DECL( 1892 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1893 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1894 1895static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1896 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); 1897 1898static SOC_ENUM_SINGLE_DECL( 1899 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1900 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1901 1902static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1903 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); 1904 1905/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1906static const char * const rt5677_dmic_src[] = { 1907 "DMIC1", "DMIC2", "DMIC3", "DMIC4" 1908}; 1909 1910static SOC_ENUM_SINGLE_DECL( 1911 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, 1912 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1913 1914static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1915 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); 1916 1917static SOC_ENUM_SINGLE_DECL( 1918 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1919 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1920 1921static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1922 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); 1923 1924static SOC_ENUM_SINGLE_DECL( 1925 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1926 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1927 1928static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1929 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); 1930 1931static SOC_ENUM_SINGLE_DECL( 1932 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1933 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1934 1935static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1936 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); 1937 1938static SOC_ENUM_SINGLE_DECL( 1939 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1940 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1941 1942static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1943 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); 1944 1945static SOC_ENUM_SINGLE_DECL( 1946 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1947 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1948 1949static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1950 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); 1951 1952/* Stereo2 ADC Source */ /* MX-26 [0] */ 1953static const char * const rt5677_stereo2_adc_lr_src[] = { 1954 "L", "LR" 1955}; 1956 1957static SOC_ENUM_SINGLE_DECL( 1958 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, 1959 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1960 1961static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1962 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1963 1964/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1965static const char * const rt5677_stereo_adc1_src[] = { 1966 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1967}; 1968 1969static SOC_ENUM_SINGLE_DECL( 1970 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, 1971 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1972 1973static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1974 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); 1975 1976static SOC_ENUM_SINGLE_DECL( 1977 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1978 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1979 1980static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1981 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); 1982 1983static SOC_ENUM_SINGLE_DECL( 1984 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1985 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1986 1987static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1988 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); 1989 1990/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ 1991static const char * const rt5677_mono_adc2_l_src[] = { 1992 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1993}; 1994 1995static SOC_ENUM_SINGLE_DECL( 1996 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, 1997 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 1998 1999static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 2000 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); 2001 2002/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ 2003static const char * const rt5677_mono_adc1_l_src[] = { 2004 "DD MIX1L", "ADC1", "MONO DAC MIXL" 2005}; 2006 2007static SOC_ENUM_SINGLE_DECL( 2008 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, 2009 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 2010 2011static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 2012 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); 2013 2014/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ 2015static const char * const rt5677_mono_adc2_r_src[] = { 2016 "DD MIX1R", "DMIC", "MONO DAC MIXR" 2017}; 2018 2019static SOC_ENUM_SINGLE_DECL( 2020 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, 2021 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 2022 2023static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 2024 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); 2025 2026/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ 2027static const char * const rt5677_mono_adc1_r_src[] = { 2028 "DD MIX1R", "ADC2", "MONO DAC MIXR" 2029}; 2030 2031static SOC_ENUM_SINGLE_DECL( 2032 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, 2033 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 2034 2035static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 2036 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); 2037 2038/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 2039static const char * const rt5677_stereo4_adc2_src[] = { 2040 "DD MIX1", "DMIC", "DD MIX2" 2041}; 2042 2043static SOC_ENUM_SINGLE_DECL( 2044 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, 2045 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 2046 2047static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 2048 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); 2049 2050 2051/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 2052static const char * const rt5677_stereo4_adc1_src[] = { 2053 "DD MIX1", "ADC1/2", "DD MIX2" 2054}; 2055 2056static SOC_ENUM_SINGLE_DECL( 2057 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, 2058 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 2059 2060static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 2061 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); 2062 2063/* InBound0/1 Source */ /* MX-A3 [14:12] */ 2064static const char * const rt5677_inbound01_src[] = { 2065 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", 2066 "VAD ADC/DAC1 FS" 2067}; 2068 2069static SOC_ENUM_SINGLE_DECL( 2070 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, 2071 RT5677_IB01_SRC_SFT, rt5677_inbound01_src); 2072 2073static const struct snd_kcontrol_new rt5677_ib01_src_mux = 2074 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); 2075 2076/* InBound2/3 Source */ /* MX-A3 [10:8] */ 2077static const char * const rt5677_inbound23_src[] = { 2078 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", 2079 "DAC1 FS", "IF4 DAC" 2080}; 2081 2082static SOC_ENUM_SINGLE_DECL( 2083 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, 2084 RT5677_IB23_SRC_SFT, rt5677_inbound23_src); 2085 2086static const struct snd_kcontrol_new rt5677_ib23_src_mux = 2087 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); 2088 2089/* InBound4/5 Source */ /* MX-A3 [6:4] */ 2090static const char * const rt5677_inbound45_src[] = { 2091 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", 2092 "IF3 DAC" 2093}; 2094 2095static SOC_ENUM_SINGLE_DECL( 2096 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, 2097 RT5677_IB45_SRC_SFT, rt5677_inbound45_src); 2098 2099static const struct snd_kcontrol_new rt5677_ib45_src_mux = 2100 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); 2101 2102/* InBound6 Source */ /* MX-A3 [2:0] */ 2103static const char * const rt5677_inbound6_src[] = { 2104 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", 2105 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" 2106}; 2107 2108static SOC_ENUM_SINGLE_DECL( 2109 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, 2110 RT5677_IB6_SRC_SFT, rt5677_inbound6_src); 2111 2112static const struct snd_kcontrol_new rt5677_ib6_src_mux = 2113 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); 2114 2115/* InBound7 Source */ /* MX-A4 [14:12] */ 2116static const char * const rt5677_inbound7_src[] = { 2117 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", 2118 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" 2119}; 2120 2121static SOC_ENUM_SINGLE_DECL( 2122 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, 2123 RT5677_IB7_SRC_SFT, rt5677_inbound7_src); 2124 2125static const struct snd_kcontrol_new rt5677_ib7_src_mux = 2126 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); 2127 2128/* InBound8 Source */ /* MX-A4 [10:8] */ 2129static const char * const rt5677_inbound8_src[] = { 2130 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", 2131 "MONO ADC MIX L", "DACL1 FS" 2132}; 2133 2134static SOC_ENUM_SINGLE_DECL( 2135 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, 2136 RT5677_IB8_SRC_SFT, rt5677_inbound8_src); 2137 2138static const struct snd_kcontrol_new rt5677_ib8_src_mux = 2139 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); 2140 2141/* InBound9 Source */ /* MX-A4 [6:4] */ 2142static const char * const rt5677_inbound9_src[] = { 2143 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", 2144 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" 2145}; 2146 2147static SOC_ENUM_SINGLE_DECL( 2148 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, 2149 RT5677_IB9_SRC_SFT, rt5677_inbound9_src); 2150 2151static const struct snd_kcontrol_new rt5677_ib9_src_mux = 2152 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); 2153 2154/* VAD Source */ /* MX-9F [6:4] */ 2155static const char * const rt5677_vad_src[] = { 2156 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", 2157 "STO3 ADC MIX L" 2158}; 2159 2160static SOC_ENUM_SINGLE_DECL( 2161 rt5677_vad_enum, RT5677_VAD_CTRL4, 2162 RT5677_VAD_SRC_SFT, rt5677_vad_src); 2163 2164static const struct snd_kcontrol_new rt5677_vad_src_mux = 2165 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); 2166 2167/* Sidetone Source */ /* MX-13 [11:9] */ 2168static const char * const rt5677_sidetone_src[] = { 2169 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" 2170}; 2171 2172static SOC_ENUM_SINGLE_DECL( 2173 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, 2174 RT5677_ST_SEL_SFT, rt5677_sidetone_src); 2175 2176static const struct snd_kcontrol_new rt5677_sidetone_mux = 2177 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); 2178 2179/* DAC1/2 Source */ /* MX-15 [1:0] */ 2180static const char * const rt5677_dac12_src[] = { 2181 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2182}; 2183 2184static SOC_ENUM_SINGLE_DECL( 2185 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, 2186 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); 2187 2188static const struct snd_kcontrol_new rt5677_dac12_mux = 2189 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); 2190 2191/* DAC3 Source */ /* MX-15 [5:4] */ 2192static const char * const rt5677_dac3_src[] = { 2193 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" 2194}; 2195 2196static SOC_ENUM_SINGLE_DECL( 2197 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, 2198 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); 2199 2200static const struct snd_kcontrol_new rt5677_dac3_mux = 2201 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 2202 2203/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 2204static const char * const rt5677_pdm_src[] = { 2205 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2206}; 2207 2208static SOC_ENUM_SINGLE_DECL( 2209 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, 2210 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 2211 2212static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 2213 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); 2214 2215static SOC_ENUM_SINGLE_DECL( 2216 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 2217 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 2218 2219static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 2220 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); 2221 2222static SOC_ENUM_SINGLE_DECL( 2223 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 2224 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 2225 2226static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 2227 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); 2228 2229static SOC_ENUM_SINGLE_DECL( 2230 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 2231 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 2232 2233static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 2234 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 2235 2236/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ 2237static const char * const rt5677_if12_adc1_src[] = { 2238 "STO1 ADC MIX", "OB01", "VAD ADC" 2239}; 2240 2241static SOC_ENUM_SINGLE_DECL( 2242 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, 2243 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 2244 2245static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 2246 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); 2247 2248static SOC_ENUM_SINGLE_DECL( 2249 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 2250 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 2251 2252static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 2253 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); 2254 2255static SOC_ENUM_SINGLE_DECL( 2256 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 2257 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 2258 2259static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 2260 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); 2261 2262/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 2263static const char * const rt5677_if12_adc2_src[] = { 2264 "STO2 ADC MIX", "OB23" 2265}; 2266 2267static SOC_ENUM_SINGLE_DECL( 2268 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, 2269 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 2270 2271static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 2272 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); 2273 2274static SOC_ENUM_SINGLE_DECL( 2275 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 2276 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 2277 2278static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 2279 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); 2280 2281static SOC_ENUM_SINGLE_DECL( 2282 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 2283 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 2284 2285static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 2286 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); 2287 2288/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 2289static const char * const rt5677_if12_adc3_src[] = { 2290 "STO3 ADC MIX", "MONO ADC MIX", "OB45" 2291}; 2292 2293static SOC_ENUM_SINGLE_DECL( 2294 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, 2295 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 2296 2297static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 2298 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); 2299 2300static SOC_ENUM_SINGLE_DECL( 2301 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 2302 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 2303 2304static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 2305 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); 2306 2307static SOC_ENUM_SINGLE_DECL( 2308 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 2309 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 2310 2311static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 2312 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 2313 2314/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 2315static const char * const rt5677_if12_adc4_src[] = { 2316 "STO4 ADC MIX", "OB67", "OB01" 2317}; 2318 2319static SOC_ENUM_SINGLE_DECL( 2320 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, 2321 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 2322 2323static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 2324 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); 2325 2326static SOC_ENUM_SINGLE_DECL( 2327 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 2328 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 2329 2330static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 2331 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); 2332 2333static SOC_ENUM_SINGLE_DECL( 2334 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 2335 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 2336 2337static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 2338 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 2339 2340/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ 2341static const char * const rt5677_if34_adc_src[] = { 2342 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 2343 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 2344}; 2345 2346static SOC_ENUM_SINGLE_DECL( 2347 rt5677_if3_adc_enum, RT5677_IF3_DATA, 2348 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 2349 2350static const struct snd_kcontrol_new rt5677_if3_adc_mux = 2351 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); 2352 2353static SOC_ENUM_SINGLE_DECL( 2354 rt5677_if4_adc_enum, RT5677_IF4_DATA, 2355 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 2356 2357static const struct snd_kcontrol_new rt5677_if4_adc_mux = 2358 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 2359 2360/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ 2361static const char * const rt5677_if12_adc_swap_src[] = { 2362 "L/R", "R/L", "L/L", "R/R" 2363}; 2364 2365static SOC_ENUM_SINGLE_DECL( 2366 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, 2367 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); 2368 2369static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = 2370 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); 2371 2372static SOC_ENUM_SINGLE_DECL( 2373 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, 2374 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2375 2376static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = 2377 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); 2378 2379static SOC_ENUM_SINGLE_DECL( 2380 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, 2381 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2382 2383static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = 2384 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); 2385 2386static SOC_ENUM_SINGLE_DECL( 2387 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, 2388 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2389 2390static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = 2391 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); 2392 2393static SOC_ENUM_SINGLE_DECL( 2394 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, 2395 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2396 2397static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = 2398 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); 2399 2400static SOC_ENUM_SINGLE_DECL( 2401 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, 2402 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2403 2404static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = 2405 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); 2406 2407static SOC_ENUM_SINGLE_DECL( 2408 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, 2409 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2410 2411static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = 2412 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); 2413 2414static SOC_ENUM_SINGLE_DECL( 2415 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, 2416 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2417 2418static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = 2419 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); 2420 2421/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ 2422static const char * const rt5677_if1_adc_tdm_swap_src[] = { 2423 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2424 "3/1/2/4", "3/4/1/2" 2425}; 2426 2427static SOC_ENUM_SINGLE_DECL( 2428 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, 2429 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); 2430 2431static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = 2432 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); 2433 2434/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ 2435static const char * const rt5677_if2_adc_tdm_swap_src[] = { 2436 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2437 "2/3/1/4", "3/4/1/2" 2438}; 2439 2440static SOC_ENUM_SINGLE_DECL( 2441 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, 2442 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); 2443 2444static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = 2445 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); 2446 2447/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] 2448 MX-3F[14:12][10:8][6:4][2:0] 2449 MX-43[14:12][10:8][6:4][2:0] 2450 MX-44[14:12][10:8][6:4][2:0] */ 2451static const char * const rt5677_if12_dac_tdm_sel_src[] = { 2452 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 2453}; 2454 2455static SOC_ENUM_SINGLE_DECL( 2456 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, 2457 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2458 2459static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = 2460 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); 2461 2462static SOC_ENUM_SINGLE_DECL( 2463 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, 2464 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2465 2466static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = 2467 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); 2468 2469static SOC_ENUM_SINGLE_DECL( 2470 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, 2471 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2472 2473static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = 2474 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); 2475 2476static SOC_ENUM_SINGLE_DECL( 2477 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, 2478 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2479 2480static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = 2481 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); 2482 2483static SOC_ENUM_SINGLE_DECL( 2484 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, 2485 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2486 2487static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = 2488 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); 2489 2490static SOC_ENUM_SINGLE_DECL( 2491 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, 2492 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2493 2494static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = 2495 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); 2496 2497static SOC_ENUM_SINGLE_DECL( 2498 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, 2499 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2500 2501static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = 2502 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); 2503 2504static SOC_ENUM_SINGLE_DECL( 2505 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, 2506 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2507 2508static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = 2509 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); 2510 2511static SOC_ENUM_SINGLE_DECL( 2512 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, 2513 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2514 2515static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = 2516 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); 2517 2518static SOC_ENUM_SINGLE_DECL( 2519 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, 2520 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2521 2522static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = 2523 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); 2524 2525static SOC_ENUM_SINGLE_DECL( 2526 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, 2527 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2528 2529static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = 2530 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); 2531 2532static SOC_ENUM_SINGLE_DECL( 2533 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, 2534 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2535 2536static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = 2537 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); 2538 2539static SOC_ENUM_SINGLE_DECL( 2540 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, 2541 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2542 2543static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = 2544 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); 2545 2546static SOC_ENUM_SINGLE_DECL( 2547 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, 2548 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2549 2550static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = 2551 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); 2552 2553static SOC_ENUM_SINGLE_DECL( 2554 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, 2555 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2556 2557static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = 2558 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); 2559 2560static SOC_ENUM_SINGLE_DECL( 2561 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, 2562 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2563 2564static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = 2565 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); 2566 2567static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2568 struct snd_kcontrol *kcontrol, int event) 2569{ 2570 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2571 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2572 2573 switch (event) { 2574 case SND_SOC_DAPM_POST_PMU: 2575 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2576 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); 2577 break; 2578 2579 case SND_SOC_DAPM_PRE_PMD: 2580 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2581 RT5677_PWR_BST1_P, 0); 2582 break; 2583 2584 default: 2585 return 0; 2586 } 2587 2588 return 0; 2589} 2590 2591static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, 2592 struct snd_kcontrol *kcontrol, int event) 2593{ 2594 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2595 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2596 2597 switch (event) { 2598 case SND_SOC_DAPM_POST_PMU: 2599 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2600 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); 2601 break; 2602 2603 case SND_SOC_DAPM_PRE_PMD: 2604 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2605 RT5677_PWR_BST2_P, 0); 2606 break; 2607 2608 default: 2609 return 0; 2610 } 2611 2612 return 0; 2613} 2614 2615static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, 2616 struct snd_kcontrol *kcontrol, int event) 2617{ 2618 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2619 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2620 2621 switch (event) { 2622 case SND_SOC_DAPM_PRE_PMU: 2623 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); 2624 break; 2625 2626 case SND_SOC_DAPM_POST_PMU: 2627 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); 2628 break; 2629 2630 default: 2631 return 0; 2632 } 2633 2634 return 0; 2635} 2636 2637static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, 2638 struct snd_kcontrol *kcontrol, int event) 2639{ 2640 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2641 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2642 2643 switch (event) { 2644 case SND_SOC_DAPM_PRE_PMU: 2645 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); 2646 break; 2647 2648 case SND_SOC_DAPM_POST_PMU: 2649 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); 2650 break; 2651 2652 default: 2653 return 0; 2654 } 2655 2656 return 0; 2657} 2658 2659static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, 2660 struct snd_kcontrol *kcontrol, int event) 2661{ 2662 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2663 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2664 2665 switch (event) { 2666 case SND_SOC_DAPM_POST_PMU: 2667 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2668 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2669 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 2670 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 2671 break; 2672 2673 case SND_SOC_DAPM_PRE_PMD: 2674 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2675 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2676 RT5677_PWR_CLK_MB, 0); 2677 break; 2678 2679 default: 2680 return 0; 2681 } 2682 2683 return 0; 2684} 2685 2686static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, 2687 struct snd_kcontrol *kcontrol, int event) 2688{ 2689 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2690 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2691 unsigned int value; 2692 2693 switch (event) { 2694 case SND_SOC_DAPM_PRE_PMU: 2695 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); 2696 if (value & RT5677_IF1_ADC_CTRL_MASK) 2697 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 2698 RT5677_IF1_ADC_MODE_MASK, 2699 RT5677_IF1_ADC_MODE_TDM); 2700 break; 2701 2702 default: 2703 return 0; 2704 } 2705 2706 return 0; 2707} 2708 2709static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, 2710 struct snd_kcontrol *kcontrol, int event) 2711{ 2712 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2713 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2714 unsigned int value; 2715 2716 switch (event) { 2717 case SND_SOC_DAPM_PRE_PMU: 2718 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); 2719 if (value & RT5677_IF2_ADC_CTRL_MASK) 2720 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 2721 RT5677_IF2_ADC_MODE_MASK, 2722 RT5677_IF2_ADC_MODE_TDM); 2723 break; 2724 2725 default: 2726 return 0; 2727 } 2728 2729 return 0; 2730} 2731 2732static int rt5677_vref_event(struct snd_soc_dapm_widget *w, 2733 struct snd_kcontrol *kcontrol, int event) 2734{ 2735 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2736 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2737 2738 switch (event) { 2739 case SND_SOC_DAPM_POST_PMU: 2740 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON && 2741 !rt5677->is_vref_slow) { 2742 mdelay(20); 2743 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 2744 RT5677_PWR_FV1 | RT5677_PWR_FV2, 2745 RT5677_PWR_FV1 | RT5677_PWR_FV2); 2746 rt5677->is_vref_slow = true; 2747 } 2748 break; 2749 2750 default: 2751 return 0; 2752 } 2753 2754 return 0; 2755} 2756 2757static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w, 2758 struct snd_kcontrol *kcontrol, int event) 2759{ 2760 switch (event) { 2761 case SND_SOC_DAPM_POST_PMU: 2762 msleep(50); 2763 break; 2764 2765 default: 2766 return 0; 2767 } 2768 2769 return 0; 2770} 2771 2772static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2773 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2774 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | 2775 SND_SOC_DAPM_POST_PMU), 2776 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, 2777 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | 2778 SND_SOC_DAPM_POST_PMU), 2779 2780 /* ASRC */ 2781 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0), 2782 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0), 2783 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0), 2784 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0), 2785 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, 2786 rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU), 2787 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL, 2788 0), 2789 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL, 2790 0), 2791 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL, 2792 0), 2793 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL, 2794 0), 2795 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL, 2796 0), 2797 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL, 2798 0), 2799 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL, 2800 0), 2801 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL, 2802 0), 2803 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL, 2804 0), 2805 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL, 2806 0), 2807 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL, 2808 0), 2809 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL, 2810 0), 2811 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0), 2812 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0), 2813 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0), 2814 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0), 2815 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL, 2816 0), 2817 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL, 2818 0), 2819 2820 /* Input Side */ 2821 /* micbias */ 2822 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 2823 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | 2824 SND_SOC_DAPM_POST_PMU), 2825 2826 /* Input Lines */ 2827 SND_SOC_DAPM_INPUT("DMIC L1"), 2828 SND_SOC_DAPM_INPUT("DMIC R1"), 2829 SND_SOC_DAPM_INPUT("DMIC L2"), 2830 SND_SOC_DAPM_INPUT("DMIC R2"), 2831 SND_SOC_DAPM_INPUT("DMIC L3"), 2832 SND_SOC_DAPM_INPUT("DMIC R3"), 2833 SND_SOC_DAPM_INPUT("DMIC L4"), 2834 SND_SOC_DAPM_INPUT("DMIC R4"), 2835 2836 SND_SOC_DAPM_INPUT("IN1P"), 2837 SND_SOC_DAPM_INPUT("IN1N"), 2838 SND_SOC_DAPM_INPUT("IN2P"), 2839 SND_SOC_DAPM_INPUT("IN2N"), 2840 2841 SND_SOC_DAPM_INPUT("Haptic Generator"), 2842 2843 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2844 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2845 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2846 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2847 2848 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, 2849 RT5677_DMIC_1_EN_SFT, 0, NULL, 0), 2850 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, 2851 RT5677_DMIC_2_EN_SFT, 0, NULL, 0), 2852 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, 2853 RT5677_DMIC_3_EN_SFT, 0, NULL, 0), 2854 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, 2855 RT5677_DMIC_4_EN_SFT, 0, NULL, 0), 2856 2857 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2858 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2859 2860 /* Boost */ 2861 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, 2862 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, 2863 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2864 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, 2865 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, 2866 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2867 2868 /* ADCs */ 2869 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 2870 0, 0), 2871 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 2872 0, 0), 2873 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), 2874 2875 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, 2876 RT5677_PWR_ADC_L_BIT, 0, NULL, 0), 2877 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, 2878 RT5677_PWR_ADC_R_BIT, 0, NULL, 0), 2879 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, 2880 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), 2881 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, 2882 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), 2883 2884 /* ADC Mux */ 2885 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2886 &rt5677_sto1_dmic_mux), 2887 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2888 &rt5677_sto1_adc1_mux), 2889 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2890 &rt5677_sto1_adc2_mux), 2891 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 2892 &rt5677_sto2_dmic_mux), 2893 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2894 &rt5677_sto2_adc1_mux), 2895 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2896 &rt5677_sto2_adc2_mux), 2897 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, 2898 &rt5677_sto2_adc_lr_mux), 2899 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, 2900 &rt5677_sto3_dmic_mux), 2901 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2902 &rt5677_sto3_adc1_mux), 2903 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2904 &rt5677_sto3_adc2_mux), 2905 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, 2906 &rt5677_sto4_dmic_mux), 2907 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2908 &rt5677_sto4_adc1_mux), 2909 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2910 &rt5677_sto4_adc2_mux), 2911 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2912 &rt5677_mono_dmic_l_mux), 2913 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2914 &rt5677_mono_dmic_r_mux), 2915 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, 2916 &rt5677_mono_adc2_l_mux), 2917 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, 2918 &rt5677_mono_adc1_l_mux), 2919 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, 2920 &rt5677_mono_adc1_r_mux), 2921 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, 2922 &rt5677_mono_adc2_r_mux), 2923 2924 /* ADC Mixer */ 2925 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, 2926 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), 2927 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, 2928 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), 2929 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, 2930 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), 2931 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, 2932 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), 2933 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2934 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), 2935 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2936 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), 2937 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 2938 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), 2939 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 2940 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), 2941 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, 2942 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), 2943 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, 2944 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), 2945 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, 2946 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), 2947 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, 2948 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), 2949 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, 2950 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2951 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2952 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), 2953 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, 2954 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2955 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2956 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), 2957 2958 /* ADC PGA */ 2959 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2960 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2961 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2962 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2963 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2964 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2965 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2966 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2967 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2968 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2969 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2970 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2971 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2972 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2973 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2974 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2975 2976 /* DSP */ 2977 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2978 &rt5677_ib9_src_mux), 2979 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, 2980 &rt5677_ib8_src_mux), 2981 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, 2982 &rt5677_ib7_src_mux), 2983 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, 2984 &rt5677_ib6_src_mux), 2985 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, 2986 &rt5677_ib45_src_mux), 2987 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, 2988 &rt5677_ib23_src_mux), 2989 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, 2990 &rt5677_ib01_src_mux), 2991 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, 2992 &rt5677_ib45_bypass_src_mux), 2993 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2994 &rt5677_ib23_bypass_src_mux), 2995 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2996 &rt5677_ib01_bypass_src_mux), 2997 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2998 &rt5677_ob23_bypass_src_mux), 2999 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 3000 &rt5677_ob01_bypass_src_mux), 3001 3002 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), 3003 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), 3004 3005 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), 3006 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), 3007 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), 3008 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), 3009 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), 3010 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), 3011 3012 /* Digital Interface */ 3013 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, 3014 RT5677_PWR_I2S1_BIT, 0, NULL, 0), 3015 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3016 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3017 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3018 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3019 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3020 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3021 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3022 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3023 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3024 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3025 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3026 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3027 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3028 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3029 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3030 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3031 3032 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, 3033 RT5677_PWR_I2S2_BIT, 0, NULL, 0), 3034 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3035 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3036 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3037 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3038 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3039 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3040 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3041 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3042 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3043 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3044 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3045 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3046 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3047 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3048 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3049 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3050 3051 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, 3052 RT5677_PWR_I2S3_BIT, 0, NULL, 0), 3053 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3054 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3055 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3056 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3057 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3058 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3059 3060 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, 3061 RT5677_PWR_I2S4_BIT, 0, NULL, 0), 3062 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3063 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3064 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3065 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3066 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3067 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3068 3069 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, 3070 RT5677_PWR_SLB_BIT, 0, NULL, 0), 3071 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3072 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3073 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3074 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3075 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3076 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3077 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3078 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3079 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3080 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3081 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3082 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3083 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3084 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3085 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3086 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3087 3088 /* Digital Interface Select */ 3089 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3090 &rt5677_if1_adc1_mux), 3091 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3092 &rt5677_if1_adc2_mux), 3093 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3094 &rt5677_if1_adc3_mux), 3095 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3096 &rt5677_if1_adc4_mux), 3097 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3098 &rt5677_if1_adc1_swap_mux), 3099 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3100 &rt5677_if1_adc2_swap_mux), 3101 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3102 &rt5677_if1_adc3_swap_mux), 3103 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3104 &rt5677_if1_adc4_swap_mux), 3105 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3106 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, 3107 SND_SOC_DAPM_PRE_PMU), 3108 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3109 &rt5677_if2_adc1_mux), 3110 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3111 &rt5677_if2_adc2_mux), 3112 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3113 &rt5677_if2_adc3_mux), 3114 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3115 &rt5677_if2_adc4_mux), 3116 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3117 &rt5677_if2_adc1_swap_mux), 3118 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3119 &rt5677_if2_adc2_swap_mux), 3120 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3121 &rt5677_if2_adc3_swap_mux), 3122 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3123 &rt5677_if2_adc4_swap_mux), 3124 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3125 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, 3126 SND_SOC_DAPM_PRE_PMU), 3127 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 3128 &rt5677_if3_adc_mux), 3129 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 3130 &rt5677_if4_adc_mux), 3131 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, 3132 &rt5677_slb_adc1_mux), 3133 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, 3134 &rt5677_slb_adc2_mux), 3135 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, 3136 &rt5677_slb_adc3_mux), 3137 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 3138 &rt5677_slb_adc4_mux), 3139 3140 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3141 &rt5677_if1_dac0_tdm_sel_mux), 3142 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3143 &rt5677_if1_dac1_tdm_sel_mux), 3144 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3145 &rt5677_if1_dac2_tdm_sel_mux), 3146 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3147 &rt5677_if1_dac3_tdm_sel_mux), 3148 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3149 &rt5677_if1_dac4_tdm_sel_mux), 3150 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3151 &rt5677_if1_dac5_tdm_sel_mux), 3152 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3153 &rt5677_if1_dac6_tdm_sel_mux), 3154 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3155 &rt5677_if1_dac7_tdm_sel_mux), 3156 3157 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3158 &rt5677_if2_dac0_tdm_sel_mux), 3159 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3160 &rt5677_if2_dac1_tdm_sel_mux), 3161 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3162 &rt5677_if2_dac2_tdm_sel_mux), 3163 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3164 &rt5677_if2_dac3_tdm_sel_mux), 3165 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3166 &rt5677_if2_dac4_tdm_sel_mux), 3167 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3168 &rt5677_if2_dac5_tdm_sel_mux), 3169 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3170 &rt5677_if2_dac6_tdm_sel_mux), 3171 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3172 &rt5677_if2_dac7_tdm_sel_mux), 3173 3174 /* Audio Interface */ 3175 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 3176 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 3177 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 3178 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 3179 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 3180 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 3181 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), 3182 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), 3183 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), 3184 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), 3185 SND_SOC_DAPM_AIF_OUT("DSPTX", "DSP Buffer", 0, SND_SOC_NOPM, 0, 0), 3186 3187 /* Sidetone Mux */ 3188 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, 3189 &rt5677_sidetone_mux), 3190 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, 3191 RT5677_ST_EN_SFT, 0, NULL, 0), 3192 3193 /* VAD Mux*/ 3194 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, 3195 &rt5677_vad_src_mux), 3196 3197 /* Tensilica DSP */ 3198 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 3199 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, 3200 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), 3201 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, 3202 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), 3203 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, 3204 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), 3205 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, 3206 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), 3207 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, 3208 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), 3209 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, 3210 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 3211 3212 /* Output Side */ 3213 /* DAC mixer before sound effect */ 3214 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 3215 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 3216 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 3217 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), 3218 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), 3219 3220 /* DAC Mux */ 3221 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, 3222 &rt5677_dac1_mux), 3223 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, 3224 &rt5677_adda1_mux), 3225 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, 3226 &rt5677_dac12_mux), 3227 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, 3228 &rt5677_dac3_mux), 3229 3230 /* DAC2 channel Mux */ 3231 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, 3232 &rt5677_dac2_l_mux), 3233 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, 3234 &rt5677_dac2_r_mux), 3235 3236 /* DAC3 channel Mux */ 3237 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, 3238 &rt5677_dac3_l_mux), 3239 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, 3240 &rt5677_dac3_r_mux), 3241 3242 /* DAC4 channel Mux */ 3243 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, 3244 &rt5677_dac4_l_mux), 3245 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, 3246 &rt5677_dac4_r_mux), 3247 3248 /* DAC Mixer */ 3249 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, 3250 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event, 3251 SND_SOC_DAPM_POST_PMU), 3252 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2, 3253 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event, 3254 SND_SOC_DAPM_POST_PMU), 3255 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2, 3256 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event, 3257 SND_SOC_DAPM_POST_PMU), 3258 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2, 3259 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event, 3260 SND_SOC_DAPM_POST_PMU), 3261 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2, 3262 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event, 3263 SND_SOC_DAPM_POST_PMU), 3264 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2, 3265 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event, 3266 SND_SOC_DAPM_POST_PMU), 3267 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2, 3268 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event, 3269 SND_SOC_DAPM_POST_PMU), 3270 3271 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 3272 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), 3273 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 3274 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), 3275 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 3276 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), 3277 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 3278 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), 3279 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, 3280 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), 3281 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, 3282 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), 3283 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, 3284 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), 3285 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, 3286 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), 3287 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3288 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3289 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3290 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3291 3292 /* DACs */ 3293 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, 3294 RT5677_PWR_DAC1_BIT, 0), 3295 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, 3296 RT5677_PWR_DAC2_BIT, 0), 3297 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, 3298 RT5677_PWR_DAC3_BIT, 0), 3299 3300 /* PDM */ 3301 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, 3302 RT5677_PWR_PDM1_BIT, 0, NULL, 0), 3303 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, 3304 RT5677_PWR_PDM2_BIT, 0, NULL, 0), 3305 3306 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, 3307 1, &rt5677_pdm1_l_mux), 3308 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, 3309 1, &rt5677_pdm1_r_mux), 3310 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, 3311 1, &rt5677_pdm2_l_mux), 3312 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 3313 1, &rt5677_pdm2_r_mux), 3314 3315 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 3316 0, NULL, 0), 3317 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 3318 0, NULL, 0), 3319 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 3320 0, NULL, 0), 3321 3322 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, 3323 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3324 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, 3325 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3326 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, 3327 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3328 3329 /* Output Lines */ 3330 SND_SOC_DAPM_OUTPUT("LOUT1"), 3331 SND_SOC_DAPM_OUTPUT("LOUT2"), 3332 SND_SOC_DAPM_OUTPUT("LOUT3"), 3333 SND_SOC_DAPM_OUTPUT("PDM1L"), 3334 SND_SOC_DAPM_OUTPUT("PDM1R"), 3335 SND_SOC_DAPM_OUTPUT("PDM2L"), 3336 SND_SOC_DAPM_OUTPUT("PDM2R"), 3337 3338 SND_SOC_DAPM_POST("vref", rt5677_vref_event), 3339}; 3340 3341static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 3342 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc }, 3343 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc }, 3344 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc }, 3345 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc }, 3346 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc }, 3347 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc }, 3348 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc}, 3349 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc}, 3350 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc}, 3351 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc}, 3352 3353 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 3354 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc }, 3355 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc }, 3356 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc }, 3357 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc }, 3358 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc }, 3359 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc }, 3360 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 3361 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc }, 3362 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc }, 3363 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc }, 3364 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 3365 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 3366 3367 { "DMIC1", NULL, "DMIC L1" }, 3368 { "DMIC1", NULL, "DMIC R1" }, 3369 { "DMIC2", NULL, "DMIC L2" }, 3370 { "DMIC2", NULL, "DMIC R2" }, 3371 { "DMIC3", NULL, "DMIC L3" }, 3372 { "DMIC3", NULL, "DMIC R3" }, 3373 { "DMIC4", NULL, "DMIC L4" }, 3374 { "DMIC4", NULL, "DMIC R4" }, 3375 3376 { "DMIC L1", NULL, "DMIC CLK" }, 3377 { "DMIC R1", NULL, "DMIC CLK" }, 3378 { "DMIC L2", NULL, "DMIC CLK" }, 3379 { "DMIC R2", NULL, "DMIC CLK" }, 3380 { "DMIC L3", NULL, "DMIC CLK" }, 3381 { "DMIC R3", NULL, "DMIC CLK" }, 3382 { "DMIC L4", NULL, "DMIC CLK" }, 3383 { "DMIC R4", NULL, "DMIC CLK" }, 3384 3385 { "DMIC L1", NULL, "DMIC1 power" }, 3386 { "DMIC R1", NULL, "DMIC1 power" }, 3387 { "DMIC L3", NULL, "DMIC3 power" }, 3388 { "DMIC R3", NULL, "DMIC3 power" }, 3389 { "DMIC L4", NULL, "DMIC4 power" }, 3390 { "DMIC R4", NULL, "DMIC4 power" }, 3391 3392 { "BST1", NULL, "IN1P" }, 3393 { "BST1", NULL, "IN1N" }, 3394 { "BST2", NULL, "IN2P" }, 3395 { "BST2", NULL, "IN2N" }, 3396 3397 { "IN1P", NULL, "MICBIAS1" }, 3398 { "IN1N", NULL, "MICBIAS1" }, 3399 { "IN2P", NULL, "MICBIAS1" }, 3400 { "IN2N", NULL, "MICBIAS1" }, 3401 3402 { "ADC 1", NULL, "BST1" }, 3403 { "ADC 1", NULL, "ADC 1 power" }, 3404 { "ADC 1", NULL, "ADC1 clock" }, 3405 { "ADC 2", NULL, "BST2" }, 3406 { "ADC 2", NULL, "ADC 2 power" }, 3407 { "ADC 2", NULL, "ADC2 clock" }, 3408 3409 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 3410 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 3411 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, 3412 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, 3413 3414 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 3415 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 3416 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, 3417 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, 3418 3419 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, 3420 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, 3421 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, 3422 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, 3423 3424 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, 3425 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, 3426 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, 3427 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, 3428 3429 { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, 3430 { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, 3431 { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, 3432 { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, 3433 3434 { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, 3435 { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, 3436 { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, 3437 { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, 3438 3439 { "ADC 1_2", NULL, "ADC 1" }, 3440 { "ADC 1_2", NULL, "ADC 2" }, 3441 3442 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3443 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3444 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3445 3446 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3447 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 3448 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3449 3450 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3451 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3452 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3453 3454 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3455 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, 3456 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3457 3458 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3459 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3460 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3461 3462 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3463 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3464 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3465 3466 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3467 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3468 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, 3469 3470 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3471 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3472 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, 3473 3474 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, 3475 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, 3476 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3477 3478 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, 3479 { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, 3480 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3481 3482 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, 3483 { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, 3484 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3485 3486 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, 3487 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, 3488 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3489 3490 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3491 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3492 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3493 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3494 3495 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 3496 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 3497 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 3498 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 3499 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3500 3501 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 3502 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 3503 3504 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3505 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3506 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3507 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3508 3509 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, 3510 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, 3511 3512 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, 3513 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, 3514 3515 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, 3516 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, 3517 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 3518 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, 3519 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3520 3521 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 3522 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 3523 3524 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3525 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3526 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3527 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3528 3529 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, 3530 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, 3531 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, 3532 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, 3533 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3534 3535 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, 3536 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, 3537 3538 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3539 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3540 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3541 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3542 3543 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, 3544 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, 3545 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, 3546 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, 3547 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3548 3549 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, 3550 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, 3551 3552 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, 3553 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, 3554 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 3555 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3556 3557 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, 3558 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, 3559 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 3560 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3561 3562 { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, 3563 { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, 3564 3565 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3566 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3567 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3568 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3569 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3570 3571 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3572 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3573 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3574 3575 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3576 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3577 3578 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3579 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3580 { "IF1 ADC3 Mux", "OB45", "OB45" }, 3581 3582 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3583 { "IF1 ADC4 Mux", "OB67", "OB67" }, 3584 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3585 3586 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, 3587 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, 3588 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, 3589 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, 3590 3591 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, 3592 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, 3593 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, 3594 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, 3595 3596 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, 3597 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, 3598 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, 3599 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, 3600 3601 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, 3602 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, 3603 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, 3604 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, 3605 3606 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, 3607 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, 3608 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, 3609 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, 3610 3611 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, 3612 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, 3613 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, 3614 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, 3615 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, 3616 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, 3617 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, 3618 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, 3619 3620 { "AIF1TX", NULL, "I2S1" }, 3621 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, 3622 3623 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3624 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3625 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3626 3627 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3628 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3629 3630 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3631 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3632 { "IF2 ADC3 Mux", "OB45", "OB45" }, 3633 3634 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3635 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3636 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3637 3638 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, 3639 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, 3640 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, 3641 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, 3642 3643 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, 3644 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, 3645 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, 3646 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, 3647 3648 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, 3649 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, 3650 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, 3651 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, 3652 3653 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, 3654 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, 3655 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, 3656 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, 3657 3658 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, 3659 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, 3660 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, 3661 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, 3662 3663 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, 3664 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, 3665 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, 3666 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, 3667 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, 3668 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, 3669 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, 3670 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, 3671 3672 { "AIF2TX", NULL, "I2S2" }, 3673 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, 3674 3675 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3676 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3677 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3678 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3679 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3680 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3681 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3682 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3683 3684 { "AIF3TX", NULL, "I2S3" }, 3685 { "AIF3TX", NULL, "IF3 ADC Mux" }, 3686 3687 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3688 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3689 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3690 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3691 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3692 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3693 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3694 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3695 3696 { "AIF4TX", NULL, "I2S4" }, 3697 { "AIF4TX", NULL, "IF4 ADC Mux" }, 3698 3699 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3700 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3701 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3702 3703 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3704 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3705 3706 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3707 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3708 { "SLB ADC3 Mux", "OB45", "OB45" }, 3709 3710 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3711 { "SLB ADC4 Mux", "OB67", "OB67" }, 3712 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3713 3714 { "SLBTX", NULL, "SLB" }, 3715 { "SLBTX", NULL, "SLB ADC1 Mux" }, 3716 { "SLBTX", NULL, "SLB ADC2 Mux" }, 3717 { "SLBTX", NULL, "SLB ADC3 Mux" }, 3718 { "SLBTX", NULL, "SLB ADC4 Mux" }, 3719 3720 { "DSPTX", NULL, "IB01 Bypass Mux" }, 3721 3722 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3723 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3724 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, 3725 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3726 /* The IB01 Mux controls the source for InBound0 and InBound1. 3727 * When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to 3728 * InBound0 and "DAC1 FS" goes to InBound1. "VAD ADC" is used for 3729 * hotwording. "DAC1 FS" is not used currently. 3730 * 3731 * Creating a common widget node for "VAD ADC" + "DAC1 FS" and 3732 * connecting the common widget to IB01 Mux causes the issue where 3733 * there is an active path going from system playback -> "DAC1 FS" -> 3734 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses 3735 * DAPM. Therefore "DAC1 FS" is ignored for now. 3736 */ 3737 { "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" }, 3738 3739 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, 3740 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, 3741 3742 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, 3743 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, 3744 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, 3745 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3746 { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, 3747 { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, 3748 3749 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, 3750 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, 3751 3752 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, 3753 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, 3754 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, 3755 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3756 { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, 3757 3758 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, 3759 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, 3760 3761 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 3762 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 3763 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, 3764 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3765 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, 3766 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3767 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3768 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3769 3770 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 3771 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 3772 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, 3773 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3774 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, 3775 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3776 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3777 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3778 3779 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3780 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3781 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3782 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3783 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3784 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, 3785 3786 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3787 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3788 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3789 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3790 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3791 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, 3792 { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, 3793 3794 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3795 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3796 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3797 { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, 3798 { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, 3799 { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, 3800 { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, 3801 3802 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3803 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3804 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3805 { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, 3806 { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, 3807 { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, 3808 { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, 3809 3810 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3811 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3812 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3813 { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, 3814 { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, 3815 { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, 3816 { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, 3817 3818 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3819 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3820 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3821 { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, 3822 { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, 3823 { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, 3824 { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, 3825 3826 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3827 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3828 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3829 { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, 3830 { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, 3831 { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, 3832 { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, 3833 3834 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3835 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3836 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3837 { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, 3838 { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, 3839 { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, 3840 { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, 3841 3842 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, 3843 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, 3844 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, 3845 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, 3846 3847 { "OutBound2", NULL, "OB23 Bypass Mux" }, 3848 { "OutBound3", NULL, "OB23 Bypass Mux" }, 3849 { "OutBound4", NULL, "OB4 MIX" }, 3850 { "OutBound5", NULL, "OB5 MIX" }, 3851 { "OutBound6", NULL, "OB6 MIX" }, 3852 { "OutBound7", NULL, "OB7 MIX" }, 3853 3854 { "OB45", NULL, "OutBound4" }, 3855 { "OB45", NULL, "OutBound5" }, 3856 { "OB67", NULL, "OutBound6" }, 3857 { "OB67", NULL, "OutBound7" }, 3858 3859 { "IF1 DAC0", NULL, "AIF1RX" }, 3860 { "IF1 DAC1", NULL, "AIF1RX" }, 3861 { "IF1 DAC2", NULL, "AIF1RX" }, 3862 { "IF1 DAC3", NULL, "AIF1RX" }, 3863 { "IF1 DAC4", NULL, "AIF1RX" }, 3864 { "IF1 DAC5", NULL, "AIF1RX" }, 3865 { "IF1 DAC6", NULL, "AIF1RX" }, 3866 { "IF1 DAC7", NULL, "AIF1RX" }, 3867 { "IF1 DAC0", NULL, "I2S1" }, 3868 { "IF1 DAC1", NULL, "I2S1" }, 3869 { "IF1 DAC2", NULL, "I2S1" }, 3870 { "IF1 DAC3", NULL, "I2S1" }, 3871 { "IF1 DAC4", NULL, "I2S1" }, 3872 { "IF1 DAC5", NULL, "I2S1" }, 3873 { "IF1 DAC6", NULL, "I2S1" }, 3874 { "IF1 DAC7", NULL, "I2S1" }, 3875 3876 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, 3877 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, 3878 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, 3879 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, 3880 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, 3881 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, 3882 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, 3883 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, 3884 3885 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, 3886 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, 3887 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, 3888 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, 3889 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, 3890 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, 3891 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, 3892 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, 3893 3894 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, 3895 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, 3896 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, 3897 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, 3898 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, 3899 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, 3900 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, 3901 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, 3902 3903 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, 3904 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, 3905 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, 3906 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, 3907 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, 3908 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, 3909 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, 3910 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, 3911 3912 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, 3913 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, 3914 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, 3915 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, 3916 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, 3917 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, 3918 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, 3919 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, 3920 3921 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, 3922 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, 3923 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, 3924 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, 3925 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, 3926 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, 3927 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, 3928 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, 3929 3930 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, 3931 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, 3932 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, 3933 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, 3934 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, 3935 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, 3936 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, 3937 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, 3938 3939 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, 3940 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, 3941 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, 3942 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, 3943 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, 3944 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, 3945 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, 3946 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, 3947 3948 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, 3949 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, 3950 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, 3951 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, 3952 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, 3953 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, 3954 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, 3955 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, 3956 3957 { "IF2 DAC0", NULL, "AIF2RX" }, 3958 { "IF2 DAC1", NULL, "AIF2RX" }, 3959 { "IF2 DAC2", NULL, "AIF2RX" }, 3960 { "IF2 DAC3", NULL, "AIF2RX" }, 3961 { "IF2 DAC4", NULL, "AIF2RX" }, 3962 { "IF2 DAC5", NULL, "AIF2RX" }, 3963 { "IF2 DAC6", NULL, "AIF2RX" }, 3964 { "IF2 DAC7", NULL, "AIF2RX" }, 3965 { "IF2 DAC0", NULL, "I2S2" }, 3966 { "IF2 DAC1", NULL, "I2S2" }, 3967 { "IF2 DAC2", NULL, "I2S2" }, 3968 { "IF2 DAC3", NULL, "I2S2" }, 3969 { "IF2 DAC4", NULL, "I2S2" }, 3970 { "IF2 DAC5", NULL, "I2S2" }, 3971 { "IF2 DAC6", NULL, "I2S2" }, 3972 { "IF2 DAC7", NULL, "I2S2" }, 3973 3974 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, 3975 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, 3976 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, 3977 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, 3978 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, 3979 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, 3980 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, 3981 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, 3982 3983 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, 3984 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, 3985 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, 3986 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, 3987 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, 3988 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, 3989 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, 3990 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, 3991 3992 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, 3993 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, 3994 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, 3995 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, 3996 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, 3997 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, 3998 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, 3999 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, 4000 4001 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, 4002 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, 4003 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, 4004 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, 4005 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, 4006 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, 4007 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, 4008 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, 4009 4010 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, 4011 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, 4012 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, 4013 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, 4014 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, 4015 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, 4016 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, 4017 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, 4018 4019 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, 4020 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, 4021 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, 4022 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, 4023 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, 4024 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, 4025 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, 4026 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, 4027 4028 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, 4029 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, 4030 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, 4031 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, 4032 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, 4033 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, 4034 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, 4035 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, 4036 4037 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, 4038 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, 4039 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, 4040 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, 4041 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, 4042 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, 4043 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, 4044 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, 4045 4046 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, 4047 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, 4048 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, 4049 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, 4050 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, 4051 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, 4052 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, 4053 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, 4054 4055 { "IF3 DAC", NULL, "AIF3RX" }, 4056 { "IF3 DAC", NULL, "I2S3" }, 4057 4058 { "IF4 DAC", NULL, "AIF4RX" }, 4059 { "IF4 DAC", NULL, "I2S4" }, 4060 4061 { "IF3 DAC L", NULL, "IF3 DAC" }, 4062 { "IF3 DAC R", NULL, "IF3 DAC" }, 4063 4064 { "IF4 DAC L", NULL, "IF4 DAC" }, 4065 { "IF4 DAC R", NULL, "IF4 DAC" }, 4066 4067 { "SLB DAC0", NULL, "SLBRX" }, 4068 { "SLB DAC1", NULL, "SLBRX" }, 4069 { "SLB DAC2", NULL, "SLBRX" }, 4070 { "SLB DAC3", NULL, "SLBRX" }, 4071 { "SLB DAC4", NULL, "SLBRX" }, 4072 { "SLB DAC5", NULL, "SLBRX" }, 4073 { "SLB DAC6", NULL, "SLBRX" }, 4074 { "SLB DAC7", NULL, "SLBRX" }, 4075 { "SLB DAC0", NULL, "SLB" }, 4076 { "SLB DAC1", NULL, "SLB" }, 4077 { "SLB DAC2", NULL, "SLB" }, 4078 { "SLB DAC3", NULL, "SLB" }, 4079 { "SLB DAC4", NULL, "SLB" }, 4080 { "SLB DAC5", NULL, "SLB" }, 4081 { "SLB DAC6", NULL, "SLB" }, 4082 { "SLB DAC7", NULL, "SLB" }, 4083 4084 { "SLB DAC01", NULL, "SLB DAC0" }, 4085 { "SLB DAC01", NULL, "SLB DAC1" }, 4086 { "SLB DAC23", NULL, "SLB DAC2" }, 4087 { "SLB DAC23", NULL, "SLB DAC3" }, 4088 { "SLB DAC45", NULL, "SLB DAC4" }, 4089 { "SLB DAC45", NULL, "SLB DAC5" }, 4090 { "SLB DAC67", NULL, "SLB DAC6" }, 4091 { "SLB DAC67", NULL, "SLB DAC7" }, 4092 4093 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 4094 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 4095 { "ADDA1 Mux", "OB 67", "OB67" }, 4096 4097 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, 4098 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, 4099 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, 4100 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, 4101 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, 4102 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, 4103 4104 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, 4105 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, 4106 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, 4107 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, 4108 4109 { "DAC1 FS", NULL, "DAC1 MIXL" }, 4110 { "DAC1 FS", NULL, "DAC1 MIXR" }, 4111 4112 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" }, 4113 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" }, 4114 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4115 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4116 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, 4117 { "DAC2 L Mux", "OB 2", "OutBound2" }, 4118 4119 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" }, 4120 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" }, 4121 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4122 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4123 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, 4124 { "DAC2 R Mux", "OB 3", "OutBound3" }, 4125 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, 4126 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, 4127 4128 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" }, 4129 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" }, 4130 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4131 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4132 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, 4133 { "DAC3 L Mux", "OB 4", "OutBound4" }, 4134 4135 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" }, 4136 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" }, 4137 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4138 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4139 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, 4140 { "DAC3 R Mux", "OB 5", "OutBound5" }, 4141 4142 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 4143 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 4144 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4145 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4146 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, 4147 { "DAC4 L Mux", "OB 6", "OutBound6" }, 4148 4149 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 4150 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 4151 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4152 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4153 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, 4154 { "DAC4 R Mux", "OB 7", "OutBound7" }, 4155 4156 { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, 4157 { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, 4158 { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, 4159 { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, 4160 { "Sidetone Mux", "ADC1", "ADC 1" }, 4161 { "Sidetone Mux", "ADC2", "ADC 2" }, 4162 { "Sidetone Mux", NULL, "Sidetone Power" }, 4163 4164 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4165 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4166 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4167 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, 4168 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 4169 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4170 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4171 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4172 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, 4173 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 4174 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 4175 4176 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4177 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4178 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4179 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, 4180 { "Mono DAC MIXL", NULL, "dac mono2 left filter" }, 4181 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4182 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4183 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4184 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4185 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, 4186 { "Mono DAC MIXR", NULL, "dac mono2 right filter" }, 4187 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4188 4189 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4190 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4191 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, 4192 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, 4193 { "DD1 MIXL", NULL, "dac mono3 left filter" }, 4194 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4195 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4196 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4197 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, 4198 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, 4199 { "DD1 MIXR", NULL, "dac mono3 right filter" }, 4200 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4201 4202 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4203 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4204 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, 4205 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, 4206 { "DD2 MIXL", NULL, "dac mono4 left filter" }, 4207 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4208 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4209 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4210 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, 4211 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, 4212 { "DD2 MIXR", NULL, "dac mono4 right filter" }, 4213 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4214 4215 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, 4216 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, 4217 { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, 4218 { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, 4219 { "DD1 MIX", NULL, "DD1 MIXL" }, 4220 { "DD1 MIX", NULL, "DD1 MIXR" }, 4221 { "DD2 MIX", NULL, "DD2 MIXL" }, 4222 { "DD2 MIX", NULL, "DD2 MIXR" }, 4223 4224 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, 4225 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, 4226 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, 4227 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, 4228 4229 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 4230 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 4231 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, 4232 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, 4233 4234 { "DAC 1", NULL, "DAC12 SRC Mux" }, 4235 { "DAC 2", NULL, "DAC12 SRC Mux" }, 4236 { "DAC 3", NULL, "DAC3 SRC Mux" }, 4237 4238 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4239 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4240 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, 4241 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, 4242 { "PDM1 L Mux", NULL, "PDM1 Power" }, 4243 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4244 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4245 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, 4246 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, 4247 { "PDM1 R Mux", NULL, "PDM1 Power" }, 4248 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4249 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4250 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, 4251 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, 4252 { "PDM2 L Mux", NULL, "PDM2 Power" }, 4253 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4254 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4255 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, 4256 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, 4257 { "PDM2 R Mux", NULL, "PDM2 Power" }, 4258 4259 { "LOUT1 amp", NULL, "DAC 1" }, 4260 { "LOUT2 amp", NULL, "DAC 2" }, 4261 { "LOUT3 amp", NULL, "DAC 3" }, 4262 4263 { "LOUT1 vref", NULL, "LOUT1 amp" }, 4264 { "LOUT2 vref", NULL, "LOUT2 amp" }, 4265 { "LOUT3 vref", NULL, "LOUT3 amp" }, 4266 4267 { "LOUT1", NULL, "LOUT1 vref" }, 4268 { "LOUT2", NULL, "LOUT2 vref" }, 4269 { "LOUT3", NULL, "LOUT3 vref" }, 4270 4271 { "PDM1L", NULL, "PDM1 L Mux" }, 4272 { "PDM1R", NULL, "PDM1 R Mux" }, 4273 { "PDM2L", NULL, "PDM2 L Mux" }, 4274 { "PDM2R", NULL, "PDM2 R Mux" }, 4275}; 4276 4277static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { 4278 { "DMIC L2", NULL, "DMIC1 power" }, 4279 { "DMIC R2", NULL, "DMIC1 power" }, 4280}; 4281 4282static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { 4283 { "DMIC L2", NULL, "DMIC2 power" }, 4284 { "DMIC R2", NULL, "DMIC2 power" }, 4285}; 4286 4287static int rt5677_hw_params(struct snd_pcm_substream *substream, 4288 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 4289{ 4290 struct snd_soc_component *component = dai->component; 4291 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4292 unsigned int val_len = 0, val_clk, mask_clk; 4293 int pre_div, bclk_ms, frame_size; 4294 4295 rt5677->lrck[dai->id] = params_rate(params); 4296 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 4297 if (pre_div < 0) { 4298 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", 4299 rt5677->sysclk, rt5677->lrck[dai->id]); 4300 return -EINVAL; 4301 } 4302 frame_size = snd_soc_params_to_frame_size(params); 4303 if (frame_size < 0) { 4304 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 4305 return -EINVAL; 4306 } 4307 bclk_ms = frame_size > 32; 4308 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); 4309 4310 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 4311 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); 4312 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 4313 bclk_ms, pre_div, dai->id); 4314 4315 switch (params_width(params)) { 4316 case 16: 4317 break; 4318 case 20: 4319 val_len |= RT5677_I2S_DL_20; 4320 break; 4321 case 24: 4322 val_len |= RT5677_I2S_DL_24; 4323 break; 4324 case 8: 4325 val_len |= RT5677_I2S_DL_8; 4326 break; 4327 default: 4328 return -EINVAL; 4329 } 4330 4331 switch (dai->id) { 4332 case RT5677_AIF1: 4333 mask_clk = RT5677_I2S_PD1_MASK; 4334 val_clk = pre_div << RT5677_I2S_PD1_SFT; 4335 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4336 RT5677_I2S_DL_MASK, val_len); 4337 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4338 mask_clk, val_clk); 4339 break; 4340 case RT5677_AIF2: 4341 mask_clk = RT5677_I2S_PD2_MASK; 4342 val_clk = pre_div << RT5677_I2S_PD2_SFT; 4343 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4344 RT5677_I2S_DL_MASK, val_len); 4345 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4346 mask_clk, val_clk); 4347 break; 4348 case RT5677_AIF3: 4349 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; 4350 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | 4351 pre_div << RT5677_I2S_PD3_SFT; 4352 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4353 RT5677_I2S_DL_MASK, val_len); 4354 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4355 mask_clk, val_clk); 4356 break; 4357 case RT5677_AIF4: 4358 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; 4359 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | 4360 pre_div << RT5677_I2S_PD4_SFT; 4361 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4362 RT5677_I2S_DL_MASK, val_len); 4363 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4364 mask_clk, val_clk); 4365 break; 4366 default: 4367 break; 4368 } 4369 4370 return 0; 4371} 4372 4373static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 4374{ 4375 struct snd_soc_component *component = dai->component; 4376 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4377 unsigned int reg_val = 0; 4378 4379 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 4380 case SND_SOC_DAIFMT_CBM_CFM: 4381 rt5677->master[dai->id] = 1; 4382 break; 4383 case SND_SOC_DAIFMT_CBS_CFS: 4384 reg_val |= RT5677_I2S_MS_S; 4385 rt5677->master[dai->id] = 0; 4386 break; 4387 default: 4388 return -EINVAL; 4389 } 4390 4391 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 4392 case SND_SOC_DAIFMT_NB_NF: 4393 break; 4394 case SND_SOC_DAIFMT_IB_NF: 4395 reg_val |= RT5677_I2S_BP_INV; 4396 break; 4397 default: 4398 return -EINVAL; 4399 } 4400 4401 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 4402 case SND_SOC_DAIFMT_I2S: 4403 break; 4404 case SND_SOC_DAIFMT_LEFT_J: 4405 reg_val |= RT5677_I2S_DF_LEFT; 4406 break; 4407 case SND_SOC_DAIFMT_DSP_A: 4408 reg_val |= RT5677_I2S_DF_PCM_A; 4409 break; 4410 case SND_SOC_DAIFMT_DSP_B: 4411 reg_val |= RT5677_I2S_DF_PCM_B; 4412 break; 4413 default: 4414 return -EINVAL; 4415 } 4416 4417 switch (dai->id) { 4418 case RT5677_AIF1: 4419 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4420 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4421 RT5677_I2S_DF_MASK, reg_val); 4422 break; 4423 case RT5677_AIF2: 4424 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4425 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4426 RT5677_I2S_DF_MASK, reg_val); 4427 break; 4428 case RT5677_AIF3: 4429 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4430 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4431 RT5677_I2S_DF_MASK, reg_val); 4432 break; 4433 case RT5677_AIF4: 4434 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4435 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4436 RT5677_I2S_DF_MASK, reg_val); 4437 break; 4438 default: 4439 break; 4440 } 4441 4442 4443 return 0; 4444} 4445 4446static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, 4447 int clk_id, unsigned int freq, int dir) 4448{ 4449 struct snd_soc_component *component = dai->component; 4450 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4451 unsigned int reg_val = 0; 4452 4453 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) 4454 return 0; 4455 4456 switch (clk_id) { 4457 case RT5677_SCLK_S_MCLK: 4458 reg_val |= RT5677_SCLK_SRC_MCLK; 4459 break; 4460 case RT5677_SCLK_S_PLL1: 4461 reg_val |= RT5677_SCLK_SRC_PLL1; 4462 break; 4463 case RT5677_SCLK_S_RCCLK: 4464 reg_val |= RT5677_SCLK_SRC_RCCLK; 4465 break; 4466 default: 4467 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 4468 return -EINVAL; 4469 } 4470 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4471 RT5677_SCLK_SRC_MASK, reg_val); 4472 rt5677->sysclk = freq; 4473 rt5677->sysclk_src = clk_id; 4474 4475 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 4476 4477 return 0; 4478} 4479 4480/** 4481 * rt5677_pll_calc - Calcualte PLL M/N/K code. 4482 * @freq_in: external clock provided to codec. 4483 * @freq_out: target clock which codec works on. 4484 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. 4485 * 4486 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. 4487 * 4488 * Returns 0 for success or negative error code. 4489 */ 4490static int rt5677_pll_calc(const unsigned int freq_in, 4491 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 4492{ 4493 if (RT5677_PLL_INP_MIN > freq_in) 4494 return -EINVAL; 4495 4496 return rl6231_pll_calc(freq_in, freq_out, pll_code); 4497} 4498 4499static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 4500 unsigned int freq_in, unsigned int freq_out) 4501{ 4502 struct snd_soc_component *component = dai->component; 4503 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4504 struct rl6231_pll_code pll_code; 4505 int ret; 4506 4507 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 4508 freq_out == rt5677->pll_out) 4509 return 0; 4510 4511 if (!freq_in || !freq_out) { 4512 dev_dbg(component->dev, "PLL disabled\n"); 4513 4514 rt5677->pll_in = 0; 4515 rt5677->pll_out = 0; 4516 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4517 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); 4518 return 0; 4519 } 4520 4521 switch (source) { 4522 case RT5677_PLL1_S_MCLK: 4523 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4524 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); 4525 break; 4526 case RT5677_PLL1_S_BCLK1: 4527 case RT5677_PLL1_S_BCLK2: 4528 case RT5677_PLL1_S_BCLK3: 4529 case RT5677_PLL1_S_BCLK4: 4530 switch (dai->id) { 4531 case RT5677_AIF1: 4532 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4533 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); 4534 break; 4535 case RT5677_AIF2: 4536 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4537 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); 4538 break; 4539 case RT5677_AIF3: 4540 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4541 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); 4542 break; 4543 case RT5677_AIF4: 4544 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4545 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); 4546 break; 4547 default: 4548 break; 4549 } 4550 break; 4551 default: 4552 dev_err(component->dev, "Unknown PLL source %d\n", source); 4553 return -EINVAL; 4554 } 4555 4556 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); 4557 if (ret < 0) { 4558 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 4559 return ret; 4560 } 4561 4562 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", 4563 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 4564 pll_code.n_code, pll_code.k_code); 4565 4566 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 4567 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); 4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 4569 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT) | 4570 (pll_code.m_bp << RT5677_PLL_M_BP_SFT)); 4571 4572 rt5677->pll_in = freq_in; 4573 rt5677->pll_out = freq_out; 4574 rt5677->pll_src = source; 4575 4576 return 0; 4577} 4578 4579static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 4580 unsigned int rx_mask, int slots, int slot_width) 4581{ 4582 struct snd_soc_component *component = dai->component; 4583 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4584 unsigned int val = 0, slot_width_25 = 0; 4585 4586 if (rx_mask || tx_mask) 4587 val |= (1 << 12); 4588 4589 switch (slots) { 4590 case 4: 4591 val |= (1 << 10); 4592 break; 4593 case 6: 4594 val |= (2 << 10); 4595 break; 4596 case 8: 4597 val |= (3 << 10); 4598 break; 4599 case 2: 4600 default: 4601 break; 4602 } 4603 4604 switch (slot_width) { 4605 case 20: 4606 val |= (1 << 8); 4607 break; 4608 case 25: 4609 slot_width_25 = 0x8080; 4610 fallthrough; 4611 case 24: 4612 val |= (2 << 8); 4613 break; 4614 case 32: 4615 val |= (3 << 8); 4616 break; 4617 case 16: 4618 default: 4619 break; 4620 } 4621 4622 switch (dai->id) { 4623 case RT5677_AIF1: 4624 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, 4625 val); 4626 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, 4627 slot_width_25); 4628 break; 4629 case RT5677_AIF2: 4630 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, 4631 val); 4632 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, 4633 slot_width_25); 4634 break; 4635 default: 4636 break; 4637 } 4638 4639 return 0; 4640} 4641 4642static int rt5677_set_bias_level(struct snd_soc_component *component, 4643 enum snd_soc_bias_level level) 4644{ 4645 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4646 enum snd_soc_bias_level prev_bias = 4647 snd_soc_component_get_bias_level(component); 4648 4649 switch (level) { 4650 case SND_SOC_BIAS_ON: 4651 break; 4652 4653 case SND_SOC_BIAS_PREPARE: 4654 if (prev_bias == SND_SOC_BIAS_STANDBY) { 4655 4656 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4657 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 4658 5 << RT5677_LDO1_SEL_SFT | 4659 5 << RT5677_LDO2_SEL_SFT); 4660 regmap_update_bits(rt5677->regmap, 4661 RT5677_PR_BASE + RT5677_BIAS_CUR4, 4662 0x0f00, 0x0f00); 4663 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4664 RT5677_PWR_FV1 | RT5677_PWR_FV2 | 4665 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4666 RT5677_PWR_BG | RT5677_PWR_VREF2, 4667 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4668 RT5677_PWR_BG | RT5677_PWR_VREF2); 4669 rt5677->is_vref_slow = false; 4670 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4671 RT5677_PWR_CORE, RT5677_PWR_CORE); 4672 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4673 0x1, 0x1); 4674 } 4675 break; 4676 4677 case SND_SOC_BIAS_STANDBY: 4678 if (prev_bias == SND_SOC_BIAS_OFF && 4679 rt5677->dsp_vad_en_request) { 4680 /* Re-enable the DSP if it was turned off at suspend */ 4681 rt5677->dsp_vad_en = true; 4682 /* The delay is to wait for MCLK */ 4683 schedule_delayed_work(&rt5677->dsp_work, 4684 msecs_to_jiffies(1000)); 4685 } 4686 break; 4687 4688 case SND_SOC_BIAS_OFF: 4689 flush_delayed_work(&rt5677->dsp_work); 4690 if (rt5677->is_dsp_mode) { 4691 /* Turn off the DSP before suspend */ 4692 rt5677->dsp_vad_en = false; 4693 schedule_delayed_work(&rt5677->dsp_work, 0); 4694 flush_delayed_work(&rt5677->dsp_work); 4695 } 4696 4697 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 4698 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 4699 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 4700 2 << RT5677_LDO1_SEL_SFT | 4701 2 << RT5677_LDO2_SEL_SFT); 4702 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4703 RT5677_PWR_CORE, 0); 4704 regmap_update_bits(rt5677->regmap, 4705 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4706 4707 if (rt5677->dsp_vad_en) 4708 rt5677_set_dsp_vad(component, true); 4709 break; 4710 4711 default: 4712 break; 4713 } 4714 4715 return 0; 4716} 4717 4718static int rt5677_update_gpio_bits(struct rt5677_priv *rt5677, unsigned offset, int m, int v) 4719{ 4720 unsigned int bank = offset / 5; 4721 unsigned int shift = (offset % 5) * 3; 4722 unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2; 4723 4724 return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift); 4725} 4726 4727#ifdef CONFIG_GPIOLIB 4728static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 4729{ 4730 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4731 int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO; 4732 int m = RT5677_GPIOx_OUT_MASK; 4733 4734 rt5677_update_gpio_bits(rt5677, offset, m, level); 4735} 4736 4737static int rt5677_gpio_direction_out(struct gpio_chip *chip, 4738 unsigned offset, int value) 4739{ 4740 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4741 int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO; 4742 int m = RT5677_GPIOx_DIR_MASK | RT5677_GPIOx_OUT_MASK; 4743 int v = RT5677_GPIOx_DIR_OUT | level; 4744 4745 return rt5677_update_gpio_bits(rt5677, offset, m, v); 4746} 4747 4748static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) 4749{ 4750 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4751 int value, ret; 4752 4753 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); 4754 if (ret < 0) 4755 return ret; 4756 4757 return (value & (0x1 << offset)) >> offset; 4758} 4759 4760static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 4761{ 4762 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4763 int m = RT5677_GPIOx_DIR_MASK; 4764 int v = RT5677_GPIOx_DIR_IN; 4765 4766 return rt5677_update_gpio_bits(rt5677, offset, m, v); 4767} 4768 4769/* 4770 * Configures the GPIO as 4771 * 0 - floating 4772 * 1 - pull down 4773 * 2 - pull up 4774 */ 4775static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4776 int value) 4777{ 4778 int shift; 4779 4780 switch (offset) { 4781 case RT5677_GPIO1 ... RT5677_GPIO2: 4782 shift = 2 * (1 - offset); 4783 regmap_update_bits(rt5677->regmap, 4784 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, 4785 0x3 << shift, 4786 (value & 0x3) << shift); 4787 break; 4788 4789 case RT5677_GPIO3 ... RT5677_GPIO6: 4790 shift = 2 * (9 - offset); 4791 regmap_update_bits(rt5677->regmap, 4792 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, 4793 0x3 << shift, 4794 (value & 0x3) << shift); 4795 break; 4796 4797 default: 4798 break; 4799 } 4800} 4801 4802static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) 4803{ 4804 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4805 int irq; 4806 4807 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || 4808 (rt5677->pdata.jd1_gpio == 2 && 4809 offset == RT5677_GPIO2) || 4810 (rt5677->pdata.jd1_gpio == 3 && 4811 offset == RT5677_GPIO3)) { 4812 irq = RT5677_IRQ_JD1; 4813 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || 4814 (rt5677->pdata.jd2_gpio == 2 && 4815 offset == RT5677_GPIO5) || 4816 (rt5677->pdata.jd2_gpio == 3 && 4817 offset == RT5677_GPIO6)) { 4818 irq = RT5677_IRQ_JD2; 4819 } else if ((rt5677->pdata.jd3_gpio == 1 && 4820 offset == RT5677_GPIO4) || 4821 (rt5677->pdata.jd3_gpio == 2 && 4822 offset == RT5677_GPIO5) || 4823 (rt5677->pdata.jd3_gpio == 3 && 4824 offset == RT5677_GPIO6)) { 4825 irq = RT5677_IRQ_JD3; 4826 } else { 4827 return -ENXIO; 4828 } 4829 4830 return irq_create_mapping(rt5677->domain, irq); 4831} 4832 4833static const struct gpio_chip rt5677_template_chip = { 4834 .label = RT5677_DRV_NAME, 4835 .owner = THIS_MODULE, 4836 .direction_output = rt5677_gpio_direction_out, 4837 .set = rt5677_gpio_set, 4838 .direction_input = rt5677_gpio_direction_in, 4839 .get = rt5677_gpio_get, 4840 .to_irq = rt5677_to_irq, 4841 .can_sleep = 1, 4842}; 4843 4844static void rt5677_init_gpio(struct i2c_client *i2c) 4845{ 4846 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4847 int ret; 4848 4849 rt5677->gpio_chip = rt5677_template_chip; 4850 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; 4851 rt5677->gpio_chip.parent = &i2c->dev; 4852 rt5677->gpio_chip.base = -1; 4853 4854 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); 4855 if (ret != 0) 4856 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); 4857} 4858 4859static void rt5677_free_gpio(struct i2c_client *i2c) 4860{ 4861 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4862 4863 gpiochip_remove(&rt5677->gpio_chip); 4864} 4865#else 4866static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4867 int value) 4868{ 4869} 4870 4871static void rt5677_init_gpio(struct i2c_client *i2c) 4872{ 4873} 4874 4875static void rt5677_free_gpio(struct i2c_client *i2c) 4876{ 4877} 4878#endif 4879 4880static int rt5677_probe(struct snd_soc_component *component) 4881{ 4882 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 4883 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4884 int i; 4885 4886 rt5677->component = component; 4887 4888 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4889 snd_soc_dapm_add_routes(dapm, 4890 rt5677_dmic2_clk_2, 4891 ARRAY_SIZE(rt5677_dmic2_clk_2)); 4892 } else { /*use dmic1 clock by default*/ 4893 snd_soc_dapm_add_routes(dapm, 4894 rt5677_dmic2_clk_1, 4895 ARRAY_SIZE(rt5677_dmic2_clk_1)); 4896 } 4897 4898 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 4899 4900 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4901 ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020); 4902 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 4903 RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO); 4904 4905 for (i = 0; i < RT5677_GPIO_NUM; i++) 4906 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); 4907 4908 mutex_init(&rt5677->dsp_cmd_lock); 4909 mutex_init(&rt5677->dsp_pri_lock); 4910 4911 return 0; 4912} 4913 4914static void rt5677_remove(struct snd_soc_component *component) 4915{ 4916 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4917 4918 cancel_delayed_work_sync(&rt5677->dsp_work); 4919 4920 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4921 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4922 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4923} 4924 4925#ifdef CONFIG_PM 4926static int rt5677_suspend(struct snd_soc_component *component) 4927{ 4928 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4929 4930 if (rt5677->irq) { 4931 cancel_delayed_work_sync(&rt5677->resume_irq_check); 4932 disable_irq(rt5677->irq); 4933 } 4934 4935 if (!rt5677->dsp_vad_en) { 4936 regcache_cache_only(rt5677->regmap, true); 4937 regcache_mark_dirty(rt5677->regmap); 4938 4939 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4940 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4941 } 4942 4943 return 0; 4944} 4945 4946static int rt5677_resume(struct snd_soc_component *component) 4947{ 4948 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4949 4950 if (!rt5677->dsp_vad_en) { 4951 rt5677->pll_src = 0; 4952 rt5677->pll_in = 0; 4953 rt5677->pll_out = 0; 4954 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); 4955 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 4956 if (rt5677->pow_ldo2 || rt5677->reset_pin) 4957 msleep(10); 4958 4959 regcache_cache_only(rt5677->regmap, false); 4960 regcache_sync(rt5677->regmap); 4961 } 4962 4963 if (rt5677->irq) { 4964 enable_irq(rt5677->irq); 4965 schedule_delayed_work(&rt5677->resume_irq_check, 0); 4966 } 4967 4968 return 0; 4969} 4970#else 4971#define rt5677_suspend NULL 4972#define rt5677_resume NULL 4973#endif 4974 4975static int rt5677_read(void *context, unsigned int reg, unsigned int *val) 4976{ 4977 struct i2c_client *client = context; 4978 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4979 4980 if (rt5677->is_dsp_mode) { 4981 if (reg > 0xff) { 4982 mutex_lock(&rt5677->dsp_pri_lock); 4983 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4984 reg & 0xff); 4985 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); 4986 mutex_unlock(&rt5677->dsp_pri_lock); 4987 } else { 4988 rt5677_dsp_mode_i2c_read(rt5677, reg, val); 4989 } 4990 } else { 4991 regmap_read(rt5677->regmap_physical, reg, val); 4992 } 4993 4994 return 0; 4995} 4996 4997static int rt5677_write(void *context, unsigned int reg, unsigned int val) 4998{ 4999 struct i2c_client *client = context; 5000 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 5001 5002 if (rt5677->is_dsp_mode) { 5003 if (reg > 0xff) { 5004 mutex_lock(&rt5677->dsp_pri_lock); 5005 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 5006 reg & 0xff); 5007 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, 5008 val); 5009 mutex_unlock(&rt5677->dsp_pri_lock); 5010 } else { 5011 rt5677_dsp_mode_i2c_write(rt5677, reg, val); 5012 } 5013 } else { 5014 regmap_write(rt5677->regmap_physical, reg, val); 5015 } 5016 5017 return 0; 5018} 5019 5020#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 5021#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 5022 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 5023 5024static const struct snd_soc_dai_ops rt5677_aif_dai_ops = { 5025 .hw_params = rt5677_hw_params, 5026 .set_fmt = rt5677_set_dai_fmt, 5027 .set_sysclk = rt5677_set_dai_sysclk, 5028 .set_pll = rt5677_set_dai_pll, 5029 .set_tdm_slot = rt5677_set_tdm_slot, 5030}; 5031 5032static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = { 5033 .set_sysclk = rt5677_set_dai_sysclk, 5034 .set_pll = rt5677_set_dai_pll, 5035}; 5036 5037static struct snd_soc_dai_driver rt5677_dai[] = { 5038 { 5039 .name = "rt5677-aif1", 5040 .id = RT5677_AIF1, 5041 .playback = { 5042 .stream_name = "AIF1 Playback", 5043 .channels_min = 1, 5044 .channels_max = 2, 5045 .rates = RT5677_STEREO_RATES, 5046 .formats = RT5677_FORMATS, 5047 }, 5048 .capture = { 5049 .stream_name = "AIF1 Capture", 5050 .channels_min = 1, 5051 .channels_max = 2, 5052 .rates = RT5677_STEREO_RATES, 5053 .formats = RT5677_FORMATS, 5054 }, 5055 .ops = &rt5677_aif_dai_ops, 5056 }, 5057 { 5058 .name = "rt5677-aif2", 5059 .id = RT5677_AIF2, 5060 .playback = { 5061 .stream_name = "AIF2 Playback", 5062 .channels_min = 1, 5063 .channels_max = 2, 5064 .rates = RT5677_STEREO_RATES, 5065 .formats = RT5677_FORMATS, 5066 }, 5067 .capture = { 5068 .stream_name = "AIF2 Capture", 5069 .channels_min = 1, 5070 .channels_max = 2, 5071 .rates = RT5677_STEREO_RATES, 5072 .formats = RT5677_FORMATS, 5073 }, 5074 .ops = &rt5677_aif_dai_ops, 5075 }, 5076 { 5077 .name = "rt5677-aif3", 5078 .id = RT5677_AIF3, 5079 .playback = { 5080 .stream_name = "AIF3 Playback", 5081 .channels_min = 1, 5082 .channels_max = 2, 5083 .rates = RT5677_STEREO_RATES, 5084 .formats = RT5677_FORMATS, 5085 }, 5086 .capture = { 5087 .stream_name = "AIF3 Capture", 5088 .channels_min = 1, 5089 .channels_max = 2, 5090 .rates = RT5677_STEREO_RATES, 5091 .formats = RT5677_FORMATS, 5092 }, 5093 .ops = &rt5677_aif_dai_ops, 5094 }, 5095 { 5096 .name = "rt5677-aif4", 5097 .id = RT5677_AIF4, 5098 .playback = { 5099 .stream_name = "AIF4 Playback", 5100 .channels_min = 1, 5101 .channels_max = 2, 5102 .rates = RT5677_STEREO_RATES, 5103 .formats = RT5677_FORMATS, 5104 }, 5105 .capture = { 5106 .stream_name = "AIF4 Capture", 5107 .channels_min = 1, 5108 .channels_max = 2, 5109 .rates = RT5677_STEREO_RATES, 5110 .formats = RT5677_FORMATS, 5111 }, 5112 .ops = &rt5677_aif_dai_ops, 5113 }, 5114 { 5115 .name = "rt5677-slimbus", 5116 .id = RT5677_AIF5, 5117 .playback = { 5118 .stream_name = "SLIMBus Playback", 5119 .channels_min = 1, 5120 .channels_max = 2, 5121 .rates = RT5677_STEREO_RATES, 5122 .formats = RT5677_FORMATS, 5123 }, 5124 .capture = { 5125 .stream_name = "SLIMBus Capture", 5126 .channels_min = 1, 5127 .channels_max = 2, 5128 .rates = RT5677_STEREO_RATES, 5129 .formats = RT5677_FORMATS, 5130 }, 5131 .ops = &rt5677_aif_dai_ops, 5132 }, 5133 { 5134 .name = "rt5677-dspbuffer", 5135 .id = RT5677_DSPBUFF, 5136 .capture = { 5137 .stream_name = "DSP Buffer", 5138 .channels_min = 1, 5139 .channels_max = 1, 5140 .rates = SNDRV_PCM_RATE_16000, 5141 .formats = SNDRV_PCM_FMTBIT_S16_LE, 5142 }, 5143 .ops = &rt5677_dsp_dai_ops, 5144 }, 5145}; 5146 5147static const struct snd_soc_component_driver soc_component_dev_rt5677 = { 5148 .name = RT5677_DRV_NAME, 5149 .probe = rt5677_probe, 5150 .remove = rt5677_remove, 5151 .suspend = rt5677_suspend, 5152 .resume = rt5677_resume, 5153 .set_bias_level = rt5677_set_bias_level, 5154 .controls = rt5677_snd_controls, 5155 .num_controls = ARRAY_SIZE(rt5677_snd_controls), 5156 .dapm_widgets = rt5677_dapm_widgets, 5157 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), 5158 .dapm_routes = rt5677_dapm_routes, 5159 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 5160 .use_pmdown_time = 1, 5161 .endianness = 1, 5162}; 5163 5164static const struct regmap_config rt5677_regmap_physical = { 5165 .name = "physical", 5166 .reg_bits = 8, 5167 .val_bits = 16, 5168 5169 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5170 RT5677_PR_SPACING), 5171 .readable_reg = rt5677_readable_register, 5172 5173 .cache_type = REGCACHE_NONE, 5174 .ranges = rt5677_ranges, 5175 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5176}; 5177 5178static const struct regmap_config rt5677_regmap = { 5179 .reg_bits = 8, 5180 .val_bits = 16, 5181 5182 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5183 RT5677_PR_SPACING), 5184 5185 .volatile_reg = rt5677_volatile_register, 5186 .readable_reg = rt5677_readable_register, 5187 .reg_read = rt5677_read, 5188 .reg_write = rt5677_write, 5189 5190 .cache_type = REGCACHE_RBTREE, 5191 .reg_defaults = rt5677_reg, 5192 .num_reg_defaults = ARRAY_SIZE(rt5677_reg), 5193 .ranges = rt5677_ranges, 5194 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5195}; 5196 5197static const struct of_device_id rt5677_of_match[] = { 5198 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 }, 5199 { } 5200}; 5201MODULE_DEVICE_TABLE(of, rt5677_of_match); 5202 5203static const struct acpi_device_id rt5677_acpi_match[] = { 5204 { "RT5677CE", RT5677 }, 5205 { } 5206}; 5207MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match); 5208 5209static void rt5677_read_device_properties(struct rt5677_priv *rt5677, 5210 struct device *dev) 5211{ 5212 u32 val; 5213 5214 rt5677->pdata.in1_diff = 5215 device_property_read_bool(dev, "IN1") || 5216 device_property_read_bool(dev, "realtek,in1-differential"); 5217 5218 rt5677->pdata.in2_diff = 5219 device_property_read_bool(dev, "IN2") || 5220 device_property_read_bool(dev, "realtek,in2-differential"); 5221 5222 rt5677->pdata.lout1_diff = 5223 device_property_read_bool(dev, "OUT1") || 5224 device_property_read_bool(dev, "realtek,lout1-differential"); 5225 5226 rt5677->pdata.lout2_diff = 5227 device_property_read_bool(dev, "OUT2") || 5228 device_property_read_bool(dev, "realtek,lout2-differential"); 5229 5230 rt5677->pdata.lout3_diff = 5231 device_property_read_bool(dev, "OUT3") || 5232 device_property_read_bool(dev, "realtek,lout3-differential"); 5233 5234 device_property_read_u8_array(dev, "realtek,gpio-config", 5235 rt5677->pdata.gpio_config, 5236 RT5677_GPIO_NUM); 5237 5238 if (!device_property_read_u32(dev, "DCLK", &val) || 5239 !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val)) 5240 rt5677->pdata.dmic2_clk_pin = val; 5241 5242 if (!device_property_read_u32(dev, "JD1", &val) || 5243 !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) 5244 rt5677->pdata.jd1_gpio = val; 5245 5246 if (!device_property_read_u32(dev, "JD2", &val) || 5247 !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) 5248 rt5677->pdata.jd2_gpio = val; 5249 5250 if (!device_property_read_u32(dev, "JD3", &val) || 5251 !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) 5252 rt5677->pdata.jd3_gpio = val; 5253} 5254 5255struct rt5677_irq_desc { 5256 unsigned int enable_mask; 5257 unsigned int status_mask; 5258 unsigned int polarity_mask; 5259}; 5260 5261static const struct rt5677_irq_desc rt5677_irq_descs[] = { 5262 [RT5677_IRQ_JD1] = { 5263 .enable_mask = RT5677_EN_IRQ_GPIO_JD1, 5264 .status_mask = RT5677_STA_GPIO_JD1, 5265 .polarity_mask = RT5677_INV_GPIO_JD1, 5266 }, 5267 [RT5677_IRQ_JD2] = { 5268 .enable_mask = RT5677_EN_IRQ_GPIO_JD2, 5269 .status_mask = RT5677_STA_GPIO_JD2, 5270 .polarity_mask = RT5677_INV_GPIO_JD2, 5271 }, 5272 [RT5677_IRQ_JD3] = { 5273 .enable_mask = RT5677_EN_IRQ_GPIO_JD3, 5274 .status_mask = RT5677_STA_GPIO_JD3, 5275 .polarity_mask = RT5677_INV_GPIO_JD3, 5276 }, 5277}; 5278 5279static bool rt5677_check_hotword(struct rt5677_priv *rt5677) 5280{ 5281 int reg_gpio; 5282 5283 if (!rt5677->is_dsp_mode) 5284 return false; 5285 5286 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio)) 5287 return false; 5288 5289 /* Firmware sets GPIO1 pin to be GPIO1 after hotword is detected */ 5290 if ((reg_gpio & RT5677_GPIO1_PIN_MASK) == RT5677_GPIO1_PIN_IRQ) 5291 return false; 5292 5293 /* Set GPIO1 pin back to be IRQ output for jack detect */ 5294 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5295 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5296 5297 rt5677_spi_hotword_detected(); 5298 return true; 5299} 5300 5301static irqreturn_t rt5677_irq(int unused, void *data) 5302{ 5303 struct rt5677_priv *rt5677 = data; 5304 int ret, loop, i, reg_irq, virq; 5305 bool irq_fired = false; 5306 5307 mutex_lock(&rt5677->irq_lock); 5308 5309 /* 5310 * Loop to handle interrupts until the last i2c read shows no pending 5311 * irqs. The interrupt line is shared by multiple interrupt sources. 5312 * After the regmap_read() below, a new interrupt source line may 5313 * become high before the regmap_write() finishes, so there isn't a 5314 * rising edge on the shared interrupt line for the new interrupt. Thus, 5315 * the loop is needed to avoid missing irqs. 5316 * 5317 * A safeguard of 20 loops is used to avoid hanging in the irq handler 5318 * if there is something wrong with the interrupt status update. The 5319 * interrupt sources here are audio jack plug/unplug events which 5320 * shouldn't happen at a high frequency for a long period of time. 5321 * Empirically, more than 3 loops have never been seen. 5322 */ 5323 for (loop = 0; loop < 20; loop++) { 5324 /* Read interrupt status */ 5325 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq); 5326 if (ret) { 5327 dev_err(rt5677->dev, "failed reading IRQ status: %d\n", 5328 ret); 5329 goto exit; 5330 } 5331 5332 irq_fired = false; 5333 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5334 if (reg_irq & rt5677_irq_descs[i].status_mask) { 5335 irq_fired = true; 5336 virq = irq_find_mapping(rt5677->domain, i); 5337 if (virq) 5338 handle_nested_irq(virq); 5339 5340 /* Clear the interrupt by flipping the polarity 5341 * of the interrupt source line that fired 5342 */ 5343 reg_irq ^= rt5677_irq_descs[i].polarity_mask; 5344 } 5345 } 5346 5347 /* Exit the loop only when we know for sure that GPIO1 pin 5348 * was low at some point since irq_lock was acquired. Any event 5349 * after that point creates a rising edge that triggers another 5350 * call to rt5677_irq(). 5351 */ 5352 if (!irq_fired && !rt5677_check_hotword(rt5677)) 5353 goto exit; 5354 5355 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); 5356 if (ret) { 5357 dev_err(rt5677->dev, "failed updating IRQ status: %d\n", 5358 ret); 5359 goto exit; 5360 } 5361 } 5362exit: 5363 WARN_ON_ONCE(loop == 20); 5364 mutex_unlock(&rt5677->irq_lock); 5365 if (irq_fired) 5366 return IRQ_HANDLED; 5367 else 5368 return IRQ_NONE; 5369} 5370 5371static void rt5677_resume_irq_check(struct work_struct *work) 5372{ 5373 int i, virq; 5374 struct rt5677_priv *rt5677 = 5375 container_of(work, struct rt5677_priv, resume_irq_check.work); 5376 5377 /* This is needed to check and clear the interrupt status register 5378 * at resume. If the headset is plugged/unplugged when the device is 5379 * fully suspended, there won't be a rising edge at resume to trigger 5380 * the interrupt. Without this, we miss the next unplug/plug event. 5381 */ 5382 rt5677_irq(0, rt5677); 5383 5384 /* Call all enabled jack detect irq handlers again. This is needed in 5385 * addition to the above check for a corner case caused by jack gpio 5386 * debounce. After codec irq is disabled at suspend, the delayed work 5387 * scheduled by soc-jack may run and read wrong jack gpio values, since 5388 * the regmap is in cache only mode. At resume, there is no irq because 5389 * rt5677_irq has already ran and cleared the irq status at suspend. 5390 * Without this explicit check, unplug the headset right after suspend 5391 * starts, then after resume the headset is still shown as plugged in. 5392 */ 5393 mutex_lock(&rt5677->irq_lock); 5394 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5395 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) { 5396 virq = irq_find_mapping(rt5677->domain, i); 5397 if (virq) 5398 handle_nested_irq(virq); 5399 } 5400 } 5401 mutex_unlock(&rt5677->irq_lock); 5402} 5403 5404static void rt5677_irq_bus_lock(struct irq_data *data) 5405{ 5406 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5407 5408 mutex_lock(&rt5677->irq_lock); 5409} 5410 5411static void rt5677_irq_bus_sync_unlock(struct irq_data *data) 5412{ 5413 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5414 5415 // Set the enable/disable bits for the jack detect IRQs. 5416 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1, 5417 RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 | 5418 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en); 5419 mutex_unlock(&rt5677->irq_lock); 5420} 5421 5422static void rt5677_irq_enable(struct irq_data *data) 5423{ 5424 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5425 5426 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask; 5427} 5428 5429static void rt5677_irq_disable(struct irq_data *data) 5430{ 5431 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5432 5433 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask; 5434} 5435 5436static struct irq_chip rt5677_irq_chip = { 5437 .name = "rt5677_irq_chip", 5438 .irq_bus_lock = rt5677_irq_bus_lock, 5439 .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock, 5440 .irq_disable = rt5677_irq_disable, 5441 .irq_enable = rt5677_irq_enable, 5442}; 5443 5444static int rt5677_irq_map(struct irq_domain *h, unsigned int virq, 5445 irq_hw_number_t hw) 5446{ 5447 struct rt5677_priv *rt5677 = h->host_data; 5448 5449 irq_set_chip_data(virq, rt5677); 5450 irq_set_chip(virq, &rt5677_irq_chip); 5451 irq_set_nested_thread(virq, 1); 5452 irq_set_noprobe(virq); 5453 return 0; 5454} 5455 5456 5457static const struct irq_domain_ops rt5677_domain_ops = { 5458 .map = rt5677_irq_map, 5459 .xlate = irq_domain_xlate_twocell, 5460}; 5461 5462static int rt5677_init_irq(struct i2c_client *i2c) 5463{ 5464 int ret; 5465 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 5466 unsigned int jd_mask = 0, jd_val = 0; 5467 5468 if (!rt5677->pdata.jd1_gpio && 5469 !rt5677->pdata.jd2_gpio && 5470 !rt5677->pdata.jd3_gpio) 5471 return 0; 5472 5473 if (!i2c->irq) { 5474 dev_err(&i2c->dev, "No interrupt specified\n"); 5475 return -EINVAL; 5476 } 5477 5478 mutex_init(&rt5677->irq_lock); 5479 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check); 5480 5481 /* 5482 * Select RC as the debounce clock so that GPIO works even when 5483 * MCLK is gated which happens when there is no audio stream 5484 * (SND_SOC_BIAS_OFF). 5485 */ 5486 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 5487 RT5677_IRQ_DEBOUNCE_SEL_MASK, 5488 RT5677_IRQ_DEBOUNCE_SEL_RC); 5489 /* Enable auto power on RC when GPIO states are changed */ 5490 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff); 5491 5492 /* Select and enable jack detection sources per platform data */ 5493 if (rt5677->pdata.jd1_gpio) { 5494 jd_mask |= RT5677_SEL_GPIO_JD1_MASK; 5495 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT; 5496 } 5497 if (rt5677->pdata.jd2_gpio) { 5498 jd_mask |= RT5677_SEL_GPIO_JD2_MASK; 5499 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT; 5500 } 5501 if (rt5677->pdata.jd3_gpio) { 5502 jd_mask |= RT5677_SEL_GPIO_JD3_MASK; 5503 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT; 5504 } 5505 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val); 5506 5507 /* Set GPIO1 pin to be IRQ output */ 5508 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5509 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5510 5511 /* Ready to listen for interrupts */ 5512 rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev), 5513 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677); 5514 if (!rt5677->domain) { 5515 dev_err(&i2c->dev, "Failed to create IRQ domain\n"); 5516 return -ENOMEM; 5517 } 5518 5519 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq, 5520 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5521 "rt5677", rt5677); 5522 if (ret) 5523 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 5524 5525 rt5677->irq = i2c->irq; 5526 5527 return ret; 5528} 5529 5530static int rt5677_i2c_probe(struct i2c_client *i2c) 5531{ 5532 struct device *dev = &i2c->dev; 5533 struct rt5677_priv *rt5677; 5534 int ret; 5535 unsigned int val; 5536 5537 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), 5538 GFP_KERNEL); 5539 if (rt5677 == NULL) 5540 return -ENOMEM; 5541 5542 rt5677->dev = &i2c->dev; 5543 rt5677->set_dsp_vad = rt5677_set_dsp_vad; 5544 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work); 5545 i2c_set_clientdata(i2c, rt5677); 5546 5547 rt5677->type = (enum rt5677_type)(uintptr_t)device_get_match_data(dev); 5548 if (rt5677->type == 0) 5549 return -EINVAL; 5550 5551 rt5677_read_device_properties(rt5677, &i2c->dev); 5552 5553 /* pow-ldo2 and reset are optional. The codec pins may be statically 5554 * connected on the board without gpios. If the gpio device property 5555 * isn't specified, devm_gpiod_get_optional returns NULL. 5556 */ 5557 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, 5558 "realtek,pow-ldo2", GPIOD_OUT_HIGH); 5559 if (IS_ERR(rt5677->pow_ldo2)) { 5560 ret = PTR_ERR(rt5677->pow_ldo2); 5561 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); 5562 return ret; 5563 } 5564 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, 5565 "realtek,reset", GPIOD_OUT_LOW); 5566 if (IS_ERR(rt5677->reset_pin)) { 5567 ret = PTR_ERR(rt5677->reset_pin); 5568 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); 5569 return ret; 5570 } 5571 5572 if (rt5677->pow_ldo2 || rt5677->reset_pin) { 5573 /* Wait a while until I2C bus becomes available. The datasheet 5574 * does not specify the exact we should wait but startup 5575 * sequence mentiones at least a few milliseconds. 5576 */ 5577 msleep(10); 5578 } 5579 5580 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, 5581 &rt5677_regmap_physical); 5582 if (IS_ERR(rt5677->regmap_physical)) { 5583 ret = PTR_ERR(rt5677->regmap_physical); 5584 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5585 ret); 5586 return ret; 5587 } 5588 5589 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); 5590 if (IS_ERR(rt5677->regmap)) { 5591 ret = PTR_ERR(rt5677->regmap); 5592 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5593 ret); 5594 return ret; 5595 } 5596 5597 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); 5598 if (val != RT5677_DEVICE_ID) { 5599 dev_err(&i2c->dev, 5600 "Device with ID register %#x is not rt5677\n", val); 5601 return -ENODEV; 5602 } 5603 5604 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 5605 5606 ret = regmap_register_patch(rt5677->regmap, init_list, 5607 ARRAY_SIZE(init_list)); 5608 if (ret != 0) 5609 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 5610 5611 if (rt5677->pdata.in1_diff) 5612 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5613 RT5677_IN_DF1, RT5677_IN_DF1); 5614 5615 if (rt5677->pdata.in2_diff) 5616 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5617 RT5677_IN_DF2, RT5677_IN_DF2); 5618 5619 if (rt5677->pdata.lout1_diff) 5620 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5621 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); 5622 5623 if (rt5677->pdata.lout2_diff) 5624 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5625 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); 5626 5627 if (rt5677->pdata.lout3_diff) 5628 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5629 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); 5630 5631 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 5632 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, 5633 RT5677_GPIO5_FUNC_MASK, 5634 RT5677_GPIO5_FUNC_DMIC); 5635 rt5677_update_gpio_bits(rt5677, RT5677_GPIO5, 5636 RT5677_GPIOx_DIR_MASK, 5637 RT5677_GPIOx_DIR_OUT); 5638 } 5639 5640 if (rt5677->pdata.micbias1_vdd_3v3) 5641 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, 5642 RT5677_MICBIAS1_CTRL_VDD_MASK, 5643 RT5677_MICBIAS1_CTRL_VDD_3_3V); 5644 5645 rt5677_init_gpio(i2c); 5646 ret = rt5677_init_irq(i2c); 5647 if (ret) 5648 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret); 5649 5650 return devm_snd_soc_register_component(&i2c->dev, 5651 &soc_component_dev_rt5677, 5652 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 5653} 5654 5655static void rt5677_i2c_remove(struct i2c_client *i2c) 5656{ 5657 rt5677_free_gpio(i2c); 5658} 5659 5660static struct i2c_driver rt5677_i2c_driver = { 5661 .driver = { 5662 .name = RT5677_DRV_NAME, 5663 .of_match_table = rt5677_of_match, 5664 .acpi_match_table = rt5677_acpi_match, 5665 }, 5666 .probe = rt5677_i2c_probe, 5667 .remove = rt5677_i2c_remove, 5668}; 5669module_i2c_driver(rt5677_i2c_driver); 5670 5671MODULE_DESCRIPTION("ASoC RT5677 driver"); 5672MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 5673MODULE_LICENSE("GPL v2"); 5674 5675MODULE_FIRMWARE("rt5677_elf_vad"); 5676