1// SPDX-License-Identifier: GPL-2.0 2// 3// rt1016.c -- RT1016 ALSA SoC audio amplifier driver 4// 5// Copyright 2020 Realtek Semiconductor Corp. 6// Author: Oder Chiou <oder_chiou@realtek.com> 7// 8 9#include <linux/fs.h> 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/init.h> 13#include <linux/delay.h> 14#include <linux/pm.h> 15#include <linux/regmap.h> 16#include <linux/i2c.h> 17#include <linux/platform_device.h> 18#include <linux/firmware.h> 19#include <sound/core.h> 20#include <sound/pcm.h> 21#include <sound/pcm_params.h> 22#include <sound/soc.h> 23#include <sound/soc-dapm.h> 24#include <sound/initval.h> 25#include <sound/tlv.h> 26 27#include "rl6231.h" 28#include "rt1016.h" 29 30static const struct reg_sequence rt1016_patch[] = { 31 {RT1016_VOL_CTRL_3, 0x8900}, 32 {RT1016_ANA_CTRL_1, 0xa002}, 33 {RT1016_ANA_CTRL_2, 0x0002}, 34 {RT1016_CLOCK_4, 0x6700}, 35 {RT1016_CLASSD_3, 0xdc55}, 36 {RT1016_CLASSD_4, 0x376a}, 37 {RT1016_CLASSD_5, 0x009f}, 38}; 39 40static const struct reg_default rt1016_reg[] = { 41 {0x00, 0x0000}, 42 {0x01, 0x5400}, 43 {0x02, 0x5506}, 44 {0x03, 0xf800}, 45 {0x04, 0x0000}, 46 {0x05, 0xbfbf}, 47 {0x06, 0x8900}, 48 {0x07, 0xa002}, 49 {0x08, 0x0000}, 50 {0x09, 0x0000}, 51 {0x0a, 0x0000}, 52 {0x0c, 0x0000}, 53 {0x0d, 0x0000}, 54 {0x0e, 0x10ec}, 55 {0x0f, 0x6595}, 56 {0x11, 0x0002}, 57 {0x1c, 0x0000}, 58 {0x1d, 0x0000}, 59 {0x1e, 0x0000}, 60 {0x1f, 0xf000}, 61 {0x20, 0x0000}, 62 {0x21, 0x6000}, 63 {0x22, 0x0000}, 64 {0x23, 0x6700}, 65 {0x24, 0x0000}, 66 {0x25, 0x0000}, 67 {0x26, 0x0000}, 68 {0x40, 0x0018}, 69 {0x60, 0x00a5}, 70 {0x80, 0x0010}, 71 {0x81, 0x0009}, 72 {0x82, 0x0000}, 73 {0x83, 0x0000}, 74 {0xa0, 0x0700}, 75 {0xc0, 0x0080}, 76 {0xc1, 0x02a0}, 77 {0xc2, 0x1400}, 78 {0xc3, 0x0a4a}, 79 {0xc4, 0x552a}, 80 {0xc5, 0x087e}, 81 {0xc6, 0x0020}, 82 {0xc7, 0xa833}, 83 {0xc8, 0x0433}, 84 {0xc9, 0x8040}, 85 {0xca, 0xdc55}, 86 {0xcb, 0x376a}, 87 {0xcc, 0x009f}, 88 {0xcf, 0x0020}, 89}; 90 91static bool rt1016_volatile_register(struct device *dev, unsigned int reg) 92{ 93 switch (reg) { 94 case RT1016_ANA_FLAG: 95 case RT1016_VERSION2_ID: 96 case RT1016_VERSION1_ID: 97 case RT1016_VENDER_ID: 98 case RT1016_DEVICE_ID: 99 case RT1016_TEST_SIGNAL: 100 case RT1016_SC_CTRL_1: 101 return true; 102 103 default: 104 return false; 105 } 106} 107 108static bool rt1016_readable_register(struct device *dev, unsigned int reg) 109{ 110 switch (reg) { 111 case RT1016_RESET: 112 case RT1016_PADS_CTRL_1: 113 case RT1016_PADS_CTRL_2: 114 case RT1016_I2C_CTRL: 115 case RT1016_VOL_CTRL_1: 116 case RT1016_VOL_CTRL_2: 117 case RT1016_VOL_CTRL_3: 118 case RT1016_ANA_CTRL_1: 119 case RT1016_MUX_SEL: 120 case RT1016_RX_I2S_CTRL: 121 case RT1016_ANA_FLAG: 122 case RT1016_VERSION2_ID: 123 case RT1016_VERSION1_ID: 124 case RT1016_VENDER_ID: 125 case RT1016_DEVICE_ID: 126 case RT1016_ANA_CTRL_2: 127 case RT1016_TEST_SIGNAL: 128 case RT1016_TEST_CTRL_1: 129 case RT1016_TEST_CTRL_2: 130 case RT1016_TEST_CTRL_3: 131 case RT1016_CLOCK_1: 132 case RT1016_CLOCK_2: 133 case RT1016_CLOCK_3: 134 case RT1016_CLOCK_4: 135 case RT1016_CLOCK_5: 136 case RT1016_CLOCK_6: 137 case RT1016_CLOCK_7: 138 case RT1016_I2S_CTRL: 139 case RT1016_DAC_CTRL_1: 140 case RT1016_SC_CTRL_1: 141 case RT1016_SC_CTRL_2: 142 case RT1016_SC_CTRL_3: 143 case RT1016_SC_CTRL_4: 144 case RT1016_SIL_DET: 145 case RT1016_SYS_CLK: 146 case RT1016_BIAS_CUR: 147 case RT1016_DAC_CTRL_2: 148 case RT1016_LDO_CTRL: 149 case RT1016_CLASSD_1: 150 case RT1016_PLL1: 151 case RT1016_PLL2: 152 case RT1016_PLL3: 153 case RT1016_CLASSD_2: 154 case RT1016_CLASSD_OUT: 155 case RT1016_CLASSD_3: 156 case RT1016_CLASSD_4: 157 case RT1016_CLASSD_5: 158 case RT1016_PWR_CTRL: 159 return true; 160 161 default: 162 return false; 163 } 164} 165 166static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9550, 50, 0); 167 168static const struct snd_kcontrol_new rt1016_snd_controls[] = { 169 SOC_DOUBLE_TLV("DAC Playback Volume", RT1016_VOL_CTRL_2, 170 RT1016_L_VOL_SFT, RT1016_R_VOL_SFT, 191, 0, dac_vol_tlv), 171 SOC_DOUBLE("DAC Playback Switch", RT1016_VOL_CTRL_1, 172 RT1016_DA_MUTE_L_SFT, RT1016_DA_MUTE_R_SFT, 1, 1), 173}; 174 175static int rt1016_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 176 struct snd_soc_dapm_widget *sink) 177{ 178 struct snd_soc_component *component = 179 snd_soc_dapm_to_component(source->dapm); 180 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 181 182 if (rt1016->sysclk_src == RT1016_SCLK_S_PLL) 183 return 1; 184 else 185 return 0; 186} 187 188/* Interface data select */ 189static const char * const rt1016_data_select[] = { 190 "L/R", "R/L", "L/L", "R/R" 191}; 192 193static SOC_ENUM_SINGLE_DECL(rt1016_if_data_swap_enum, 194 RT1016_I2S_CTRL, RT1016_I2S_DATA_SWAP_SFT, rt1016_data_select); 195 196static const struct snd_kcontrol_new rt1016_if_data_swap_mux = 197 SOC_DAPM_ENUM("Data Swap Mux", rt1016_if_data_swap_enum); 198 199static const struct snd_soc_dapm_widget rt1016_dapm_widgets[] = { 200 SND_SOC_DAPM_MUX("Data Swap Mux", SND_SOC_NOPM, 0, 0, 201 &rt1016_if_data_swap_mux), 202 203 SND_SOC_DAPM_SUPPLY("DAC Filter", RT1016_CLOCK_3, 204 RT1016_PWR_DAC_FILTER_BIT, 0, NULL, 0), 205 SND_SOC_DAPM_SUPPLY("DAMOD", RT1016_CLOCK_3, RT1016_PWR_DACMOD_BIT, 0, 206 NULL, 0), 207 SND_SOC_DAPM_SUPPLY("FIFO", RT1016_CLOCK_3, RT1016_PWR_CLK_FIFO_BIT, 0, 208 NULL, 0), 209 SND_SOC_DAPM_SUPPLY("Pure DC", RT1016_CLOCK_3, 210 RT1016_PWR_CLK_PUREDC_BIT, 0, NULL, 0), 211 SND_SOC_DAPM_SUPPLY("CLK Silence Det", RT1016_CLOCK_3, 212 RT1016_PWR_SIL_DET_BIT, 0, NULL, 0), 213 SND_SOC_DAPM_SUPPLY("RC 25M", RT1016_CLOCK_3, RT1016_PWR_RC_25M_BIT, 0, 214 NULL, 0), 215 SND_SOC_DAPM_SUPPLY("PLL1", RT1016_CLOCK_3, RT1016_PWR_PLL1_BIT, 0, 216 NULL, 0), 217 SND_SOC_DAPM_SUPPLY("ANA CTRL", RT1016_CLOCK_3, RT1016_PWR_ANA_CTRL_BIT, 218 0, NULL, 0), 219 SND_SOC_DAPM_SUPPLY("CLK SYS", RT1016_CLOCK_3, RT1016_PWR_CLK_SYS_BIT, 220 0, NULL, 0), 221 222 SND_SOC_DAPM_SUPPLY("LRCK Det", RT1016_CLOCK_4, RT1016_PWR_LRCK_DET_BIT, 223 0, NULL, 0), 224 SND_SOC_DAPM_SUPPLY("BCLK Det", RT1016_CLOCK_4, RT1016_PWR_BCLK_DET_BIT, 225 0, NULL, 0), 226 227 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1016_DAC_CTRL_2, 228 RT1016_CKGEN_DAC_BIT, 0, NULL, 0), 229 SND_SOC_DAPM_SUPPLY("VCM SLOW", RT1016_CLASSD_1, RT1016_VCM_SLOW_BIT, 0, 230 NULL, 0), 231 SND_SOC_DAPM_SUPPLY("Silence Det", RT1016_SIL_DET, 232 RT1016_SIL_DET_EN_BIT, 0, NULL, 0), 233 SND_SOC_DAPM_SUPPLY("PLL2", RT1016_PLL2, RT1016_PLL2_EN_BIT, 0, NULL, 234 0), 235 236 SND_SOC_DAPM_SUPPLY_S("BG1 BG2", 1, RT1016_PWR_CTRL, 237 RT1016_PWR_BG_1_2_BIT, 0, NULL, 0), 238 SND_SOC_DAPM_SUPPLY_S("MBIAS BG", 1, RT1016_PWR_CTRL, 239 RT1016_PWR_MBIAS_BG_BIT, 0, NULL, 0), 240 SND_SOC_DAPM_SUPPLY_S("PLL", 1, RT1016_PWR_CTRL, RT1016_PWR_PLL_BIT, 0, 241 NULL, 0), 242 SND_SOC_DAPM_SUPPLY_S("BASIC", 1, RT1016_PWR_CTRL, RT1016_PWR_BASIC_BIT, 243 0, NULL, 0), 244 SND_SOC_DAPM_SUPPLY_S("CLASS D", 1, RT1016_PWR_CTRL, 245 RT1016_PWR_CLSD_BIT, 0, NULL, 0), 246 SND_SOC_DAPM_SUPPLY_S("25M", 1, RT1016_PWR_CTRL, RT1016_PWR_25M_BIT, 0, 247 NULL, 0), 248 SND_SOC_DAPM_SUPPLY_S("DACL", 1, RT1016_PWR_CTRL, RT1016_PWR_DACL_BIT, 249 0, NULL, 0), 250 SND_SOC_DAPM_SUPPLY_S("DACR", 1, RT1016_PWR_CTRL, RT1016_PWR_DACR_BIT, 251 0, NULL, 0), 252 SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT1016_PWR_CTRL, RT1016_PWR_LDO2_BIT, 253 0, NULL, 0), 254 SND_SOC_DAPM_SUPPLY_S("VREF", 1, RT1016_PWR_CTRL, RT1016_PWR_VREF_BIT, 255 0, NULL, 0), 256 SND_SOC_DAPM_SUPPLY_S("MBIAS", 1, RT1016_PWR_CTRL, RT1016_PWR_MBIAS_BIT, 257 0, NULL, 0), 258 259 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 260 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 261 262 SND_SOC_DAPM_OUTPUT("SPO"), 263}; 264 265static const struct snd_soc_dapm_route rt1016_dapm_routes[] = { 266 { "Data Swap Mux", "L/R", "AIFRX" }, 267 { "Data Swap Mux", "R/L", "AIFRX" }, 268 { "Data Swap Mux", "L/L", "AIFRX" }, 269 { "Data Swap Mux", "R/R", "AIFRX" }, 270 271 { "DAC", NULL, "DAC Filter" }, 272 { "DAC", NULL, "DAMOD" }, 273 { "DAC", NULL, "FIFO" }, 274 { "DAC", NULL, "Pure DC" }, 275 { "DAC", NULL, "Silence Det" }, 276 { "DAC", NULL, "ANA CTRL" }, 277 { "DAC", NULL, "CLK SYS" }, 278 { "DAC", NULL, "LRCK Det" }, 279 { "DAC", NULL, "BCLK Det" }, 280 { "DAC", NULL, "CKGEN DAC" }, 281 { "DAC", NULL, "VCM SLOW" }, 282 283 { "PLL", NULL, "PLL1" }, 284 { "PLL", NULL, "PLL2" }, 285 { "25M", NULL, "RC 25M" }, 286 { "Silence Det", NULL, "CLK Silence Det" }, 287 288 { "DAC", NULL, "Data Swap Mux" }, 289 { "DAC", NULL, "BG1 BG2" }, 290 { "DAC", NULL, "MBIAS BG" }, 291 { "DAC", NULL, "PLL", rt1016_is_sys_clk_from_pll}, 292 { "DAC", NULL, "BASIC" }, 293 { "DAC", NULL, "CLASS D" }, 294 { "DAC", NULL, "25M" }, 295 { "DAC", NULL, "DACL" }, 296 { "DAC", NULL, "DACR" }, 297 { "DAC", NULL, "LDO2" }, 298 { "DAC", NULL, "VREF" }, 299 { "DAC", NULL, "MBIAS" }, 300 301 { "SPO", NULL, "DAC" }, 302}; 303 304static int rt1016_hw_params(struct snd_pcm_substream *substream, 305 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 306{ 307 struct snd_soc_component *component = dai->component; 308 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 309 int pre_div, bclk_ms, frame_size; 310 unsigned int val_len = 0; 311 312 rt1016->lrck = params_rate(params); 313 pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck); 314 if (pre_div < 0) { 315 dev_err(component->dev, "Unsupported clock rate\n"); 316 return -EINVAL; 317 } 318 319 frame_size = snd_soc_params_to_frame_size(params); 320 if (frame_size < 0) { 321 dev_err(component->dev, "Unsupported frame size: %d\n", 322 frame_size); 323 return -EINVAL; 324 } 325 326 bclk_ms = frame_size > 32; 327 rt1016->bclk = rt1016->lrck * (32 << bclk_ms); 328 329 if (bclk_ms && rt1016->master) 330 snd_soc_component_update_bits(component, RT1016_I2S_CTRL, 331 RT1016_I2S_BCLK_MS_MASK, RT1016_I2S_BCLK_MS_64); 332 333 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 334 rt1016->lrck, pre_div, dai->id); 335 336 switch (params_width(params)) { 337 case 16: 338 val_len = RT1016_I2S_DL_16; 339 break; 340 case 20: 341 val_len = RT1016_I2S_DL_20; 342 break; 343 case 24: 344 val_len = RT1016_I2S_DL_24; 345 break; 346 case 32: 347 val_len = RT1016_I2S_DL_32; 348 break; 349 default: 350 return -EINVAL; 351 } 352 353 snd_soc_component_update_bits(component, RT1016_I2S_CTRL, 354 RT1016_I2S_DL_MASK, val_len); 355 snd_soc_component_update_bits(component, RT1016_CLOCK_2, 356 RT1016_FS_PD_MASK | RT1016_OSR_PD_MASK, 357 ((pre_div + 3) << RT1016_FS_PD_SFT) | 358 (pre_div << RT1016_OSR_PD_SFT)); 359 360 return 0; 361} 362 363static int rt1016_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 364{ 365 struct snd_soc_component *component = dai->component; 366 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 367 unsigned int reg_val = 0; 368 369 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 370 case SND_SOC_DAIFMT_CBM_CFM: 371 reg_val |= RT1016_I2S_MS_M; 372 rt1016->master = 1; 373 break; 374 case SND_SOC_DAIFMT_CBS_CFS: 375 reg_val |= RT1016_I2S_MS_S; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 382 case SND_SOC_DAIFMT_NB_NF: 383 break; 384 case SND_SOC_DAIFMT_IB_NF: 385 reg_val |= RT1016_I2S_BCLK_POL_INV; 386 break; 387 default: 388 return -EINVAL; 389 } 390 391 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 392 case SND_SOC_DAIFMT_I2S: 393 break; 394 395 case SND_SOC_DAIFMT_LEFT_J: 396 reg_val |= RT1016_I2S_DF_LEFT; 397 break; 398 399 case SND_SOC_DAIFMT_DSP_A: 400 reg_val |= RT1016_I2S_DF_PCM_A; 401 break; 402 403 case SND_SOC_DAIFMT_DSP_B: 404 reg_val |= RT1016_I2S_DF_PCM_B; 405 break; 406 407 default: 408 return -EINVAL; 409 } 410 411 snd_soc_component_update_bits(component, RT1016_I2S_CTRL, 412 RT1016_I2S_MS_MASK | RT1016_I2S_BCLK_POL_MASK | 413 RT1016_I2S_DF_MASK, reg_val); 414 415 return 0; 416} 417 418static int rt1016_set_component_sysclk(struct snd_soc_component *component, 419 int clk_id, int source, unsigned int freq, int dir) 420{ 421 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 422 unsigned int reg_val = 0; 423 424 if (freq == rt1016->sysclk && clk_id == rt1016->sysclk_src) 425 return 0; 426 427 switch (clk_id) { 428 case RT1016_SCLK_S_MCLK: 429 reg_val |= RT1016_CLK_SYS_SEL_MCLK; 430 break; 431 432 case RT1016_SCLK_S_PLL: 433 reg_val |= RT1016_CLK_SYS_SEL_PLL; 434 break; 435 436 default: 437 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 438 return -EINVAL; 439 } 440 441 rt1016->sysclk = freq; 442 rt1016->sysclk_src = clk_id; 443 444 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 445 freq, clk_id); 446 447 snd_soc_component_update_bits(component, RT1016_CLOCK_1, 448 RT1016_CLK_SYS_SEL_MASK, reg_val); 449 450 return 0; 451} 452 453static int rt1016_set_component_pll(struct snd_soc_component *component, 454 int pll_id, int source, unsigned int freq_in, 455 unsigned int freq_out) 456{ 457 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 458 struct rl6231_pll_code pll_code; 459 int ret; 460 461 if (!freq_in || !freq_out) { 462 dev_dbg(component->dev, "PLL disabled\n"); 463 464 rt1016->pll_in = 0; 465 rt1016->pll_out = 0; 466 467 return 0; 468 } 469 470 if (source == rt1016->pll_src && freq_in == rt1016->pll_in && 471 freq_out == rt1016->pll_out) 472 return 0; 473 474 switch (source) { 475 case RT1016_PLL_S_MCLK: 476 snd_soc_component_update_bits(component, RT1016_CLOCK_1, 477 RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_MCLK); 478 break; 479 480 case RT1016_PLL_S_BCLK: 481 snd_soc_component_update_bits(component, RT1016_CLOCK_1, 482 RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_BCLK); 483 break; 484 485 default: 486 dev_err(component->dev, "Unknown PLL Source %d\n", source); 487 return -EINVAL; 488 } 489 490 ret = rl6231_pll_calc(freq_in, freq_out * 4, &pll_code); 491 if (ret < 0) { 492 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 493 return ret; 494 } 495 496 dev_dbg(component->dev, "mbypass=%d m=%d n=%d kbypass=%d k=%d\n", 497 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 498 pll_code.n_code, pll_code.k_bp, 499 (pll_code.k_bp ? 0 : pll_code.k_code)); 500 501 snd_soc_component_write(component, RT1016_PLL1, 502 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1016_PLL_M_SFT) | 503 (pll_code.m_bp << RT1016_PLL_M_BP_SFT) | 504 pll_code.n_code); 505 snd_soc_component_write(component, RT1016_PLL2, 506 (pll_code.k_bp << RT1016_PLL_K_BP_SFT) | 507 (pll_code.k_bp ? 0 : pll_code.k_code)); 508 509 rt1016->pll_in = freq_in; 510 rt1016->pll_out = freq_out; 511 rt1016->pll_src = source; 512 513 return 0; 514} 515 516static int rt1016_probe(struct snd_soc_component *component) 517{ 518 struct rt1016_priv *rt1016 = 519 snd_soc_component_get_drvdata(component); 520 521 rt1016->component = component; 522 523 return 0; 524} 525 526static void rt1016_remove(struct snd_soc_component *component) 527{ 528 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 529 530 regmap_write(rt1016->regmap, RT1016_RESET, 0); 531} 532 533#define RT1016_STEREO_RATES SNDRV_PCM_RATE_8000_48000 534#define RT1016_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 535 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 536 537static const struct snd_soc_dai_ops rt1016_aif_dai_ops = { 538 .hw_params = rt1016_hw_params, 539 .set_fmt = rt1016_set_dai_fmt, 540}; 541 542static struct snd_soc_dai_driver rt1016_dai[] = { 543 { 544 .name = "rt1016-aif", 545 .id = 0, 546 .playback = { 547 .stream_name = "AIF Playback", 548 .channels_min = 1, 549 .channels_max = 2, 550 .rates = RT1016_STEREO_RATES, 551 .formats = RT1016_FORMATS, 552 }, 553 .ops = &rt1016_aif_dai_ops, 554 } 555}; 556 557#ifdef CONFIG_PM 558static int rt1016_suspend(struct snd_soc_component *component) 559{ 560 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 561 562 regcache_cache_only(rt1016->regmap, true); 563 regcache_mark_dirty(rt1016->regmap); 564 565 return 0; 566} 567 568static int rt1016_resume(struct snd_soc_component *component) 569{ 570 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component); 571 572 regcache_cache_only(rt1016->regmap, false); 573 regcache_sync(rt1016->regmap); 574 575 return 0; 576} 577#else 578#define rt1016_suspend NULL 579#define rt1016_resume NULL 580#endif 581 582static const struct snd_soc_component_driver soc_component_dev_rt1016 = { 583 .probe = rt1016_probe, 584 .remove = rt1016_remove, 585 .suspend = rt1016_suspend, 586 .resume = rt1016_resume, 587 .controls = rt1016_snd_controls, 588 .num_controls = ARRAY_SIZE(rt1016_snd_controls), 589 .dapm_widgets = rt1016_dapm_widgets, 590 .num_dapm_widgets = ARRAY_SIZE(rt1016_dapm_widgets), 591 .dapm_routes = rt1016_dapm_routes, 592 .num_dapm_routes = ARRAY_SIZE(rt1016_dapm_routes), 593 .set_sysclk = rt1016_set_component_sysclk, 594 .set_pll = rt1016_set_component_pll, 595 .use_pmdown_time = 1, 596 .endianness = 1, 597}; 598 599static const struct regmap_config rt1016_regmap = { 600 .reg_bits = 8, 601 .val_bits = 16, 602 .max_register = RT1016_PWR_CTRL, 603 .volatile_reg = rt1016_volatile_register, 604 .readable_reg = rt1016_readable_register, 605 .cache_type = REGCACHE_RBTREE, 606 .reg_defaults = rt1016_reg, 607 .num_reg_defaults = ARRAY_SIZE(rt1016_reg), 608}; 609 610static const struct i2c_device_id rt1016_i2c_id[] = { 611 { "rt1016", 0 }, 612 { } 613}; 614MODULE_DEVICE_TABLE(i2c, rt1016_i2c_id); 615 616#if defined(CONFIG_OF) 617static const struct of_device_id rt1016_of_match[] = { 618 { .compatible = "realtek,rt1016", }, 619 {}, 620}; 621MODULE_DEVICE_TABLE(of, rt1016_of_match); 622#endif 623 624#ifdef CONFIG_ACPI 625static const struct acpi_device_id rt1016_acpi_match[] = { 626 {"10EC1016", 0,}, 627 {}, 628}; 629MODULE_DEVICE_TABLE(acpi, rt1016_acpi_match); 630#endif 631 632static int rt1016_i2c_probe(struct i2c_client *i2c) 633{ 634 struct rt1016_priv *rt1016; 635 int ret; 636 unsigned int val; 637 638 rt1016 = devm_kzalloc(&i2c->dev, sizeof(struct rt1016_priv), 639 GFP_KERNEL); 640 if (rt1016 == NULL) 641 return -ENOMEM; 642 643 i2c_set_clientdata(i2c, rt1016); 644 645 rt1016->regmap = devm_regmap_init_i2c(i2c, &rt1016_regmap); 646 if (IS_ERR(rt1016->regmap)) { 647 ret = PTR_ERR(rt1016->regmap); 648 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 649 ret); 650 return ret; 651 } 652 653 regmap_read(rt1016->regmap, RT1016_DEVICE_ID, &val); 654 if (val != RT1016_DEVICE_ID_VAL) { 655 dev_err(&i2c->dev, 656 "Device with ID register %x is not rt1016\n", val); 657 return -ENODEV; 658 } 659 660 regmap_write(rt1016->regmap, RT1016_RESET, 0); 661 662 ret = regmap_register_patch(rt1016->regmap, rt1016_patch, 663 ARRAY_SIZE(rt1016_patch)); 664 if (ret != 0) 665 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 666 667 return devm_snd_soc_register_component(&i2c->dev, 668 &soc_component_dev_rt1016, 669 rt1016_dai, ARRAY_SIZE(rt1016_dai)); 670} 671 672static void rt1016_i2c_shutdown(struct i2c_client *client) 673{ 674 struct rt1016_priv *rt1016 = i2c_get_clientdata(client); 675 676 regmap_write(rt1016->regmap, RT1016_RESET, 0); 677} 678 679static struct i2c_driver rt1016_i2c_driver = { 680 .driver = { 681 .name = "rt1016", 682 .of_match_table = of_match_ptr(rt1016_of_match), 683 .acpi_match_table = ACPI_PTR(rt1016_acpi_match), 684 }, 685 .probe = rt1016_i2c_probe, 686 .shutdown = rt1016_i2c_shutdown, 687 .id_table = rt1016_i2c_id, 688}; 689module_i2c_driver(rt1016_i2c_driver); 690 691MODULE_DESCRIPTION("ASoC RT1016 driver"); 692MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 693MODULE_LICENSE("GPL v2"); 694