1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * rl6231.c - RL6231 class device shared support
4 *
5 * Copyright 2014 Realtek Semiconductor Corp.
6 *
7 * Author: Oder Chiou <oder_chiou@realtek.com>
8 */
9
10#include <linux/module.h>
11#include <linux/regmap.h>
12
13#include <linux/gcd.h>
14#include "rl6231.h"
15
16/**
17 * rl6231_get_pre_div - Return the value of pre divider.
18 *
19 * @map: map for setting.
20 * @reg: register.
21 * @sft: shift.
22 *
23 * Return the value of pre divider from given register value.
24 * Return negative error code for unexpected register value.
25 */
26int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
27{
28	int pd, val;
29
30	regmap_read(map, reg, &val);
31
32	val = (val >> sft) & 0x7;
33
34	switch (val) {
35	case 0:
36	case 1:
37	case 2:
38	case 3:
39		pd = val + 1;
40		break;
41	case 4:
42		pd = 6;
43		break;
44	case 5:
45		pd = 8;
46		break;
47	case 6:
48		pd = 12;
49		break;
50	case 7:
51		pd = 16;
52		break;
53	default:
54		pd = -EINVAL;
55		break;
56	}
57
58	return pd;
59}
60EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
61
62/**
63 * rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
64 *
65 * @rate: base clock rate.
66 *
67 * Choose divider parameter that gives the highest possible DMIC frequency in
68 * 1MHz - 3MHz range.
69 */
70int rl6231_calc_dmic_clk(int rate)
71{
72	static const int div[] = {2, 3, 4, 6, 8, 12};
73	int i;
74
75	if (rate < 1000000 * div[0]) {
76		pr_warn("Base clock rate %d is too low\n", rate);
77		return -EINVAL;
78	}
79
80	for (i = 0; i < ARRAY_SIZE(div); i++) {
81		if ((div[i] % 3) == 0)
82			continue;
83		/* find divider that gives DMIC frequency below 1.536MHz */
84		if (1536000 * div[i] >= rate)
85			return i;
86	}
87
88	pr_warn("Base clock rate %d is too high\n", rate);
89	return -EINVAL;
90}
91EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
92
93struct pll_calc_map {
94	unsigned int pll_in;
95	unsigned int pll_out;
96	int k;
97	int n;
98	int m;
99	bool m_bp;
100	bool k_bp;
101};
102
103static const struct pll_calc_map pll_preset_table[] = {
104	{19200000,  4096000,  23, 14, 1, false, false},
105	{19200000,  24576000,  3, 30, 3, false, false},
106	{48000000,  3840000,  23,  2, 0, false, false},
107	{3840000,   24576000,  3, 30, 0, true, false},
108	{3840000,   22579200,  3,  5, 0, true, false},
109};
110
111static unsigned int find_best_div(unsigned int in,
112	unsigned int max, unsigned int div)
113{
114	unsigned int d;
115
116	if (in <= max)
117		return 1;
118
119	d = in / max;
120	if (in % max)
121		d++;
122
123	while (div % d != 0)
124		d++;
125
126
127	return d;
128}
129
130/**
131 * rl6231_pll_calc - Calcualte PLL M/N/K code.
132 * @freq_in: external clock provided to codec.
133 * @freq_out: target clock which codec works on.
134 * @pll_code: Pointer to structure with M, N, K, m_bypass and k_bypass flag.
135 *
136 * Calcualte M/N/K code to configure PLL for codec.
137 *
138 * Returns 0 for success or negative error code.
139 */
140int rl6231_pll_calc(const unsigned int freq_in,
141	const unsigned int freq_out, struct rl6231_pll_code *pll_code)
142{
143	int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
144	int i, k, n_t;
145	int k_t, min_k, max_k, n = 0, m = 0, m_t = 0;
146	unsigned int red, pll_out, in_t, out_t, div, div_t;
147	unsigned int red_t = abs(freq_out - freq_in);
148	unsigned int f_in, f_out, f_max;
149	bool m_bypass = false, k_bypass = false;
150
151	if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
152		return -EINVAL;
153
154	for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
155		if (freq_in == pll_preset_table[i].pll_in &&
156			freq_out == pll_preset_table[i].pll_out) {
157			k = pll_preset_table[i].k;
158			m = pll_preset_table[i].m;
159			n = pll_preset_table[i].n;
160			m_bypass = pll_preset_table[i].m_bp;
161			k_bypass = pll_preset_table[i].k_bp;
162			pr_debug("Use preset PLL parameter table\n");
163			goto code_find;
164		}
165	}
166
167	min_k = 80000000 / freq_out - 2;
168	max_k = 150000000 / freq_out - 2;
169	if (max_k > RL6231_PLL_K_MAX)
170		max_k = RL6231_PLL_K_MAX;
171	if (min_k > RL6231_PLL_K_MAX)
172		min_k = max_k = RL6231_PLL_K_MAX;
173	div_t = gcd(freq_in, freq_out);
174	f_max = 0xffffffff / RL6231_PLL_N_MAX;
175	div = find_best_div(freq_in, f_max, div_t);
176	f_in = freq_in / div;
177	f_out = freq_out / div;
178	k = min_k;
179	if (min_k < -1)
180		min_k = -1;
181	for (k_t = min_k; k_t <= max_k; k_t++) {
182		for (n_t = 0; n_t <= max_n; n_t++) {
183			in_t = f_in * (n_t + 2);
184			pll_out = f_out * (k_t + 2);
185			if (in_t == pll_out) {
186				m_bypass = true;
187				n = n_t;
188				k = k_t;
189				goto code_find;
190			}
191			out_t = in_t / (k_t + 2);
192			red = abs(f_out - out_t);
193			if (red < red_t) {
194				m_bypass = true;
195				n = n_t;
196				m = 0;
197				k = k_t;
198				if (red == 0)
199					goto code_find;
200				red_t = red;
201			}
202			for (m_t = 0; m_t <= max_m; m_t++) {
203				out_t = in_t / ((m_t + 2) * (k_t + 2));
204				red = abs(f_out - out_t);
205				if (red < red_t) {
206					m_bypass = false;
207					n = n_t;
208					m = m_t;
209					k = k_t;
210					if (red == 0)
211						goto code_find;
212					red_t = red;
213				}
214			}
215		}
216	}
217	pr_debug("Only get approximation about PLL\n");
218
219code_find:
220	if (k == -1) {
221		k_bypass = true;
222		k = 0;
223	}
224
225	pll_code->m_bp = m_bypass;
226	pll_code->k_bp = k_bypass;
227	pll_code->m_code = m;
228	pll_code->n_code = n;
229	pll_code->k_code = k;
230	return 0;
231}
232EXPORT_SYMBOL_GPL(rl6231_pll_calc);
233
234int rl6231_get_clk_info(int sclk, int rate)
235{
236	int i;
237	static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
238
239	if (sclk <= 0 || rate <= 0)
240		return -EINVAL;
241
242	rate = rate << 8;
243	for (i = 0; i < ARRAY_SIZE(pd); i++)
244		if (sclk == rate * pd[i])
245			return i;
246
247	return -EINVAL;
248}
249EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
250
251MODULE_DESCRIPTION("RL6231 class device shared support");
252MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
253MODULE_LICENSE("GPL v2");
254