1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Rockchip RK3308 internal audio codec driver 4 * 5 * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. 6 * Copyright (c) 2024, Vivax-Metrotech Ltd 7 */ 8 9#include <linux/clk.h> 10#include <linux/device.h> 11#include <linux/delay.h> 12#include <linux/init.h> 13#include <linux/io.h> 14#include <linux/mfd/syscon.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/regmap.h> 19#include <linux/reset.h> 20#include <linux/util_macros.h> 21#include <sound/core.h> 22#include <sound/pcm.h> 23#include <sound/pcm_params.h> 24#include <sound/soc.h> 25#include <sound/tlv.h> 26 27#include "rk3308_codec.h" 28 29#define ADC_LR_GROUP_MAX 4 30 31#define GRF_CHIP_ID 0x800 32 33enum { 34 ACODEC_VERSION_A = 'A', 35 ACODEC_VERSION_B, 36 ACODEC_VERSION_C, 37}; 38 39struct rk3308_codec_priv { 40 const struct device *dev; 41 struct regmap *regmap; 42 struct regmap *grf; 43 struct reset_control *reset; 44 struct clk *hclk; 45 struct clk *mclk_rx; 46 struct clk *mclk_tx; 47 struct snd_soc_component *component; 48 unsigned char codec_ver; 49}; 50 51static struct clk_bulk_data rk3308_codec_clocks[] = { 52 { .id = "hclk" }, 53 { .id = "mclk_rx" }, 54 { .id = "mclk_tx" }, 55}; 56 57static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv, -1800, 150, 0); 58static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv, -3900, 150, 0); 59static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv, -600, 600, 0); 60 61static const DECLARE_TLV_DB_RANGE(rk3308_codec_dac_lineout_gain_tlv, 62 0, 0, TLV_DB_SCALE_ITEM(-600, 0, 0), 63 1, 1, TLV_DB_SCALE_ITEM(-300, 0, 0), 64 2, 2, TLV_DB_SCALE_ITEM(-150, 0, 0), 65 3, 3, TLV_DB_SCALE_ITEM(0, 0, 0), 66); 67 68static const char * const rk3308_codec_hpf_cutoff_text[] = { 69 "20 Hz", "245 Hz", "612 Hz" 70}; 71 72static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum12, RK3308_ADC_DIG_CON04(0), 0, 73 rk3308_codec_hpf_cutoff_text); 74static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum34, RK3308_ADC_DIG_CON04(1), 0, 75 rk3308_codec_hpf_cutoff_text); 76static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum56, RK3308_ADC_DIG_CON04(2), 0, 77 rk3308_codec_hpf_cutoff_text); 78static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum78, RK3308_ADC_DIG_CON04(3), 0, 79 rk3308_codec_hpf_cutoff_text); 80 81static const struct snd_kcontrol_new rk3308_codec_controls[] = { 82 /* Despite the register names, these set the gain when AGC is OFF */ 83 SOC_SINGLE_RANGE_TLV("MIC1 Capture Volume", 84 RK3308_ADC_ANA_CON03(0), 85 RK3308_ADC_CH1_ALC_GAIN_SFT, 86 RK3308_ADC_CH1_ALC_GAIN_MIN, 87 RK3308_ADC_CH1_ALC_GAIN_MAX, 88 0, rk3308_codec_adc_alc_gain_tlv), 89 SOC_SINGLE_RANGE_TLV("MIC2 Capture Volume", 90 RK3308_ADC_ANA_CON04(0), 91 RK3308_ADC_CH2_ALC_GAIN_SFT, 92 RK3308_ADC_CH2_ALC_GAIN_MIN, 93 RK3308_ADC_CH2_ALC_GAIN_MAX, 94 0, rk3308_codec_adc_alc_gain_tlv), 95 SOC_SINGLE_RANGE_TLV("MIC3 Capture Volume", 96 RK3308_ADC_ANA_CON03(1), 97 RK3308_ADC_CH1_ALC_GAIN_SFT, 98 RK3308_ADC_CH1_ALC_GAIN_MIN, 99 RK3308_ADC_CH1_ALC_GAIN_MAX, 100 0, rk3308_codec_adc_alc_gain_tlv), 101 SOC_SINGLE_RANGE_TLV("MIC4 Capture Volume", 102 RK3308_ADC_ANA_CON04(1), 103 RK3308_ADC_CH2_ALC_GAIN_SFT, 104 RK3308_ADC_CH2_ALC_GAIN_MIN, 105 RK3308_ADC_CH2_ALC_GAIN_MAX, 106 0, rk3308_codec_adc_alc_gain_tlv), 107 SOC_SINGLE_RANGE_TLV("MIC5 Capture Volume", 108 RK3308_ADC_ANA_CON03(2), 109 RK3308_ADC_CH1_ALC_GAIN_SFT, 110 RK3308_ADC_CH1_ALC_GAIN_MIN, 111 RK3308_ADC_CH1_ALC_GAIN_MAX, 112 0, rk3308_codec_adc_alc_gain_tlv), 113 SOC_SINGLE_RANGE_TLV("MIC6 Capture Volume", 114 RK3308_ADC_ANA_CON04(2), 115 RK3308_ADC_CH2_ALC_GAIN_SFT, 116 RK3308_ADC_CH2_ALC_GAIN_MIN, 117 RK3308_ADC_CH2_ALC_GAIN_MAX, 118 0, rk3308_codec_adc_alc_gain_tlv), 119 SOC_SINGLE_RANGE_TLV("MIC7 Capture Volume", 120 RK3308_ADC_ANA_CON03(3), 121 RK3308_ADC_CH1_ALC_GAIN_SFT, 122 RK3308_ADC_CH1_ALC_GAIN_MIN, 123 RK3308_ADC_CH1_ALC_GAIN_MAX, 124 0, rk3308_codec_adc_alc_gain_tlv), 125 SOC_SINGLE_RANGE_TLV("MIC8 Capture Volume", 126 RK3308_ADC_ANA_CON04(3), 127 RK3308_ADC_CH2_ALC_GAIN_SFT, 128 RK3308_ADC_CH2_ALC_GAIN_MIN, 129 RK3308_ADC_CH2_ALC_GAIN_MAX, 130 0, rk3308_codec_adc_alc_gain_tlv), 131 132 SOC_SINGLE("MIC1 Capture Switch", RK3308_ADC_ANA_CON00(0), 3, 1, 0), 133 SOC_SINGLE("MIC2 Capture Switch", RK3308_ADC_ANA_CON00(0), 7, 1, 0), 134 SOC_SINGLE("MIC3 Capture Switch", RK3308_ADC_ANA_CON00(1), 3, 1, 0), 135 SOC_SINGLE("MIC4 Capture Switch", RK3308_ADC_ANA_CON00(1), 7, 1, 0), 136 SOC_SINGLE("MIC5 Capture Switch", RK3308_ADC_ANA_CON00(2), 3, 1, 0), 137 SOC_SINGLE("MIC6 Capture Switch", RK3308_ADC_ANA_CON00(2), 7, 1, 0), 138 SOC_SINGLE("MIC7 Capture Switch", RK3308_ADC_ANA_CON00(3), 3, 1, 0), 139 SOC_SINGLE("MIC8 Capture Switch", RK3308_ADC_ANA_CON00(3), 7, 1, 0), 140 141 SOC_SINGLE("MIC12 HPF Capture Switch", RK3308_ADC_DIG_CON04(0), 2, 1, 1), 142 SOC_SINGLE("MIC34 HPF Capture Switch", RK3308_ADC_DIG_CON04(1), 2, 1, 1), 143 SOC_SINGLE("MIC56 HPF Capture Switch", RK3308_ADC_DIG_CON04(2), 2, 1, 1), 144 SOC_SINGLE("MIC78 HPF Capture Switch", RK3308_ADC_DIG_CON04(3), 2, 1, 1), 145 146 SOC_ENUM("MIC12 HPF Cutoff", rk3308_codec_hpf_cutoff_enum12), 147 SOC_ENUM("MIC34 HPF Cutoff", rk3308_codec_hpf_cutoff_enum34), 148 SOC_ENUM("MIC56 HPF Cutoff", rk3308_codec_hpf_cutoff_enum56), 149 SOC_ENUM("MIC78 HPF Cutoff", rk3308_codec_hpf_cutoff_enum78), 150 151 SOC_DOUBLE_TLV("Line Out Playback Volume", 152 RK3308_DAC_ANA_CON04, 153 RK3308_DAC_L_LINEOUT_GAIN_SFT, 154 RK3308_DAC_R_LINEOUT_GAIN_SFT, 155 RK3308_DAC_x_LINEOUT_GAIN_MAX, 156 0, rk3308_codec_dac_lineout_gain_tlv), 157 SOC_DOUBLE("Line Out Playback Switch", 158 RK3308_DAC_ANA_CON04, 159 RK3308_DAC_L_LINEOUT_MUTE_SFT, 160 RK3308_DAC_R_LINEOUT_MUTE_SFT, 1, 0), 161 SOC_DOUBLE_R_TLV("Headphone Playback Volume", 162 RK3308_DAC_ANA_CON05, 163 RK3308_DAC_ANA_CON06, 164 RK3308_DAC_x_HPOUT_GAIN_SFT, 165 RK3308_DAC_x_HPOUT_GAIN_MAX, 166 0, rk3308_codec_dac_hpout_gain_tlv), 167 SOC_DOUBLE("Headphone Playback Switch", 168 RK3308_DAC_ANA_CON03, 169 RK3308_DAC_L_HPOUT_MUTE_SFT, 170 RK3308_DAC_R_HPOUT_MUTE_SFT, 1, 0), 171 SOC_DOUBLE_RANGE_TLV("DAC HPMIX Playback Volume", 172 RK3308_DAC_ANA_CON12, 173 RK3308_DAC_L_HPMIX_GAIN_SFT, 174 RK3308_DAC_R_HPMIX_GAIN_SFT, 175 1, 2, 0, rk3308_codec_dac_hpmix_gain_tlv), 176}; 177 178static int rk3308_codec_pop_sound_set(struct snd_soc_dapm_widget *w, 179 struct snd_kcontrol *kcontrol, 180 int event) 181{ 182 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 183 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); 184 unsigned int val = (event == SND_SOC_DAPM_POST_PMU) ? 185 RK3308_DAC_HPOUT_POP_SOUND_x_WORK : 186 RK3308_DAC_HPOUT_POP_SOUND_x_INIT; 187 unsigned int mask = RK3308_DAC_HPOUT_POP_SOUND_x_MSK; 188 189 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, 190 mask << w->shift, val << w->shift); 191 192 return 0; 193} 194 195static const struct snd_soc_dapm_widget rk3308_codec_dapm_widgets[] = { 196 SND_SOC_DAPM_INPUT("MIC1"), 197 SND_SOC_DAPM_INPUT("MIC2"), 198 SND_SOC_DAPM_INPUT("MIC3"), 199 SND_SOC_DAPM_INPUT("MIC4"), 200 SND_SOC_DAPM_INPUT("MIC5"), 201 SND_SOC_DAPM_INPUT("MIC6"), 202 SND_SOC_DAPM_INPUT("MIC7"), 203 SND_SOC_DAPM_INPUT("MIC8"), 204 205 SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN12", RK3308_ADC_ANA_CON06(0), 0, 0, NULL, 0), 206 SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN34", RK3308_ADC_ANA_CON06(1), 0, 0, NULL, 0), 207 SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN56", RK3308_ADC_ANA_CON06(2), 0, 0, NULL, 0), 208 SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN78", RK3308_ADC_ANA_CON06(3), 0, 0, NULL, 0), 209 210 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC1_EN", RK3308_ADC_ANA_CON00(0), 1, 1, 1, 0), 211 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC2_EN", RK3308_ADC_ANA_CON00(0), 5, 1, 1, 0), 212 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC3_EN", RK3308_ADC_ANA_CON00(1), 1, 1, 1, 0), 213 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC4_EN", RK3308_ADC_ANA_CON00(1), 5, 1, 1, 0), 214 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC5_EN", RK3308_ADC_ANA_CON00(2), 1, 1, 1, 0), 215 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC6_EN", RK3308_ADC_ANA_CON00(2), 5, 1, 1, 0), 216 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC7_EN", RK3308_ADC_ANA_CON00(3), 1, 1, 1, 0), 217 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC8_EN", RK3308_ADC_ANA_CON00(3), 5, 1, 1, 0), 218 219 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC1_WORK", RK3308_ADC_ANA_CON00(0), 2, 1, 1, 0), 220 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC2_WORK", RK3308_ADC_ANA_CON00(0), 6, 1, 1, 0), 221 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC3_WORK", RK3308_ADC_ANA_CON00(1), 2, 1, 1, 0), 222 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC4_WORK", RK3308_ADC_ANA_CON00(1), 6, 1, 1, 0), 223 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC5_WORK", RK3308_ADC_ANA_CON00(2), 2, 1, 1, 0), 224 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC6_WORK", RK3308_ADC_ANA_CON00(2), 6, 1, 1, 0), 225 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC7_WORK", RK3308_ADC_ANA_CON00(3), 2, 1, 1, 0), 226 SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC8_WORK", RK3308_ADC_ANA_CON00(3), 6, 1, 1, 0), 227 228 /* 229 * In theory MIC1 and MIC2 can switch to LINE IN, but this is not 230 * supported so all we can do is enabling the MIC input. 231 */ 232 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "CH1_IN_SEL", RK3308_ADC_ANA_CON07(0), 4, 1, 1, 0), 233 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "CH2_IN_SEL", RK3308_ADC_ANA_CON07(0), 6, 1, 1, 0), 234 235 SND_SOC_DAPM_SUPPLY("ADC1_BUF_REF_EN", RK3308_ADC_ANA_CON00(0), 0, 0, NULL, 0), 236 SND_SOC_DAPM_SUPPLY("ADC2_BUF_REF_EN", RK3308_ADC_ANA_CON00(0), 4, 0, NULL, 0), 237 SND_SOC_DAPM_SUPPLY("ADC3_BUF_REF_EN", RK3308_ADC_ANA_CON00(1), 0, 0, NULL, 0), 238 SND_SOC_DAPM_SUPPLY("ADC4_BUF_REF_EN", RK3308_ADC_ANA_CON00(1), 4, 0, NULL, 0), 239 SND_SOC_DAPM_SUPPLY("ADC5_BUF_REF_EN", RK3308_ADC_ANA_CON00(2), 0, 0, NULL, 0), 240 SND_SOC_DAPM_SUPPLY("ADC6_BUF_REF_EN", RK3308_ADC_ANA_CON00(2), 4, 0, NULL, 0), 241 SND_SOC_DAPM_SUPPLY("ADC7_BUF_REF_EN", RK3308_ADC_ANA_CON00(3), 0, 0, NULL, 0), 242 SND_SOC_DAPM_SUPPLY("ADC8_BUF_REF_EN", RK3308_ADC_ANA_CON00(3), 4, 0, NULL, 0), 243 244 SND_SOC_DAPM_SUPPLY("ADC_MCLK_GATE", RK3308_GLB_CON, 5, 1, NULL, 0), 245 246 SND_SOC_DAPM_SUPPLY("ADC1_CLK_EN", RK3308_ADC_ANA_CON05(0), 0, 0, NULL, 0), 247 SND_SOC_DAPM_SUPPLY("ADC2_CLK_EN", RK3308_ADC_ANA_CON05(0), 4, 0, NULL, 0), 248 SND_SOC_DAPM_SUPPLY("ADC3_CLK_EN", RK3308_ADC_ANA_CON05(1), 0, 0, NULL, 0), 249 SND_SOC_DAPM_SUPPLY("ADC4_CLK_EN", RK3308_ADC_ANA_CON05(1), 4, 0, NULL, 0), 250 SND_SOC_DAPM_SUPPLY("ADC5_CLK_EN", RK3308_ADC_ANA_CON05(2), 0, 0, NULL, 0), 251 SND_SOC_DAPM_SUPPLY("ADC6_CLK_EN", RK3308_ADC_ANA_CON05(2), 4, 0, NULL, 0), 252 SND_SOC_DAPM_SUPPLY("ADC7_CLK_EN", RK3308_ADC_ANA_CON05(3), 0, 0, NULL, 0), 253 SND_SOC_DAPM_SUPPLY("ADC8_CLK_EN", RK3308_ADC_ANA_CON05(3), 4, 0, NULL, 0), 254 255 /* The "ALC" name from the TRM is misleading, these are needed even without ALC/AGC */ 256 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC1_EN", RK3308_ADC_ANA_CON02(0), 0, 1, 1, 0), 257 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC2_EN", RK3308_ADC_ANA_CON02(0), 4, 1, 1, 0), 258 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC3_EN", RK3308_ADC_ANA_CON02(1), 0, 1, 1, 0), 259 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC4_EN", RK3308_ADC_ANA_CON02(1), 4, 1, 1, 0), 260 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC5_EN", RK3308_ADC_ANA_CON02(2), 0, 1, 1, 0), 261 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC6_EN", RK3308_ADC_ANA_CON02(2), 4, 1, 1, 0), 262 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC7_EN", RK3308_ADC_ANA_CON02(3), 0, 1, 1, 0), 263 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC8_EN", RK3308_ADC_ANA_CON02(3), 4, 1, 1, 0), 264 265 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC1_EN", RK3308_ADC_ANA_CON05(0), 1, 1, 1, 0), 266 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC2_EN", RK3308_ADC_ANA_CON05(0), 5, 1, 1, 0), 267 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC3_EN", RK3308_ADC_ANA_CON05(1), 1, 1, 1, 0), 268 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC4_EN", RK3308_ADC_ANA_CON05(1), 5, 1, 1, 0), 269 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC5_EN", RK3308_ADC_ANA_CON05(2), 1, 1, 1, 0), 270 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC6_EN", RK3308_ADC_ANA_CON05(2), 5, 1, 1, 0), 271 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC7_EN", RK3308_ADC_ANA_CON05(3), 1, 1, 1, 0), 272 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC8_EN", RK3308_ADC_ANA_CON05(3), 5, 1, 1, 0), 273 274 SND_SOC_DAPM_ADC("ADC1_WORK", "Capture", RK3308_ADC_ANA_CON05(0), 2, 0), 275 SND_SOC_DAPM_ADC("ADC2_WORK", "Capture", RK3308_ADC_ANA_CON05(0), 6, 0), 276 SND_SOC_DAPM_ADC("ADC3_WORK", "Capture", RK3308_ADC_ANA_CON05(1), 2, 0), 277 SND_SOC_DAPM_ADC("ADC4_WORK", "Capture", RK3308_ADC_ANA_CON05(1), 6, 0), 278 SND_SOC_DAPM_ADC("ADC5_WORK", "Capture", RK3308_ADC_ANA_CON05(2), 2, 0), 279 SND_SOC_DAPM_ADC("ADC6_WORK", "Capture", RK3308_ADC_ANA_CON05(2), 6, 0), 280 SND_SOC_DAPM_ADC("ADC7_WORK", "Capture", RK3308_ADC_ANA_CON05(3), 2, 0), 281 SND_SOC_DAPM_ADC("ADC8_WORK", "Capture", RK3308_ADC_ANA_CON05(3), 6, 0), 282 283 /* The "ALC" name from the TRM is misleading, these are needed even without ALC/AGC */ 284 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC1_WORK", RK3308_ADC_ANA_CON02(0), 1, 1, 1, 0), 285 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC2_WORK", RK3308_ADC_ANA_CON02(0), 5, 1, 1, 0), 286 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC3_WORK", RK3308_ADC_ANA_CON02(1), 1, 1, 1, 0), 287 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC4_WORK", RK3308_ADC_ANA_CON02(1), 5, 1, 1, 0), 288 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC5_WORK", RK3308_ADC_ANA_CON02(2), 1, 1, 1, 0), 289 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC6_WORK", RK3308_ADC_ANA_CON02(2), 5, 1, 1, 0), 290 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC7_WORK", RK3308_ADC_ANA_CON02(3), 1, 1, 1, 0), 291 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC8_WORK", RK3308_ADC_ANA_CON02(3), 5, 1, 1, 0), 292 293 SND_SOC_DAPM_SUPPLY("MICBIAS Current", RK3308_ADC_ANA_CON08(0), 4, 0, NULL, 0), 294 SND_SOC_DAPM_SUPPLY("MICBIAS1", RK3308_ADC_ANA_CON07(1), 3, 0, NULL, 0), 295 SND_SOC_DAPM_SUPPLY("MICBIAS2", RK3308_ADC_ANA_CON07(2), 3, 0, NULL, 0), 296 297 SND_SOC_DAPM_OUT_DRV("DAC_L_HPMIX_EN", RK3308_DAC_ANA_CON13, 0, 0, NULL, 0), 298 SND_SOC_DAPM_OUT_DRV("DAC_R_HPMIX_EN", RK3308_DAC_ANA_CON13, 4, 0, NULL, 0), 299 SND_SOC_DAPM_OUT_DRV("DAC_L_HPMIX_WORK", RK3308_DAC_ANA_CON13, 1, 0, NULL, 0), 300 SND_SOC_DAPM_OUT_DRV("DAC_R_HPMIX_WORK", RK3308_DAC_ANA_CON13, 5, 0, NULL, 0), 301 /* HPMIX is not actually acting as a mixer as the only supported input is I2S */ 302 SND_SOC_DAPM_OUT_DRV("DAC_L_HPMIX_SEL", RK3308_DAC_ANA_CON12, 2, 0, NULL, 0), 303 SND_SOC_DAPM_OUT_DRV("DAC_R_HPMIX_SEL", RK3308_DAC_ANA_CON12, 6, 0, NULL, 0), 304 SND_SOC_DAPM_MIXER("DAC HPMIX Left", RK3308_DAC_ANA_CON13, 2, 0, NULL, 0), 305 SND_SOC_DAPM_MIXER("DAC HPMIX Right", RK3308_DAC_ANA_CON13, 6, 0, NULL, 0), 306 307 SND_SOC_DAPM_SUPPLY("DAC_MCLK_GATE", RK3308_GLB_CON, 4, 1, NULL, 0), 308 309 SND_SOC_DAPM_SUPPLY("DAC_CURRENT_EN", RK3308_DAC_ANA_CON00, 0, 0, NULL, 0), 310 SND_SOC_DAPM_SUPPLY("DAC_L_REF_EN", RK3308_DAC_ANA_CON02, 0, 0, NULL, 0), 311 SND_SOC_DAPM_SUPPLY("DAC_R_REF_EN", RK3308_DAC_ANA_CON02, 4, 0, NULL, 0), 312 SND_SOC_DAPM_SUPPLY("DAC_L_CLK_EN", RK3308_DAC_ANA_CON02, 1, 0, NULL, 0), 313 SND_SOC_DAPM_SUPPLY("DAC_R_CLK_EN", RK3308_DAC_ANA_CON02, 5, 0, NULL, 0), 314 SND_SOC_DAPM_DAC("DAC_L_DAC_WORK", NULL, RK3308_DAC_ANA_CON02, 3, 0), 315 SND_SOC_DAPM_DAC("DAC_R_DAC_WORK", NULL, RK3308_DAC_ANA_CON02, 7, 0), 316 317 SND_SOC_DAPM_SUPPLY("DAC_BUF_REF_L", RK3308_DAC_ANA_CON01, 2, 0, NULL, 0), 318 SND_SOC_DAPM_SUPPLY("DAC_BUF_REF_R", RK3308_DAC_ANA_CON01, 6, 0, NULL, 0), 319 SND_SOC_DAPM_OUT_DRV_E("HPOUT_POP_SOUND_L", SND_SOC_NOPM, 0, 0, NULL, 0, 320 rk3308_codec_pop_sound_set, 321 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 322 SND_SOC_DAPM_OUT_DRV_E("HPOUT_POP_SOUND_R", SND_SOC_NOPM, 4, 0, NULL, 0, 323 rk3308_codec_pop_sound_set, 324 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 325 SND_SOC_DAPM_OUT_DRV("L_HPOUT_EN", RK3308_DAC_ANA_CON03, 1, 0, NULL, 0), 326 SND_SOC_DAPM_OUT_DRV("R_HPOUT_EN", RK3308_DAC_ANA_CON03, 5, 0, NULL, 0), 327 SND_SOC_DAPM_OUT_DRV("L_HPOUT_WORK", RK3308_DAC_ANA_CON03, 2, 0, NULL, 0), 328 SND_SOC_DAPM_OUT_DRV("R_HPOUT_WORK", RK3308_DAC_ANA_CON03, 6, 0, NULL, 0), 329 SND_SOC_DAPM_OUTPUT("HPOUT_L"), 330 SND_SOC_DAPM_OUTPUT("HPOUT_R"), 331 332 SND_SOC_DAPM_OUT_DRV("L_LINEOUT_EN", RK3308_DAC_ANA_CON04, 0, 0, NULL, 0), 333 SND_SOC_DAPM_OUT_DRV("R_LINEOUT_EN", RK3308_DAC_ANA_CON04, 4, 0, NULL, 0), 334 SND_SOC_DAPM_OUTPUT("LINEOUT_L"), 335 SND_SOC_DAPM_OUTPUT("LINEOUT_R"), 336}; 337 338static const struct snd_soc_dapm_route rk3308_codec_dapm_routes[] = { 339 { "MICBIAS1", NULL, "MICBIAS Current" }, 340 { "MICBIAS2", NULL, "MICBIAS Current" }, 341 342 { "MIC1_EN", NULL, "MIC1" }, 343 { "MIC2_EN", NULL, "MIC2" }, 344 { "MIC3_EN", NULL, "MIC3" }, 345 { "MIC4_EN", NULL, "MIC4" }, 346 { "MIC5_EN", NULL, "MIC5" }, 347 { "MIC6_EN", NULL, "MIC6" }, 348 { "MIC7_EN", NULL, "MIC7" }, 349 { "MIC8_EN", NULL, "MIC8" }, 350 351 { "MIC1_WORK", NULL, "MIC1_EN" }, 352 { "MIC2_WORK", NULL, "MIC2_EN" }, 353 { "MIC3_WORK", NULL, "MIC3_EN" }, 354 { "MIC4_WORK", NULL, "MIC4_EN" }, 355 { "MIC5_WORK", NULL, "MIC5_EN" }, 356 { "MIC6_WORK", NULL, "MIC6_EN" }, 357 { "MIC7_WORK", NULL, "MIC7_EN" }, 358 { "MIC8_WORK", NULL, "MIC8_EN" }, 359 360 { "CH1_IN_SEL", NULL, "MIC1_WORK" }, 361 { "CH2_IN_SEL", NULL, "MIC2_WORK" }, 362 363 { "ALC1_EN", NULL, "CH1_IN_SEL" }, 364 { "ALC2_EN", NULL, "CH2_IN_SEL" }, 365 { "ALC3_EN", NULL, "MIC3_WORK" }, 366 { "ALC4_EN", NULL, "MIC4_WORK" }, 367 { "ALC5_EN", NULL, "MIC5_WORK" }, 368 { "ALC6_EN", NULL, "MIC6_WORK" }, 369 { "ALC7_EN", NULL, "MIC7_WORK" }, 370 { "ALC8_EN", NULL, "MIC8_WORK" }, 371 372 { "ADC1_EN", NULL, "ALC1_EN" }, 373 { "ADC2_EN", NULL, "ALC2_EN" }, 374 { "ADC3_EN", NULL, "ALC3_EN" }, 375 { "ADC4_EN", NULL, "ALC4_EN" }, 376 { "ADC5_EN", NULL, "ALC5_EN" }, 377 { "ADC6_EN", NULL, "ALC6_EN" }, 378 { "ADC7_EN", NULL, "ALC7_EN" }, 379 { "ADC8_EN", NULL, "ALC8_EN" }, 380 381 { "ADC1_WORK", NULL, "ADC1_EN" }, 382 { "ADC2_WORK", NULL, "ADC2_EN" }, 383 { "ADC3_WORK", NULL, "ADC3_EN" }, 384 { "ADC4_WORK", NULL, "ADC4_EN" }, 385 { "ADC5_WORK", NULL, "ADC5_EN" }, 386 { "ADC6_WORK", NULL, "ADC6_EN" }, 387 { "ADC7_WORK", NULL, "ADC7_EN" }, 388 { "ADC8_WORK", NULL, "ADC8_EN" }, 389 390 { "ADC1_BUF_REF_EN", NULL, "ADC_CURRENT_EN12" }, 391 { "ADC2_BUF_REF_EN", NULL, "ADC_CURRENT_EN12" }, 392 { "ADC3_BUF_REF_EN", NULL, "ADC_CURRENT_EN34" }, 393 { "ADC4_BUF_REF_EN", NULL, "ADC_CURRENT_EN34" }, 394 { "ADC5_BUF_REF_EN", NULL, "ADC_CURRENT_EN56" }, 395 { "ADC6_BUF_REF_EN", NULL, "ADC_CURRENT_EN56" }, 396 { "ADC7_BUF_REF_EN", NULL, "ADC_CURRENT_EN78" }, 397 { "ADC8_BUF_REF_EN", NULL, "ADC_CURRENT_EN78" }, 398 399 { "ADC1_WORK", NULL, "ADC1_BUF_REF_EN" }, 400 { "ADC2_WORK", NULL, "ADC2_BUF_REF_EN" }, 401 { "ADC3_WORK", NULL, "ADC3_BUF_REF_EN" }, 402 { "ADC4_WORK", NULL, "ADC4_BUF_REF_EN" }, 403 { "ADC5_WORK", NULL, "ADC5_BUF_REF_EN" }, 404 { "ADC6_WORK", NULL, "ADC6_BUF_REF_EN" }, 405 { "ADC7_WORK", NULL, "ADC7_BUF_REF_EN" }, 406 { "ADC8_WORK", NULL, "ADC8_BUF_REF_EN" }, 407 408 { "ADC1_CLK_EN", NULL, "ADC_MCLK_GATE" }, 409 { "ADC2_CLK_EN", NULL, "ADC_MCLK_GATE" }, 410 { "ADC3_CLK_EN", NULL, "ADC_MCLK_GATE" }, 411 { "ADC4_CLK_EN", NULL, "ADC_MCLK_GATE" }, 412 { "ADC5_CLK_EN", NULL, "ADC_MCLK_GATE" }, 413 { "ADC6_CLK_EN", NULL, "ADC_MCLK_GATE" }, 414 { "ADC7_CLK_EN", NULL, "ADC_MCLK_GATE" }, 415 { "ADC8_CLK_EN", NULL, "ADC_MCLK_GATE" }, 416 417 { "ADC1_WORK", NULL, "ADC1_CLK_EN" }, 418 { "ADC2_WORK", NULL, "ADC2_CLK_EN" }, 419 { "ADC3_WORK", NULL, "ADC3_CLK_EN" }, 420 { "ADC4_WORK", NULL, "ADC4_CLK_EN" }, 421 { "ADC5_WORK", NULL, "ADC5_CLK_EN" }, 422 { "ADC6_WORK", NULL, "ADC6_CLK_EN" }, 423 { "ADC7_WORK", NULL, "ADC7_CLK_EN" }, 424 { "ADC8_WORK", NULL, "ADC8_CLK_EN" }, 425 426 { "ALC1_WORK", NULL, "ADC1_WORK" }, 427 { "ALC2_WORK", NULL, "ADC2_WORK" }, 428 { "ALC3_WORK", NULL, "ADC3_WORK" }, 429 { "ALC4_WORK", NULL, "ADC4_WORK" }, 430 { "ALC5_WORK", NULL, "ADC5_WORK" }, 431 { "ALC6_WORK", NULL, "ADC6_WORK" }, 432 { "ALC7_WORK", NULL, "ADC7_WORK" }, 433 { "ALC8_WORK", NULL, "ADC8_WORK" }, 434 435 { "HiFi Capture", NULL, "ALC1_WORK" }, 436 { "HiFi Capture", NULL, "ALC2_WORK" }, 437 { "HiFi Capture", NULL, "ALC3_WORK" }, 438 { "HiFi Capture", NULL, "ALC4_WORK" }, 439 { "HiFi Capture", NULL, "ALC5_WORK" }, 440 { "HiFi Capture", NULL, "ALC6_WORK" }, 441 { "HiFi Capture", NULL, "ALC7_WORK" }, 442 { "HiFi Capture", NULL, "ALC8_WORK" }, 443 444 { "DAC_L_HPMIX_EN", NULL, "HiFi Playback" }, 445 { "DAC_R_HPMIX_EN", NULL, "HiFi Playback" }, 446 { "DAC_L_HPMIX_WORK", NULL, "DAC_L_HPMIX_EN" }, 447 { "DAC_R_HPMIX_WORK", NULL, "DAC_R_HPMIX_EN" }, 448 { "DAC HPMIX Left", NULL, "DAC_L_HPMIX_WORK" }, 449 { "DAC HPMIX Right", NULL, "DAC_R_HPMIX_WORK" }, 450 451 { "DAC_L_DAC_WORK", NULL, "DAC HPMIX Left" }, 452 { "DAC_R_DAC_WORK", NULL, "DAC HPMIX Right" }, 453 454 { "DAC_L_REF_EN", NULL, "DAC_CURRENT_EN" }, 455 { "DAC_R_REF_EN", NULL, "DAC_CURRENT_EN" }, 456 { "DAC_L_CLK_EN", NULL, "DAC_L_REF_EN" }, 457 { "DAC_R_CLK_EN", NULL, "DAC_R_REF_EN" }, 458 { "DAC_L_CLK_EN", NULL, "DAC_MCLK_GATE" }, 459 { "DAC_R_CLK_EN", NULL, "DAC_MCLK_GATE" }, 460 { "DAC_L_DAC_WORK", NULL, "DAC_L_CLK_EN" }, 461 { "DAC_R_DAC_WORK", NULL, "DAC_R_CLK_EN" }, 462 { "DAC_L_HPMIX_SEL", NULL, "DAC_L_DAC_WORK" }, 463 { "DAC_R_HPMIX_SEL", NULL, "DAC_R_DAC_WORK" }, 464 465 { "HPOUT_L", NULL, "DAC_BUF_REF_L" }, 466 { "HPOUT_R", NULL, "DAC_BUF_REF_R" }, 467 { "L_HPOUT_EN", NULL, "DAC_L_HPMIX_SEL" }, 468 { "R_HPOUT_EN", NULL, "DAC_R_HPMIX_SEL" }, 469 { "L_HPOUT_WORK", NULL, "L_HPOUT_EN" }, 470 { "R_HPOUT_WORK", NULL, "R_HPOUT_EN" }, 471 { "HPOUT_POP_SOUND_L", NULL, "L_HPOUT_WORK" }, 472 { "HPOUT_POP_SOUND_R", NULL, "R_HPOUT_WORK" }, 473 { "HPOUT_L", NULL, "HPOUT_POP_SOUND_L" }, 474 { "HPOUT_R", NULL, "HPOUT_POP_SOUND_R" }, 475 476 { "L_LINEOUT_EN", NULL, "DAC_L_HPMIX_SEL" }, 477 { "R_LINEOUT_EN", NULL, "DAC_R_HPMIX_SEL" }, 478 { "LINEOUT_L", NULL, "L_LINEOUT_EN" }, 479 { "LINEOUT_R", NULL, "R_LINEOUT_EN" }, 480}; 481 482static int rk3308_codec_set_dai_fmt(struct snd_soc_dai *codec_dai, 483 unsigned int fmt) 484{ 485 struct snd_soc_component *component = codec_dai->component; 486 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); 487 const unsigned int inv_bits = fmt & SND_SOC_DAIFMT_INV_MASK; 488 const bool inv_bitclk = 489 (inv_bits & SND_SOC_DAIFMT_IB_IF) || 490 (inv_bits & SND_SOC_DAIFMT_IB_NF); 491 const bool inv_frmclk = 492 (inv_bits & SND_SOC_DAIFMT_IB_IF) || 493 (inv_bits & SND_SOC_DAIFMT_NB_IF); 494 const unsigned int dac_master_bits = rk3308->codec_ver < ACODEC_VERSION_C ? 495 RK3308_DAC_IO_MODE_MASTER | RK3308_DAC_MODE_MASTER : 496 RK3308BS_DAC_IO_MODE_MASTER | RK3308BS_DAC_MODE_MASTER; 497 unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; 498 bool is_master = false; 499 int grp; 500 501 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 502 case SND_SOC_DAIFMT_CBC_CFC: 503 break; 504 case SND_SOC_DAIFMT_CBP_CFP: 505 adc_aif2 |= RK3308_ADC_IO_MODE_MASTER; 506 adc_aif2 |= RK3308_ADC_MODE_MASTER; 507 dac_aif2 |= dac_master_bits; 508 is_master = true; 509 break; 510 default: 511 return -EINVAL; 512 } 513 514 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 515 case SND_SOC_DAIFMT_DSP_A: 516 adc_aif1 |= RK3308_ADC_I2S_MODE_PCM; 517 dac_aif1 |= RK3308_DAC_I2S_MODE_PCM; 518 break; 519 case SND_SOC_DAIFMT_I2S: 520 adc_aif1 |= RK3308_ADC_I2S_MODE_I2S; 521 dac_aif1 |= RK3308_DAC_I2S_MODE_I2S; 522 break; 523 case SND_SOC_DAIFMT_RIGHT_J: 524 adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; 525 dac_aif1 |= RK3308_DAC_I2S_MODE_RJ; 526 break; 527 case SND_SOC_DAIFMT_LEFT_J: 528 adc_aif1 |= RK3308_ADC_I2S_MODE_LJ; 529 dac_aif1 |= RK3308_DAC_I2S_MODE_LJ; 530 break; 531 default: 532 return -EINVAL; 533 } 534 535 if (inv_bitclk) { 536 adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; 537 dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; 538 } 539 540 if (inv_frmclk) { 541 adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; 542 dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; 543 } 544 545 /* 546 * Hold ADC Digital registers start at master mode 547 * 548 * There are 8 ADCs which use the same internal SCLK and LRCK for 549 * master mode. We need to make sure that they are in effect at the 550 * same time, otherwise they will cause abnormal clocks. 551 */ 552 if (is_master) 553 regmap_clear_bits(rk3308->regmap, RK3308_GLB_CON, RK3308_ADC_DIG_WORK); 554 555 for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { 556 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), 557 RK3308_ADC_I2S_LRC_POL_REVERSAL | 558 RK3308_ADC_I2S_MODE_MSK, 559 adc_aif1); 560 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), 561 RK3308_ADC_IO_MODE_MASTER | 562 RK3308_ADC_MODE_MASTER | 563 RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL, 564 adc_aif2); 565 } 566 567 /* Hold ADC Digital registers end at master mode */ 568 if (is_master) 569 regmap_set_bits(rk3308->regmap, RK3308_GLB_CON, RK3308_ADC_DIG_WORK); 570 571 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, 572 RK3308_DAC_I2S_LRC_POL_REVERSAL | 573 RK3308_DAC_I2S_MODE_MSK, 574 dac_aif1); 575 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, 576 dac_master_bits | RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL, 577 dac_aif2); 578 579 return 0; 580} 581 582static int rk3308_codec_dac_dig_config(struct rk3308_codec_priv *rk3308, 583 struct snd_pcm_hw_params *params) 584{ 585 unsigned int dac_aif1 = 0; 586 587 switch (params_format(params)) { 588 case SNDRV_PCM_FORMAT_S16_LE: 589 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS; 590 break; 591 case SNDRV_PCM_FORMAT_S20_3LE: 592 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS; 593 break; 594 case SNDRV_PCM_FORMAT_S24_LE: 595 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS; 596 break; 597 case SNDRV_PCM_FORMAT_S32_LE: 598 dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS; 599 break; 600 default: 601 return -EINVAL; 602 } 603 604 regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, 605 RK3308_DAC_I2S_VALID_LEN_MSK, dac_aif1); 606 regmap_set_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, RK3308_DAC_I2S_WORK); 607 608 return 0; 609} 610 611static int rk3308_codec_adc_dig_config(struct rk3308_codec_priv *rk3308, 612 struct snd_pcm_hw_params *params) 613{ 614 unsigned int adc_aif1 = 0; 615 /* 616 * grp 0 = ADC1 and ADC2 617 * grp 1 = ADC3 and ADC4 618 * grp 2 = ADC5 and ADC6 619 * grp 3 = ADC7 and ADC8 620 */ 621 u32 used_adc_grps; 622 int grp; 623 624 switch (params_channels(params)) { 625 case 1: 626 adc_aif1 |= RK3308_ADC_I2S_MONO; 627 used_adc_grps = 1; 628 break; 629 case 2: 630 case 4: 631 case 6: 632 case 8: 633 used_adc_grps = params_channels(params) / 2; 634 break; 635 default: 636 dev_err(rk3308->dev, "Invalid channel number %d\n", params_channels(params)); 637 return -EINVAL; 638 } 639 640 switch (params_format(params)) { 641 case SNDRV_PCM_FORMAT_S16_LE: 642 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS; 643 break; 644 case SNDRV_PCM_FORMAT_S20_3LE: 645 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS; 646 break; 647 case SNDRV_PCM_FORMAT_S24_LE: 648 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS; 649 break; 650 case SNDRV_PCM_FORMAT_S32_LE: 651 adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS; 652 break; 653 default: 654 return -EINVAL; 655 } 656 657 for (grp = 0; grp < used_adc_grps; grp++) { 658 regmap_update_bits(rk3308->regmap, 659 RK3308_ADC_DIG_CON03(grp), 660 RK3308_ADC_L_CH_BIST_MSK | RK3308_ADC_R_CH_BIST_MSK, 661 RK3308_ADC_L_CH_NORMAL_LEFT | RK3308_ADC_R_CH_NORMAL_RIGHT); 662 regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), 663 RK3308_ADC_I2S_VALID_LEN_MSK | RK3308_ADC_I2S_MONO, adc_aif1); 664 regmap_set_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), RK3308_ADC_I2S_WORK); 665 } 666 667 return 0; 668} 669 670static int rk3308_codec_hw_params(struct snd_pcm_substream *substream, 671 struct snd_pcm_hw_params *params, 672 struct snd_soc_dai *dai) 673{ 674 struct snd_soc_component *component = dai->component; 675 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); 676 677 return (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 678 rk3308_codec_dac_dig_config(rk3308, params) : 679 rk3308_codec_adc_dig_config(rk3308, params); 680} 681 682static const struct snd_soc_dai_ops rk3308_codec_dai_ops = { 683 .hw_params = rk3308_codec_hw_params, 684 .set_fmt = rk3308_codec_set_dai_fmt, 685}; 686 687static struct snd_soc_dai_driver rk3308_codec_dai_driver = { 688 .name = "rk3308-hifi", 689 .playback = { 690 .stream_name = "HiFi Playback", 691 .channels_min = 2, 692 .channels_max = 2, 693 .rates = SNDRV_PCM_RATE_8000_192000, 694 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 695 SNDRV_PCM_FMTBIT_S20_3LE | 696 SNDRV_PCM_FMTBIT_S24_LE | 697 SNDRV_PCM_FMTBIT_S32_LE), 698 }, 699 .capture = { 700 .stream_name = "HiFi Capture", 701 .channels_min = 1, 702 .channels_max = 8, 703 .rates = SNDRV_PCM_RATE_8000_192000, 704 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 705 SNDRV_PCM_FMTBIT_S20_3LE | 706 SNDRV_PCM_FMTBIT_S24_LE | 707 SNDRV_PCM_FMTBIT_S32_LE), 708 }, 709 .ops = &rk3308_codec_dai_ops, 710}; 711 712static void rk3308_codec_reset(struct snd_soc_component *component) 713{ 714 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); 715 716 reset_control_assert(rk3308->reset); 717 usleep_range(10000, 11000); /* estimated value */ 718 reset_control_deassert(rk3308->reset); 719 720 regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00); 721 usleep_range(10000, 11000); /* estimated value */ 722 regmap_write(rk3308->regmap, RK3308_GLB_CON, 723 RK3308_SYS_WORK | 724 RK3308_DAC_DIG_WORK | 725 RK3308_ADC_DIG_WORK); 726} 727 728/* 729 * Initialize register whose default after HW reset is problematic or which 730 * are never modified. 731 */ 732static int rk3308_codec_initialize(struct rk3308_codec_priv *rk3308) 733{ 734 int grp; 735 736 /* 737 * Init ADC digital vol to 0 dB (reset value is 0xff, undocumented). 738 * Range: -97dB ~ +32dB. 739 */ 740 if (rk3308->codec_ver == ACODEC_VERSION_C) { 741 for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { 742 regmap_write(rk3308->regmap, RK3308_ADC_DIG_CON05(grp), 743 RK3308_ADC_DIG_VOL_CON_x_0DB); 744 regmap_write(rk3308->regmap, RK3308_ADC_DIG_CON06(grp), 745 RK3308_ADC_DIG_VOL_CON_x_0DB); 746 } 747 } 748 749 /* set HPMIX default gains (reset value is 0, which is illegal) */ 750 regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, 751 RK3308_DAC_L_HPMIX_GAIN_MSK | 752 RK3308_DAC_R_HPMIX_GAIN_MSK, 753 RK3308_DAC_L_HPMIX_GAIN_NDB_6 | 754 RK3308_DAC_R_HPMIX_GAIN_NDB_6); 755 756 /* recover DAC digital gain to 0 dB (reset value is 0xff, undocumented) */ 757 if (rk3308->codec_ver == ACODEC_VERSION_C) 758 regmap_write(rk3308->regmap, RK3308_DAC_DIG_CON04, 759 RK3308BS_DAC_DIG_GAIN_0DB); 760 761 /* 762 * Unconditionally enable zero-cross detection (needed for AGC, 763 * harmless without AGC) 764 */ 765 for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) 766 regmap_set_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), 767 RK3308_ADC_CH1_ZEROCROSS_DET_EN | 768 RK3308_ADC_CH2_ZEROCROSS_DET_EN); 769 770 return 0; 771} 772 773static int rk3308_codec_probe(struct snd_soc_component *component) 774{ 775 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); 776 777 rk3308->component = component; 778 779 rk3308_codec_reset(component); 780 rk3308_codec_initialize(rk3308); 781 782 return 0; 783} 784 785static int rk3308_codec_set_bias_level(struct snd_soc_component *component, 786 enum snd_soc_bias_level level) 787{ 788 struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); 789 790 switch (level) { 791 case SND_SOC_BIAS_ON: 792 break; 793 case SND_SOC_BIAS_PREPARE: 794 break; 795 case SND_SOC_BIAS_STANDBY: 796 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_OFF) 797 break; 798 799 /* Sequence from TRM Section 8.6.3 "Power Up" */ 800 regmap_set_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, 801 RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN); 802 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), 803 RK3308_ADC_CURRENT_CHARGE_MSK, 1); 804 regmap_set_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), 805 RK3308_ADC_REF_EN); 806 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), 807 RK3308_ADC_CURRENT_CHARGE_MSK, 0x7f); 808 msleep(20); /* estimated value */ 809 break; 810 case SND_SOC_BIAS_OFF: 811 /* Sequence from TRM Section 8.6.4 "Power Down" */ 812 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), 813 RK3308_ADC_CURRENT_CHARGE_MSK, 1); 814 regmap_clear_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), 815 RK3308_ADC_REF_EN); 816 regmap_clear_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, 817 RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN); 818 msleep(20); /* estimated value */ 819 break; 820 } 821 return 0; 822} 823 824static const struct snd_soc_component_driver rk3308_codec_component_driver = { 825 .probe = rk3308_codec_probe, 826 .set_bias_level = rk3308_codec_set_bias_level, 827 .controls = rk3308_codec_controls, 828 .num_controls = ARRAY_SIZE(rk3308_codec_controls), 829 .dapm_widgets = rk3308_codec_dapm_widgets, 830 .num_dapm_widgets = ARRAY_SIZE(rk3308_codec_dapm_widgets), 831 .dapm_routes = rk3308_codec_dapm_routes, 832 .num_dapm_routes = ARRAY_SIZE(rk3308_codec_dapm_routes), 833}; 834 835static const struct regmap_config rk3308_codec_regmap_config = { 836 .reg_bits = 32, 837 .reg_stride = 4, 838 .val_bits = 32, 839 .max_register = RK3308_DAC_ANA_CON15, 840}; 841 842static int rk3308_codec_get_version(struct rk3308_codec_priv *rk3308) 843{ 844 unsigned int chip_id; 845 int err; 846 847 err = regmap_read(rk3308->grf, GRF_CHIP_ID, &chip_id); 848 if (err) 849 return err; 850 851 switch (chip_id) { 852 case 3306: 853 rk3308->codec_ver = ACODEC_VERSION_A; 854 break; 855 case 0x3308: 856 rk3308->codec_ver = ACODEC_VERSION_B; 857 return dev_err_probe(rk3308->dev, -EINVAL, "Chip version B not supported\n"); 858 case 0x3308c: 859 rk3308->codec_ver = ACODEC_VERSION_C; 860 break; 861 default: 862 return dev_err_probe(rk3308->dev, -EINVAL, "Unknown chip_id: 0x%x\n", chip_id); 863 } 864 865 dev_info(rk3308->dev, "Found codec version %c\n", rk3308->codec_ver); 866 return 0; 867} 868 869static int rk3308_codec_set_micbias_level(struct rk3308_codec_priv *rk3308) 870{ 871 struct device_node *np = rk3308->dev->of_node; 872 u32 percent; 873 u32 mult; 874 int err; 875 876 err = of_property_read_u32(np, "rockchip,micbias-avdd-percent", &percent); 877 if (err == -EINVAL) 878 return 0; 879 if (err) 880 return dev_err_probe(rk3308->dev, err, 881 "Error reading 'rockchip,micbias-avdd-percent'\n"); 882 883 /* Convert percent to register value, linerarly (50% -> 0, 5% step = +1) */ 884 mult = (percent - 50) / 5; 885 886 /* Check range and that the percent was an exact value allowed */ 887 if (mult > RK3308_ADC_LEVEL_RANGE_MICBIAS_MAX || mult * 5 + 50 != percent) 888 return dev_err_probe(rk3308->dev, -EINVAL, 889 "Invalid value %u for 'rockchip,micbias-avdd-percent'\n", 890 percent); 891 892 regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), 893 RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, 894 mult << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT); 895 896 return 0; 897} 898 899static int rk3308_codec_platform_probe(struct platform_device *pdev) 900{ 901 struct device_node *np = pdev->dev.of_node; 902 struct device *dev = &pdev->dev; 903 struct rk3308_codec_priv *rk3308; 904 void __iomem *base; 905 int err; 906 907 rk3308 = devm_kzalloc(&pdev->dev, sizeof(*rk3308), GFP_KERNEL); 908 if (!rk3308) 909 return -ENOMEM; 910 911 rk3308->dev = dev; 912 913 rk3308->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 914 if (IS_ERR(rk3308->grf)) 915 return dev_err_probe(dev, PTR_ERR(rk3308->grf), "Error getting GRF\n"); 916 917 rk3308->reset = devm_reset_control_get_optional_exclusive(dev, "codec"); 918 if (IS_ERR(rk3308->reset)) 919 return dev_err_probe(dev, PTR_ERR(rk3308->reset), "Failed to get reset control\n"); 920 921 err = devm_clk_bulk_get(dev, ARRAY_SIZE(rk3308_codec_clocks), rk3308_codec_clocks); 922 if (err) 923 return dev_err_probe(dev, err, "Failed to get clocks\n"); 924 925 err = clk_bulk_prepare_enable(ARRAY_SIZE(rk3308_codec_clocks), rk3308_codec_clocks); 926 if (err) 927 return dev_err_probe(dev, err, "Failed to enable clocks\n"); 928 929 err = rk3308_codec_get_version(rk3308); 930 if (err) 931 return err; 932 933 base = devm_platform_ioremap_resource(pdev, 0); 934 if (IS_ERR(base)) 935 return PTR_ERR(base); 936 937 rk3308->regmap = devm_regmap_init_mmio(dev, base, &rk3308_codec_regmap_config); 938 if (IS_ERR(rk3308->regmap)) 939 return dev_err_probe(dev, PTR_ERR(rk3308->regmap), 940 "Failed to init regmap\n"); 941 942 platform_set_drvdata(pdev, rk3308); 943 944 err = rk3308_codec_set_micbias_level(rk3308); 945 if (err) 946 return err; 947 948 err = devm_snd_soc_register_component(dev, &rk3308_codec_component_driver, 949 &rk3308_codec_dai_driver, 1); 950 if (err) 951 return dev_err_probe(dev, err, "Failed to register codec\n"); 952 953 return 0; 954} 955 956static const struct of_device_id __maybe_unused rk3308_codec_of_match[] = { 957 { .compatible = "rockchip,rk3308-codec", }, 958 {}, 959}; 960MODULE_DEVICE_TABLE(of, rk3308_codec_of_match); 961 962static struct platform_driver rk3308_codec_driver = { 963 .driver = { 964 .name = "rk3308-acodec", 965 .of_match_table = rk3308_codec_of_match, 966 }, 967 .probe = rk3308_codec_platform_probe, 968}; 969module_platform_driver(rk3308_codec_driver); 970 971MODULE_AUTHOR("Xing Zheng <zhengxing@rock-chips.com>"); 972MODULE_AUTHOR("Luca Ceresoli <luca.ceresoli@bootlin.com>"); 973MODULE_DESCRIPTION("ASoC RK3308 Codec Driver"); 974MODULE_LICENSE("GPL"); 975