1// SPDX-License-Identifier: GPL-2.0-only 2// 3// Components shared between ASoC and HDA CS35L56 drivers 4// 5// Copyright (C) 2023 Cirrus Logic, Inc. and 6// Cirrus Logic International Semiconductor Ltd. 7 8#include <linux/firmware/cirrus/wmfw.h> 9#include <linux/gpio/consumer.h> 10#include <linux/regmap.h> 11#include <linux/regulator/consumer.h> 12#include <linux/types.h> 13#include <sound/cs-amp-lib.h> 14 15#include "cs35l56.h" 16 17static const struct reg_sequence cs35l56_patch[] = { 18 /* 19 * Firmware can change these to non-defaults to satisfy SDCA. 20 * Ensure that they are at known defaults. 21 */ 22 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 23 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 24 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 25 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 26 27 /* These are not reset by a soft-reset, so patch to defaults. */ 28 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 29 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 30 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 31}; 32 33int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 34{ 35 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 36 ARRAY_SIZE(cs35l56_patch)); 37} 38EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED); 39 40static const struct reg_default cs35l56_reg_defaults[] = { 41 /* no defaults for OTP_MEM - first read populates cache */ 42 43 /* 44 * No defaults for ASP1 control or ASP1TX mixer. See 45 * cs35l56_populate_asp1_register_defaults() and 46 * cs35l56_sync_asp1_mixer_widgets_with_firmware(). 47 */ 48 49 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 50 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 51 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 52 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 53 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 54 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 55 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 56 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 57 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 58 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 59 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 60 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 61 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 62}; 63 64static bool cs35l56_is_dsp_memory(unsigned int reg) 65{ 66 switch (reg) { 67 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 68 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 69 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 70 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 71 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 72 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 73 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 74 return true; 75 default: 76 return false; 77 } 78} 79 80static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 81{ 82 switch (reg) { 83 case CS35L56_DEVID: 84 case CS35L56_REVID: 85 case CS35L56_RELID: 86 case CS35L56_OTPID: 87 case CS35L56_SFT_RESET: 88 case CS35L56_GLOBAL_ENABLES: 89 case CS35L56_BLOCK_ENABLES: 90 case CS35L56_BLOCK_ENABLES2: 91 case CS35L56_REFCLK_INPUT: 92 case CS35L56_GLOBAL_SAMPLE_RATE: 93 case CS35L56_OTP_MEM_53: 94 case CS35L56_OTP_MEM_54: 95 case CS35L56_OTP_MEM_55: 96 case CS35L56_ASP1_ENABLES1: 97 case CS35L56_ASP1_CONTROL1: 98 case CS35L56_ASP1_CONTROL2: 99 case CS35L56_ASP1_CONTROL3: 100 case CS35L56_ASP1_FRAME_CONTROL1: 101 case CS35L56_ASP1_FRAME_CONTROL5: 102 case CS35L56_ASP1_DATA_CONTROL1: 103 case CS35L56_ASP1_DATA_CONTROL5: 104 case CS35L56_DACPCM1_INPUT: 105 case CS35L56_DACPCM2_INPUT: 106 case CS35L56_ASP1TX1_INPUT: 107 case CS35L56_ASP1TX2_INPUT: 108 case CS35L56_ASP1TX3_INPUT: 109 case CS35L56_ASP1TX4_INPUT: 110 case CS35L56_DSP1RX1_INPUT: 111 case CS35L56_DSP1RX2_INPUT: 112 case CS35L56_SWIRE_DP3_CH1_INPUT: 113 case CS35L56_SWIRE_DP3_CH2_INPUT: 114 case CS35L56_SWIRE_DP3_CH3_INPUT: 115 case CS35L56_SWIRE_DP3_CH4_INPUT: 116 case CS35L56_IRQ1_CFG: 117 case CS35L56_IRQ1_STATUS: 118 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 119 case CS35L56_IRQ1_EINT_18: 120 case CS35L56_IRQ1_EINT_20: 121 case CS35L56_IRQ1_MASK_1: 122 case CS35L56_IRQ1_MASK_2: 123 case CS35L56_IRQ1_MASK_4: 124 case CS35L56_IRQ1_MASK_8: 125 case CS35L56_IRQ1_MASK_18: 126 case CS35L56_IRQ1_MASK_20: 127 case CS35L56_DSP_VIRTUAL1_MBOX_1: 128 case CS35L56_DSP_VIRTUAL1_MBOX_2: 129 case CS35L56_DSP_VIRTUAL1_MBOX_3: 130 case CS35L56_DSP_VIRTUAL1_MBOX_4: 131 case CS35L56_DSP_VIRTUAL1_MBOX_5: 132 case CS35L56_DSP_VIRTUAL1_MBOX_6: 133 case CS35L56_DSP_VIRTUAL1_MBOX_7: 134 case CS35L56_DSP_VIRTUAL1_MBOX_8: 135 case CS35L56_DSP_RESTRICT_STS1: 136 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 137 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 138 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 139 case CS35L56_DSP1_SCRATCH1: 140 case CS35L56_DSP1_SCRATCH2: 141 case CS35L56_DSP1_SCRATCH3: 142 case CS35L56_DSP1_SCRATCH4: 143 return true; 144 default: 145 return cs35l56_is_dsp_memory(reg); 146 } 147} 148 149static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 150{ 151 switch (reg) { 152 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 153 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 154 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 155 return true; 156 default: 157 return false; 158 } 159} 160 161static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 162{ 163 switch (reg) { 164 case CS35L56_DEVID: 165 case CS35L56_REVID: 166 case CS35L56_RELID: 167 case CS35L56_OTPID: 168 case CS35L56_SFT_RESET: 169 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 170 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 171 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 172 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 173 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 174 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 175 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 176 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 177 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 178 case CS35L56_IRQ1_STATUS: 179 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 180 case CS35L56_IRQ1_EINT_18: 181 case CS35L56_IRQ1_EINT_20: 182 case CS35L56_DSP_VIRTUAL1_MBOX_1: 183 case CS35L56_DSP_VIRTUAL1_MBOX_2: 184 case CS35L56_DSP_VIRTUAL1_MBOX_3: 185 case CS35L56_DSP_VIRTUAL1_MBOX_4: 186 case CS35L56_DSP_VIRTUAL1_MBOX_5: 187 case CS35L56_DSP_VIRTUAL1_MBOX_6: 188 case CS35L56_DSP_VIRTUAL1_MBOX_7: 189 case CS35L56_DSP_VIRTUAL1_MBOX_8: 190 case CS35L56_DSP_RESTRICT_STS1: 191 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 192 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 193 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 194 case CS35L56_DSP1_SCRATCH1: 195 case CS35L56_DSP1_SCRATCH2: 196 case CS35L56_DSP1_SCRATCH3: 197 case CS35L56_DSP1_SCRATCH4: 198 return true; 199 case CS35L56_MAIN_RENDER_USER_MUTE: 200 case CS35L56_MAIN_RENDER_USER_VOLUME: 201 case CS35L56_MAIN_POSTURE_NUMBER: 202 return false; 203 default: 204 return cs35l56_is_dsp_memory(reg); 205 } 206} 207 208static const struct reg_sequence cs35l56_asp1_defaults[] = { 209 REG_SEQ0(CS35L56_ASP1_ENABLES1, 0x00000000), 210 REG_SEQ0(CS35L56_ASP1_CONTROL1, 0x00000028), 211 REG_SEQ0(CS35L56_ASP1_CONTROL2, 0x18180200), 212 REG_SEQ0(CS35L56_ASP1_CONTROL3, 0x00000002), 213 REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL1, 0x03020100), 214 REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL5, 0x00020100), 215 REG_SEQ0(CS35L56_ASP1_DATA_CONTROL1, 0x00000018), 216 REG_SEQ0(CS35L56_ASP1_DATA_CONTROL5, 0x00000018), 217}; 218 219/* 220 * The firmware can have control of the ASP so we don't provide regmap 221 * with defaults for these registers, to prevent a regcache_sync() from 222 * overwriting the firmware settings. But if the machine driver hooks up 223 * the ASP it means the driver is taking control of the ASP, so then the 224 * registers are populated with the defaults. 225 */ 226int cs35l56_init_asp1_regs_for_driver_control(struct cs35l56_base *cs35l56_base) 227{ 228 if (!cs35l56_base->fw_owns_asp1) 229 return 0; 230 231 cs35l56_base->fw_owns_asp1 = false; 232 233 return regmap_multi_reg_write(cs35l56_base->regmap, cs35l56_asp1_defaults, 234 ARRAY_SIZE(cs35l56_asp1_defaults)); 235} 236EXPORT_SYMBOL_NS_GPL(cs35l56_init_asp1_regs_for_driver_control, SND_SOC_CS35L56_SHARED); 237 238/* 239 * The firmware boot sequence can overwrite the ASP1 config registers so that 240 * they don't match regmap's view of their values. Rewrite the values from the 241 * regmap cache into the hardware registers. 242 */ 243int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base) 244{ 245 struct reg_sequence asp1_regs[ARRAY_SIZE(cs35l56_asp1_defaults)]; 246 int i, ret; 247 248 if (cs35l56_base->fw_owns_asp1) 249 return 0; 250 251 memcpy(asp1_regs, cs35l56_asp1_defaults, sizeof(asp1_regs)); 252 253 /* Read current values from regmap cache into the write sequence */ 254 for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) { 255 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def); 256 if (ret) 257 goto err; 258 } 259 260 /* Write the values cache-bypassed so that they will be written to silicon */ 261 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs, 262 ARRAY_SIZE(asp1_regs)); 263 if (ret) 264 goto err; 265 266 return 0; 267 268err: 269 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret); 270 271 return ret; 272} 273EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED); 274 275int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 276{ 277 unsigned int val; 278 int ret; 279 280 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 281 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 282 val, (val == 0), 283 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 284 if (ret) { 285 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 286 return ret; 287 } 288 289 return 0; 290} 291EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED); 292 293int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 294{ 295 int ret; 296 unsigned int reg; 297 unsigned int val; 298 299 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 300 if (ret) 301 return ret; 302 303 if (cs35l56_base->rev < CS35L56_REVID_B0) 304 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 305 else 306 reg = CS35L56_DSP1_PM_CUR_STATE; 307 308 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg, 309 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 310 CS35L56_HALO_STATE_POLL_US, 311 CS35L56_HALO_STATE_TIMEOUT_US); 312 if (ret < 0) 313 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 314 val, ret); 315 return ret; 316} 317EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); 318 319int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 320{ 321 unsigned int reg; 322 unsigned int val = 0; 323 int read_ret, poll_ret; 324 325 if (cs35l56_base->rev < CS35L56_REVID_B0) 326 reg = CS35L56_DSP1_HALO_STATE_A1; 327 else 328 reg = CS35L56_DSP1_HALO_STATE; 329 330 /* 331 * The regmap must remain in cache-only until the chip has 332 * booted, so use a bypassed read of the status register. 333 */ 334 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 335 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 336 CS35L56_HALO_STATE_POLL_US, 337 CS35L56_HALO_STATE_TIMEOUT_US, 338 false, 339 cs35l56_base->regmap, reg, &val); 340 341 if (poll_ret) { 342 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 343 read_ret, val); 344 return -EIO; 345 } 346 347 return 0; 348} 349EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED); 350 351void cs35l56_wait_control_port_ready(void) 352{ 353 /* Wait for control port to be ready (datasheet tIRS). */ 354 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 355} 356EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED); 357 358void cs35l56_wait_min_reset_pulse(void) 359{ 360 /* Satisfy minimum reset pulse width spec */ 361 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 362} 363EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED); 364 365static const struct reg_sequence cs35l56_system_reset_seq[] = { 366 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 367 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 368}; 369 370void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 371{ 372 /* 373 * Must enter cache-only first so there can't be any more register 374 * accesses other than the controlled system reset sequence below. 375 */ 376 regcache_cache_only(cs35l56_base->regmap, true); 377 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 378 cs35l56_system_reset_seq, 379 ARRAY_SIZE(cs35l56_system_reset_seq)); 380 381 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 382 if (is_soundwire) 383 return; 384 385 cs35l56_wait_control_port_ready(); 386 387 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 388} 389EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED); 390 391int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 392{ 393 int ret; 394 395 if (!irq) 396 return 0; 397 398 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 399 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 400 "cs35l56", cs35l56_base); 401 if (!ret) 402 cs35l56_base->irq = irq; 403 else 404 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 405 406 return ret; 407} 408EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED); 409 410irqreturn_t cs35l56_irq(int irq, void *data) 411{ 412 struct cs35l56_base *cs35l56_base = data; 413 unsigned int status1 = 0, status8 = 0, status20 = 0; 414 unsigned int mask1, mask8, mask20; 415 unsigned int val; 416 int rv; 417 418 irqreturn_t ret = IRQ_NONE; 419 420 if (!cs35l56_base->init_done) 421 return IRQ_NONE; 422 423 mutex_lock(&cs35l56_base->irq_lock); 424 425 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 426 if (rv < 0) { 427 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 428 goto err_unlock; 429 } 430 431 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 432 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 433 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 434 goto err; 435 } 436 437 /* Ack interrupts */ 438 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 439 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 440 status1 &= ~mask1; 441 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 442 443 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 444 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 445 status8 &= ~mask8; 446 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 447 448 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 449 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 450 status20 &= ~mask20; 451 /* We don't want EINT20 but they default to unmasked: force mask */ 452 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 453 454 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 455 456 /* Check to see if unmasked bits are active */ 457 if (!status1 && !status8 && !status20) 458 goto err; 459 460 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 461 dev_crit(cs35l56_base->dev, "Amp short error\n"); 462 463 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 464 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 465 466 ret = IRQ_HANDLED; 467 468err: 469 pm_runtime_put(cs35l56_base->dev); 470err_unlock: 471 mutex_unlock(&cs35l56_base->irq_lock); 472 473 return ret; 474} 475EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED); 476 477int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 478{ 479 unsigned int val; 480 int ret; 481 482 /* 483 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 484 * can't be used here to test for memory retention. 485 * Assume that tuning must be re-loaded. 486 */ 487 if (cs35l56_base->secured) 488 return true; 489 490 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 491 if (ret) { 492 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 493 return ret; 494 } 495 496 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val); 497 if (ret) 498 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 499 else 500 ret = !!(val & CS35L56_FIRMWARE_MISSING); 501 502 pm_runtime_put_autosuspend(cs35l56_base->dev); 503 504 return ret; 505} 506EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); 507 508static const struct reg_sequence cs35l56_hibernate_seq[] = { 509 /* This must be the last register access */ 510 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 511}; 512 513static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 514 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 515}; 516 517static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 518{ 519 /* 520 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 521 * transactions to meet the minimum required time from the rising edge 522 * to the last falling edge of wake. 523 * 524 * It uses bypassed write because we must wake the chip before 525 * disabling regmap cache-only. 526 * 527 * This can NAK on I2C which will terminate the write sequence so the 528 * single-write sequence is issued twice. 529 */ 530 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 531 cs35l56_hibernate_wake_seq, 532 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 533 534 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 535 536 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 537 cs35l56_hibernate_wake_seq, 538 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 539 540 cs35l56_wait_control_port_ready(); 541} 542 543int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 544{ 545 unsigned int val; 546 int ret; 547 548 if (!cs35l56_base->init_done) 549 return 0; 550 551 /* Firmware must have entered a power-save state */ 552 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 553 CS35L56_TRANSDUCER_ACTUAL_PS, 554 val, (val >= CS35L56_PS3), 555 CS35L56_PS3_POLL_US, 556 CS35L56_PS3_TIMEOUT_US); 557 if (ret) 558 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 559 560 /* Clear BOOT_DONE so it can be used to detect a reboot */ 561 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 562 563 if (!cs35l56_base->can_hibernate) { 564 regcache_cache_only(cs35l56_base->regmap, true); 565 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 566 567 return 0; 568 } 569 570 /* 571 * Must enter cache-only first so there can't be any more register 572 * accesses other than the controlled hibernate sequence below. 573 */ 574 regcache_cache_only(cs35l56_base->regmap, true); 575 576 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 577 cs35l56_hibernate_seq, 578 ARRAY_SIZE(cs35l56_hibernate_seq)); 579 580 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 581 582 return 0; 583} 584EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED); 585 586int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 587{ 588 unsigned int val; 589 int ret; 590 591 if (!cs35l56_base->init_done) 592 return 0; 593 594 if (!cs35l56_base->can_hibernate) 595 goto out_sync; 596 597 /* Must be done before releasing cache-only */ 598 if (!is_soundwire) 599 cs35l56_issue_wake_event(cs35l56_base); 600 601out_sync: 602 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 603 if (ret) { 604 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 605 goto err; 606 } 607 608 regcache_cache_only(cs35l56_base->regmap, false); 609 610 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 611 if (ret) 612 goto err; 613 614 /* BOOT_DONE will be 1 if the amp reset */ 615 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 616 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 617 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 618 regcache_mark_dirty(cs35l56_base->regmap); 619 } 620 621 regcache_sync(cs35l56_base->regmap); 622 623 dev_dbg(cs35l56_base->dev, "Resumed"); 624 625 return 0; 626 627err: 628 regcache_cache_only(cs35l56_base->regmap, true); 629 630 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 631 cs35l56_hibernate_seq, 632 ARRAY_SIZE(cs35l56_hibernate_seq)); 633 634 return ret; 635} 636EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); 637 638static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 639 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 640 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 641 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 642 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 643 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 644}; 645 646void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 647{ 648 cs_dsp->num = 1; 649 cs_dsp->type = WMFW_HALO; 650 cs_dsp->rev = 0; 651 cs_dsp->dev = cs35l56_base->dev; 652 cs_dsp->regmap = cs35l56_base->regmap; 653 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 654 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 655 cs_dsp->mem = cs35l56_dsp1_regions; 656 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 657 cs_dsp->no_core_startstop = true; 658} 659EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED); 660 661struct cs35l56_pte { 662 u8 x; 663 u8 wafer_id; 664 u8 pte[2]; 665 u8 lot[3]; 666 u8 y; 667 u8 unused[3]; 668 u8 dvs; 669} __packed; 670static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 671 672static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid) 673{ 674 struct cs35l56_pte pte; 675 u64 unique_id; 676 int ret; 677 678 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 679 if (ret) { 680 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 681 return ret; 682 } 683 684 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 685 unique_id <<= 32; 686 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 687 ((u32)pte.dvs << 24); 688 689 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id); 690 691 *uid = unique_id; 692 693 return 0; 694} 695 696/* Firmware calibration controls */ 697const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 698 .alg_id = 0x9f210, 699 .mem_region = WMFW_ADSP2_YM, 700 .ambient = "CAL_AMBIENT", 701 .calr = "CAL_R", 702 .status = "CAL_STATUS", 703 .checksum = "CAL_CHECKSUM", 704}; 705EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, SND_SOC_CS35L56_SHARED); 706 707int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 708{ 709 u64 silicon_uid = 0; 710 int ret; 711 712 /* Driver can't apply calibration to a secured part, so skip */ 713 if (cs35l56_base->secured) 714 return 0; 715 716 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid); 717 if (ret < 0) 718 return ret; 719 720 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid, 721 cs35l56_base->cal_index, 722 &cs35l56_base->cal_data); 723 724 /* Only return an error status if probe should be aborted */ 725 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 726 return 0; 727 728 if (ret < 0) 729 return ret; 730 731 cs35l56_base->cal_data_valid = true; 732 733 return 0; 734} 735EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, SND_SOC_CS35L56_SHARED); 736 737int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 738 bool *fw_missing, unsigned int *fw_version) 739{ 740 unsigned int prot_status; 741 int ret; 742 743 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status); 744 if (ret) { 745 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 746 return ret; 747 } 748 749 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 750 751 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version); 752 if (ret) { 753 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 754 return ret; 755 } 756 757 return 0; 758} 759EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED); 760 761int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 762{ 763 int ret; 764 unsigned int devid, revid, otpid, secured, fw_ver; 765 bool fw_missing; 766 767 /* 768 * When the system is not using a reset_gpio ensure the device is 769 * awake, otherwise the device has just been released from reset and 770 * the driver must wait for the control port to become usable. 771 */ 772 if (!cs35l56_base->reset_gpio) 773 cs35l56_issue_wake_event(cs35l56_base); 774 else 775 cs35l56_wait_control_port_ready(); 776 777 /* 778 * The HALO_STATE register is in different locations on Ax and B0 779 * devices so the REVID needs to be determined before waiting for the 780 * firmware to boot. 781 */ 782 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 783 if (ret < 0) { 784 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 785 return ret; 786 } 787 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 788 789 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 790 if (ret) 791 return ret; 792 793 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 794 if (ret < 0) { 795 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 796 return ret; 797 } 798 devid &= CS35L56_DEVID_MASK; 799 800 switch (devid) { 801 case 0x35A54: 802 case 0x35A56: 803 case 0x35A57: 804 break; 805 default: 806 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 807 return ret; 808 } 809 810 cs35l56_base->type = devid & 0xFF; 811 812 /* Silicon is now identified and booted so exit cache-only */ 813 regcache_cache_only(cs35l56_base->regmap, false); 814 815 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 816 if (ret) { 817 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 818 return ret; 819 } 820 821 /* When any bus is restricted treat the device as secured */ 822 if (secured & CS35L56_RESTRICTED_MASK) 823 cs35l56_base->secured = true; 824 825 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 826 if (ret < 0) { 827 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 828 return ret; 829 } 830 831 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 832 if (ret) 833 return ret; 834 835 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 836 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 837 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 838 839 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 840 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 841 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 842 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 843 0); 844 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 845 CS35L56_TEMP_ERR_EINT1_MASK, 846 0); 847 848 return 0; 849} 850EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED); 851 852int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 853{ 854 struct gpio_descs *descs; 855 int speaker_id; 856 int i, ret; 857 858 /* Read the speaker type qualifier from the motherboard GPIOs */ 859 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 860 if (!descs) { 861 return -ENOENT; 862 } else if (IS_ERR(descs)) { 863 ret = PTR_ERR(descs); 864 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 865 } 866 867 speaker_id = 0; 868 for (i = 0; i < descs->ndescs; i++) { 869 ret = gpiod_get_value_cansleep(descs->desc[i]); 870 if (ret < 0) { 871 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 872 goto err; 873 } 874 875 speaker_id |= (ret << i); 876 } 877 878 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 879 ret = speaker_id; 880err: 881 gpiod_put_array(descs); 882 883 return ret; 884} 885EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED); 886 887static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 888 [0x0C] = 128000, 889 [0x0F] = 256000, 890 [0x11] = 384000, 891 [0x12] = 512000, 892 [0x15] = 768000, 893 [0x17] = 1024000, 894 [0x1A] = 1500000, 895 [0x1B] = 1536000, 896 [0x1C] = 2000000, 897 [0x1D] = 2048000, 898 [0x1E] = 2400000, 899 [0x20] = 3000000, 900 [0x21] = 3072000, 901 [0x23] = 4000000, 902 [0x24] = 4096000, 903 [0x25] = 4800000, 904 [0x27] = 6000000, 905 [0x28] = 6144000, 906 [0x29] = 6250000, 907 [0x2A] = 6400000, 908 [0x2E] = 8000000, 909 [0x2F] = 8192000, 910 [0x30] = 9600000, 911 [0x32] = 12000000, 912 [0x33] = 12288000, 913 [0x37] = 13500000, 914 [0x38] = 19200000, 915 [0x39] = 22579200, 916 [0x3B] = 24576000, 917}; 918 919int cs35l56_get_bclk_freq_id(unsigned int freq) 920{ 921 int i; 922 923 if (freq == 0) 924 return -EINVAL; 925 926 /* The BCLK frequency must be a valid PLL REFCLK */ 927 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 928 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 929 return i; 930 } 931 932 return -EINVAL; 933} 934EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED); 935 936static const char * const cs35l56_supplies[/* auto-sized */] = { 937 "VDD_P", 938 "VDD_IO", 939 "VDD_A", 940}; 941 942void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 943{ 944 int i; 945 946 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 947 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 948 data[i].supply = cs35l56_supplies[i]; 949} 950EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED); 951 952const char * const cs35l56_tx_input_texts[] = { 953 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 954 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 955 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 956 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 957}; 958EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED); 959 960const unsigned int cs35l56_tx_input_values[] = { 961 CS35L56_INPUT_SRC_NONE, 962 CS35L56_INPUT_SRC_ASP1RX1, 963 CS35L56_INPUT_SRC_ASP1RX2, 964 CS35L56_INPUT_SRC_VMON, 965 CS35L56_INPUT_SRC_IMON, 966 CS35L56_INPUT_SRC_ERR_VOL, 967 CS35L56_INPUT_SRC_CLASSH, 968 CS35L56_INPUT_SRC_VDDBMON, 969 CS35L56_INPUT_SRC_VBSTMON, 970 CS35L56_INPUT_SRC_DSP1TX1, 971 CS35L56_INPUT_SRC_DSP1TX2, 972 CS35L56_INPUT_SRC_DSP1TX3, 973 CS35L56_INPUT_SRC_DSP1TX4, 974 CS35L56_INPUT_SRC_DSP1TX5, 975 CS35L56_INPUT_SRC_DSP1TX6, 976 CS35L56_INPUT_SRC_DSP1TX7, 977 CS35L56_INPUT_SRC_DSP1TX8, 978 CS35L56_INPUT_SRC_TEMPMON, 979 CS35L56_INPUT_SRC_INTERPOLATOR, 980 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 981 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 982}; 983EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED); 984 985struct regmap_config cs35l56_regmap_i2c = { 986 .reg_bits = 32, 987 .val_bits = 32, 988 .reg_stride = 4, 989 .reg_format_endian = REGMAP_ENDIAN_BIG, 990 .val_format_endian = REGMAP_ENDIAN_BIG, 991 .max_register = CS35L56_DSP1_PMEM_5114, 992 .reg_defaults = cs35l56_reg_defaults, 993 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 994 .volatile_reg = cs35l56_volatile_reg, 995 .readable_reg = cs35l56_readable_reg, 996 .precious_reg = cs35l56_precious_reg, 997 .cache_type = REGCACHE_MAPLE, 998}; 999EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED); 1000 1001struct regmap_config cs35l56_regmap_spi = { 1002 .reg_bits = 32, 1003 .val_bits = 32, 1004 .pad_bits = 16, 1005 .reg_stride = 4, 1006 .reg_format_endian = REGMAP_ENDIAN_BIG, 1007 .val_format_endian = REGMAP_ENDIAN_BIG, 1008 .max_register = CS35L56_DSP1_PMEM_5114, 1009 .reg_defaults = cs35l56_reg_defaults, 1010 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1011 .volatile_reg = cs35l56_volatile_reg, 1012 .readable_reg = cs35l56_readable_reg, 1013 .precious_reg = cs35l56_precious_reg, 1014 .cache_type = REGCACHE_MAPLE, 1015}; 1016EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED); 1017 1018struct regmap_config cs35l56_regmap_sdw = { 1019 .reg_bits = 32, 1020 .val_bits = 32, 1021 .reg_stride = 4, 1022 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1023 .val_format_endian = REGMAP_ENDIAN_BIG, 1024 .max_register = CS35L56_DSP1_PMEM_5114, 1025 .reg_defaults = cs35l56_reg_defaults, 1026 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1027 .volatile_reg = cs35l56_volatile_reg, 1028 .readable_reg = cs35l56_readable_reg, 1029 .precious_reg = cs35l56_precious_reg, 1030 .cache_type = REGCACHE_MAPLE, 1031}; 1032EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED); 1033 1034MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1035MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1036MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1037MODULE_LICENSE("GPL"); 1038MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB); 1039