1169691Skan/* SPDX-License-Identifier: GPL-2.0+ */ 2169691Skan/* 3169691Skan * AMD ALSA SoC PDM Driver 4169691Skan * 5169691Skan * Copyright 2020 Advanced Micro Devices, Inc. 6169691Skan */ 7169691Skan 8169691Skan#include "rn_chip_offset_byte.h" 9169691Skan 10169691Skan#define ACP_DEVS 3 11169691Skan#define ACP_PHY_BASE_ADDRESS 0x1240000 12169691Skan#define ACP_REG_START 0x1240000 13169691Skan#define ACP_REG_END 0x1250200 14169691Skan 15169691Skan#define ACP_DEVICE_ID 0x15E2 16169691Skan#define ACP_POWER_ON 0x00 17169691Skan#define ACP_POWER_ON_IN_PROGRESS 0x01 18169691Skan#define ACP_POWER_OFF 0x02 19169691Skan#define ACP_POWER_OFF_IN_PROGRESS 0x03 20169691Skan#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 21169691Skan 22169691Skan#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 23169691Skan#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00 24169691Skan#define ACP_PGFSM_STATUS_MASK 0x03 25169691Skan#define ACP_POWERED_ON 0x00 26169691Skan#define ACP_POWER_ON_IN_PROGRESS 0x01 27169691Skan#define ACP_POWERED_OFF 0x02 28169691Skan#define ACP_POWER_OFF_IN_PROGRESS 0x03 29169691Skan 30169691Skan#define ACP_ERROR_MASK 0x20000000 31169691Skan#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF 32169691Skan#define PDM_DMA_STAT 0x10 33169691Skan#define PDM_DMA_INTR_MASK 0x10000 34169691Skan#define ACP_ERROR_STAT 29 35169691Skan#define PDM_DECIMATION_FACTOR 0x2 36169691Skan#define ACP_PDM_CLK_FREQ_MASK 0x07 37169691Skan#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3) 38169691Skan#define ACP_PDM_ENABLE 0x01 39169691Skan#define ACP_PDM_DISABLE 0x00 40169691Skan#define ACP_PDM_DMA_EN_STATUS 0x02 41169691Skan#define TWO_CH 0x02 42169691Skan#define DELAY_US 5 43169691Skan#define ACP_COUNTER 20000 44169691Skan/* time in ms for runtime suspend delay */ 45169691Skan#define ACP_SUSPEND_DELAY_MS 2000 46169691Skan 47169691Skan#define ACP_SRAM_PTE_OFFSET 0x02050000 48169691Skan#define PAGE_SIZE_4K_ENABLE 0x2 49169691Skan#define MEM_WINDOW_START 0x4000000 50169691Skan 51169691Skan#define CAPTURE_MIN_NUM_PERIODS 4 52169691Skan#define CAPTURE_MAX_NUM_PERIODS 4 53169691Skan#define CAPTURE_MAX_PERIOD_SIZE 8192 54169691Skan#define CAPTURE_MIN_PERIOD_SIZE 4096 55169691Skan 56169691Skan#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) 57169691Skan#define MIN_BUFFER MAX_BUFFER 58169691Skan#define ACP_DMIC_AUTO -1 59169691Skan 60169691Skanstruct pdm_dev_data { 61169691Skan u32 pdm_irq; 62169691Skan void __iomem *acp_base; 63169691Skan struct snd_pcm_substream *capture_stream; 64169691Skan}; 65169691Skan 66169691Skanstruct pdm_stream_instance { 67169691Skan u16 num_pages; 68169691Skan u16 channels; 69169691Skan dma_addr_t dma_addr; 70169691Skan u64 bytescount; 71169691Skan void __iomem *acp_base; 72169691Skan}; 73169691Skan 74169691Skanunion acp_pdm_dma_count { 75169691Skan struct { 76169691Skan u32 low; 77169691Skan u32 high; 78169691Skan } bcount; 79169691Skan u64 bytescount; 80169691Skan}; 81169691Skan 82169691Skanstatic inline u32 rn_readl(void __iomem *base_addr) 83169691Skan{ 84169691Skan return readl(base_addr - ACP_PHY_BASE_ADDRESS); 85169691Skan} 86169691Skan 87169691Skanstatic inline void rn_writel(u32 val, void __iomem *base_addr) 88169691Skan{ 89169691Skan writel(val, base_addr - ACP_PHY_BASE_ADDRESS); 90169691Skan} 91169691Skan 92169691Skan/* Machine configuration */ 93169691Skanint snd_amd_acp_find_config(struct pci_dev *pci); 94169691Skan