1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 Aureal Advantage Soundcard driver. 4 */ 5 6#define CHIP_AU8810 7 8#define CARD_NAME "Aureal Advantage" 9#define CARD_NAME_SHORT "au8810" 10 11#define NR_ADB 0x10 12#define NR_WT 0x00 13#define NR_SRC 0x10 14#define NR_A3D 0x10 15#define NR_MIXIN 0x20 16#define NR_MIXOUT 0x10 17 18 19/* ADBDMA */ 20#define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */ 21#define POS_MASK 0x00000fff 22#define POS_SHIFT 0x0 23#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ 24#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ 25#define VORTEX_ADBDMA_CTRL 0x27180 /* write only; format, flags, DMA pos */ 26#define OFFSET_MASK 0x00000fff 27#define OFFSET_SHIFT 0x0 28#define IE_MASK 0x00001000 /* interrupt enable. */ 29#define IE_SHIFT 0xc 30#define DIR_MASK 0x00002000 /* Direction */ 31#define DIR_SHIFT 0xd 32#define FMT_MASK 0x0003c000 33#define FMT_SHIFT 0xe 34// The ADB masks and shift also are valid for the wtdma, except if specified otherwise. 35#define VORTEX_ADBDMA_BUFCFG0 0x27100 36#define VORTEX_ADBDMA_BUFCFG1 0x27104 37#define VORTEX_ADBDMA_BUFBASE 0x27000 38#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */ 39 40#define VORTEX_ADBDMA_STATUS 0x27A90 /* stored at AdbDma->this_10 / 2 DWORD in size. */ 41 42/* WTDMA */ 43#define VORTEX_WTDMA_CTRL 0x27fd8 /* format, DMA pos */ 44#define VORTEX_WTDMA_STAT 0x27fe8 /* DMA subbuf, DMA pos */ 45#define WT_SUBBUF_MASK 0x3 46#define WT_SUBBUF_SHIFT 0xc 47#define VORTEX_WTDMA_BUFBASE 0x27fc0 48#define VORTEX_WTDMA_BUFCFG0 0x27fd0 49#define VORTEX_WTDMA_BUFCFG1 0x27fd4 50#define VORTEX_WTDMA_START 0x27fe4 /* which subbuffer is first */ 51 52/* ADB */ 53#define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */ 54#define VORTEX_ADB_RTBASE 0x28000 55#define VORTEX_ADB_RTBASE_COUNT 173 56#define VORTEX_ADB_CHNBASE 0x282b4 57#define VORTEX_ADB_CHNBASE_COUNT 24 58#define ROUTE_MASK 0xffff 59#define SOURCE_MASK 0xff00 60#define ADB_MASK 0xff 61#define ADB_SHIFT 0x8 62 63/* ADB address */ 64#define OFFSET_ADBDMA 0x00 65#define OFFSET_SRCIN 0x40 66#define OFFSET_SRCOUT 0x20 67#define OFFSET_MIXIN 0x50 68#define OFFSET_MIXOUT 0x30 69#define OFFSET_CODECIN 0x70 70#define OFFSET_CODECOUT 0x88 71#define OFFSET_SPORTIN 0x78 /* ch 0x13 */ 72#define OFFSET_SPORTOUT 0x90 73#define OFFSET_SPDIFOUT 0x92 /* ch 0x14 check this! */ 74#define OFFSET_EQIN 0xa0 75#define OFFSET_EQOUT 0x7e /* 2 routes on ch 0x11 */ 76#define OFFSET_XTALKOUT 0x66 /* crosstalk canceller (source) */ 77#define OFFSET_XTALKIN 0x96 /* crosstalk canceller (sink) */ 78#define OFFSET_A3DIN 0x70 /* ADB sink. */ 79#define OFFSET_A3DOUT 0xA6 /* ADB source. 2 routes per slice = 8 */ 80#define OFFSET_EFXIN 0x80 /* ADB sink. */ 81#define OFFSET_EFXOUT 0x68 /* ADB source. */ 82 83/* ADB route translate helper */ 84#define ADB_DMA(x) (x) 85#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) 86#define ADB_SRCIN(x) (x + OFFSET_SRCIN) 87#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) 88#define ADB_MIXIN(x) (x + OFFSET_MIXIN) 89#define ADB_CODECIN(x) (x + OFFSET_CODECIN) 90#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) 91#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) 92#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) 93#define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT) 94#define ADB_EQIN(x) (x + OFFSET_EQIN) 95#define ADB_EQOUT(x) (x + OFFSET_EQOUT) 96#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 0x10 A3D blocks */ 97#define ADB_A3DIN(x) (x + OFFSET_A3DIN) 98#define ADB_XTALKIN(x) (x + OFFSET_XTALKIN) 99#define ADB_XTALKOUT(x) (x + OFFSET_XTALKOUT) 100 101#define MIX_OUTL 0xe 102#define MIX_OUTR 0xf 103#define MIX_INL 0x1e 104#define MIX_INR 0x1f 105#define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */ 106#define MIX_DEFOGAIN 0x08 107 108/* MIXER */ 109#define VORTEX_MIXER_SR 0x21f00 110#define VORTEX_MIXER_CLIP 0x21f80 111#define VORTEX_MIXER_CHNBASE 0x21e40 112#define VORTEX_MIXER_RTBASE 0x21e00 113#define MIXER_RTBASE_SIZE 0x38 114#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */ 115#define VORTEX_MIX_SMP 0x21c00 /* AU8820: 0x9c00 */ 116 117/* MIX */ 118#define VORTEX_MIX_INVOL_A 0x21000 /* in? */ 119#define VORTEX_MIX_INVOL_B 0x20000 /* out? */ 120#define VORTEX_MIX_VOL_A 0x21800 121#define VORTEX_MIX_VOL_B 0x20800 122 123#define VOL_MIN 0x80 /* Input volume when muted. */ 124#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ 125 126/* SRC */ 127#define VORTEX_SRC_CHNBASE 0x26c40 128#define VORTEX_SRC_RTBASE 0x26c00 129#define VORTEX_SRCBLOCK_SR 0x26cc0 130#define VORTEX_SRC_SOURCE 0x26cc4 131#define VORTEX_SRC_SOURCESIZE 0x26cc8 132/* Params 133 0x26e00 : 1 U0 134 0x26e40 : 2 CR 135 0x26e80 : 3 U3 136 0x26ec0 : 4 DRIFT1 137 0x26f00 : 5 U1 138 0x26f40 : 6 DRIFT2 139 0x26f80 : 7 U2 : Target rate, direction 140*/ 141 142#define VORTEX_SRC_CONVRATIO 0x26e40 143#define VORTEX_SRC_DRIFT0 0x26e80 144#define VORTEX_SRC_DRIFT1 0x26ec0 145#define VORTEX_SRC_DRIFT2 0x26f40 146#define VORTEX_SRC_U0 0x26e00 147#define U0_SLOWLOCK 0x200 148#define VORTEX_SRC_U1 0x26f00 149#define VORTEX_SRC_U2 0x26f80 150#define VORTEX_SRC_DATA 0x26800 /* 0xc800 */ 151#define VORTEX_SRC_DATA0 0x26000 152 153/* FIFO */ 154#define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */ 155#define VORTEX_FIFO_WTCTRL 0x16000 156#define FIFO_RDONLY 0x00000001 157#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ 158#define FIFO_VALID 0x00000010 159#define FIFO_EMPTY 0x00000020 160#define FIFO_U0 0x00001000 /* Unknown. */ 161#define FIFO_U1 0x00010000 162#define FIFO_SIZE_BITS 5 163#define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20 164#define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */ 165//#define FIFO_MASK 0x1f /* at shift left 0xb */ 166//#define FIFO_SIZE 0x20 167#define FIFO_BITS 0x03880000 168#define VORTEX_FIFO_ADBDATA 0x14000 169#define VORTEX_FIFO_WTDATA 0x10000 170 171/* CODEC */ 172#define VORTEX_CODEC_CTRL 0x29184 173#define VORTEX_CODEC_EN 0x29190 174#define EN_CODEC0 0x00000300 175#define EN_AC98 0x00000c00 /* Modem AC98 slots. */ 176#define EN_CODEC1 0x00003000 177#define EN_CODEC (EN_CODEC0 | EN_CODEC1) 178#define EN_SPORT 0x00030000 179#define EN_SPDIF 0x000c0000 180 181#define VORTEX_CODEC_CHN 0x29080 182#define VORTEX_CODEC_IO 0x29188 183 184/* SPDIF */ 185#define VORTEX_SPDIF_FLAGS 0x2205c 186#define VORTEX_SPDIF_CFG0 0x291D0 187#define VORTEX_SPDIF_CFG1 0x291D4 188#define VORTEX_SPDIF_SMPRATE 0x29194 189 190/* Sample timer */ 191#define VORTEX_SMP_TIME 0x29198 192 193#define VORTEX_MODEM_CTRL 0x291ac 194 195/* IRQ */ 196#define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */ 197#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */ 198 199#define VORTEX_STAT 0x2a008 /* Status */ 200 201#define VORTEX_CTRL 0x2a00c 202#define CTRL_MIDI_EN 0x00000001 203#define CTRL_MIDI_PORT 0x00000060 204#define CTRL_GAME_EN 0x00000008 205#define CTRL_GAME_PORT 0x00000e00 206//#define CTRL_IRQ_ENABLE 0x01004000 207#define CTRL_IRQ_ENABLE 0x00004000 208 209/* write: Timer period config / read: TIMER IRQ ack. */ 210#define VORTEX_IRQ_STAT 0x2919c 211 212/* DMA */ 213#define VORTEX_ENGINE_CTRL 0x27ae8 214#define ENGINE_INIT 0x1380000 215 216/* MIDI *//* GAME. */ 217#define VORTEX_MIDI_DATA 0x28800 218#define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */ 219 220#define VORTEX_CTRL2 0x2880c 221#define CTRL2_GAME_ADCMODE 0x40 222#define VORTEX_GAME_LEGACY 0x28808 223#define VORTEX_GAME_AXIS 0x28810 224#define AXIS_SIZE 4 225#define AXIS_RANGE 0x1fff 226