1189765Sgabor// SPDX-License-Identifier: GPL-2.0
2189765Sgabor#include <dt-bindings/clock/ingenic,jz4740-cgu.h>
3189765Sgabor#include <dt-bindings/clock/ingenic,tcu.h>
4189765Sgabor
5189765Sgabor/ {
6189765Sgabor	#address-cells = <1>;
7189765Sgabor	#size-cells = <1>;
8189765Sgabor	compatible = "ingenic,jz4740";
9189765Sgabor
10189765Sgabor	cpus {
11189765Sgabor		#address-cells = <1>;
12189765Sgabor		#size-cells = <0>;
13189765Sgabor
14189765Sgabor		cpu0: cpu@0 {
15189765Sgabor			device_type = "cpu";
16189765Sgabor			compatible = "ingenic,xburst-mxu1.0";
17189765Sgabor			reg = <0>;
18189765Sgabor
19189765Sgabor			clocks = <&cgu JZ4740_CLK_CCLK>;
20189765Sgabor			clock-names = "cpu";
21189765Sgabor		};
22189765Sgabor	};
23189765Sgabor
24189765Sgabor	cpuintc: interrupt-controller {
25189765Sgabor		#address-cells = <0>;
26189765Sgabor		#interrupt-cells = <1>;
27189765Sgabor		interrupt-controller;
28189765Sgabor		compatible = "mti,cpu-interrupt-controller";
29189765Sgabor	};
30189765Sgabor
31189765Sgabor	intc: interrupt-controller@10001000 {
32189765Sgabor		compatible = "ingenic,jz4740-intc";
33189765Sgabor		reg = <0x10001000 0x14>;
34189765Sgabor
35189765Sgabor		interrupt-controller;
36189765Sgabor		#interrupt-cells = <1>;
37189765Sgabor
38189765Sgabor		interrupt-parent = <&cpuintc>;
39189765Sgabor		interrupts = <2>;
40189765Sgabor	};
41189765Sgabor
42189765Sgabor	ext: ext {
43189765Sgabor		compatible = "fixed-clock";
44189765Sgabor		#clock-cells = <0>;
45189765Sgabor	};
46189765Sgabor
47189765Sgabor	rtc: rtc {
48189765Sgabor		compatible = "fixed-clock";
49189765Sgabor		#clock-cells = <0>;
50189765Sgabor		clock-frequency = <32768>;
51189765Sgabor	};
52189765Sgabor
53189765Sgabor	cgu: jz4740-cgu@10000000 {
54189765Sgabor		compatible = "ingenic,jz4740-cgu";
55189765Sgabor		reg = <0x10000000 0x100>;
56189765Sgabor
57189765Sgabor		clocks = <&ext>, <&rtc>;
58189765Sgabor		clock-names = "ext", "rtc";
59189765Sgabor
60189765Sgabor		#clock-cells = <1>;
61189765Sgabor	};
62189765Sgabor
63189765Sgabor	tcu: timer@10002000 {
64189765Sgabor		compatible = "ingenic,jz4740-tcu", "simple-mfd";
65200077Sgabor		reg = <0x10002000 0x1000>;
66189765Sgabor		#address-cells = <1>;
67189765Sgabor		#size-cells = <1>;
68189765Sgabor		ranges = <0x0 0x10002000 0x1000>;
69189765Sgabor
70189765Sgabor		#clock-cells = <1>;
71189765Sgabor
72189765Sgabor		clocks = <&cgu JZ4740_CLK_RTC>,
73189765Sgabor			 <&cgu JZ4740_CLK_EXT>,
74189765Sgabor			 <&cgu JZ4740_CLK_PCLK>,
75189765Sgabor			 <&cgu JZ4740_CLK_TCU>;
76189765Sgabor		clock-names = "rtc", "ext", "pclk", "tcu";
77189765Sgabor
78189765Sgabor		interrupt-controller;
79189765Sgabor		#interrupt-cells = <1>;
80189765Sgabor
81189765Sgabor		interrupt-parent = <&intc>;
82189765Sgabor		interrupts = <23 22 21>;
83189765Sgabor
84189765Sgabor		watchdog: watchdog@0 {
85189765Sgabor			compatible = "ingenic,jz4740-watchdog";
86189765Sgabor			reg = <0x0 0xc>;
87189765Sgabor
88189765Sgabor			clocks = <&tcu TCU_CLK_WDT>;
89189765Sgabor			clock-names = "wdt";
90189765Sgabor		};
91200077Sgabor
92189765Sgabor		pwm: pwm@40 {
93189765Sgabor			compatible = "ingenic,jz4740-pwm";
94189765Sgabor			reg = <0x40 0x80>;
95189765Sgabor
96189765Sgabor			#pwm-cells = <3>;
97189765Sgabor
98189765Sgabor			clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
99189765Sgabor				 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
100189765Sgabor				 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
101189765Sgabor				 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
102189765Sgabor			clock-names = "timer0", "timer1", "timer2", "timer3",
103189765Sgabor				      "timer4", "timer5", "timer6", "timer7";
104189765Sgabor		};
105189765Sgabor	};
106189765Sgabor
107189765Sgabor	rtc_dev: rtc@10003000 {
108189765Sgabor		compatible = "ingenic,jz4740-rtc";
109189765Sgabor		reg = <0x10003000 0x40>;
110189765Sgabor
111189765Sgabor		interrupt-parent = <&intc>;
112189765Sgabor		interrupts = <15>;
113189765Sgabor
114189765Sgabor		clocks = <&cgu JZ4740_CLK_RTC>;
115189765Sgabor		clock-names = "rtc";
116189765Sgabor	};
117189765Sgabor
118189765Sgabor	pinctrl: pin-controller@10010000 {
119189765Sgabor		compatible = "ingenic,jz4740-pinctrl";
120189765Sgabor		reg = <0x10010000 0x400>;
121189765Sgabor
122189765Sgabor		#address-cells = <1>;
123189765Sgabor		#size-cells = <0>;
124189765Sgabor
125189765Sgabor		gpa: gpio@0 {
126189765Sgabor			compatible = "ingenic,jz4740-gpio";
127189765Sgabor			reg = <0>;
128189765Sgabor
129189765Sgabor			gpio-controller;
130189765Sgabor			gpio-ranges = <&pinctrl 0 0 32>;
131189765Sgabor			#gpio-cells = <2>;
132189765Sgabor
133189765Sgabor			interrupt-controller;
134189765Sgabor			#interrupt-cells = <2>;
135189765Sgabor
136189765Sgabor			interrupt-parent = <&intc>;
137189765Sgabor			interrupts = <28>;
138189765Sgabor		};
139189765Sgabor
140189765Sgabor		gpb: gpio@1 {
141189765Sgabor			compatible = "ingenic,jz4740-gpio";
142189765Sgabor			reg = <1>;
143189765Sgabor
144189765Sgabor			gpio-controller;
145189765Sgabor			gpio-ranges = <&pinctrl 0 32 32>;
146189765Sgabor			#gpio-cells = <2>;
147189765Sgabor
148189765Sgabor			interrupt-controller;
149189765Sgabor			#interrupt-cells = <2>;
150189765Sgabor
151189765Sgabor			interrupt-parent = <&intc>;
152189765Sgabor			interrupts = <27>;
153189765Sgabor		};
154189765Sgabor
155189765Sgabor		gpc: gpio@2 {
156189765Sgabor			compatible = "ingenic,jz4740-gpio";
157189765Sgabor			reg = <2>;
158189765Sgabor
159189765Sgabor			gpio-controller;
160189765Sgabor			gpio-ranges = <&pinctrl 0 64 32>;
161189765Sgabor			#gpio-cells = <2>;
162189765Sgabor
163189765Sgabor			interrupt-controller;
164189765Sgabor			#interrupt-cells = <2>;
165189765Sgabor
166189765Sgabor			interrupt-parent = <&intc>;
167189765Sgabor			interrupts = <26>;
168189765Sgabor		};
169189765Sgabor
170189765Sgabor		gpd: gpio@3 {
171189765Sgabor			compatible = "ingenic,jz4740-gpio";
172189765Sgabor			reg = <3>;
173189765Sgabor
174189765Sgabor			gpio-controller;
175189765Sgabor			gpio-ranges = <&pinctrl 0 96 32>;
176189765Sgabor			#gpio-cells = <2>;
177189765Sgabor
178189765Sgabor			interrupt-controller;
179200077Sgabor			#interrupt-cells = <2>;
180189765Sgabor
181189765Sgabor			interrupt-parent = <&intc>;
182189765Sgabor			interrupts = <25>;
183189765Sgabor		};
184200077Sgabor	};
185200077Sgabor
186200077Sgabor	aic: audio-controller@10020000 {
187200077Sgabor		compatible = "ingenic,jz4740-i2s";
188200077Sgabor		reg = <0x10020000 0x38>;
189200077Sgabor
190200077Sgabor		#sound-dai-cells = <0>;
191200077Sgabor
192200077Sgabor		interrupt-parent = <&intc>;
193200077Sgabor		interrupts = <18>;
194189765Sgabor
195189765Sgabor		clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
196189765Sgabor		clock-names = "aic", "i2s";
197189765Sgabor
198189765Sgabor		dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
199200077Sgabor		dma-names = "rx", "tx";
200189765Sgabor	};
201189765Sgabor
202189765Sgabor	codec: audio-codec@100200a4 {
203189765Sgabor		compatible = "ingenic,jz4740-codec";
204189765Sgabor		reg = <0x10020080 0x8>;
205200077Sgabor
206189765Sgabor		#sound-dai-cells = <0>;
207189765Sgabor
208189765Sgabor		clocks = <&cgu JZ4740_CLK_AIC>;
209189765Sgabor		clock-names = "aic";
210189765Sgabor	};
211189765Sgabor
212189765Sgabor	mmc: mmc@10021000 {
213189765Sgabor		compatible = "ingenic,jz4740-mmc";
214189765Sgabor		reg = <0x10021000 0x1000>;
215189765Sgabor
216189765Sgabor		clocks = <&cgu JZ4740_CLK_MMC>;
217189765Sgabor		clock-names = "mmc";
218189765Sgabor
219189765Sgabor		interrupt-parent = <&intc>;
220189765Sgabor		interrupts = <14>;
221189765Sgabor
222189765Sgabor		dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
223189765Sgabor		dma-names = "rx", "tx";
224189765Sgabor
225189765Sgabor		cap-sd-highspeed;
226189765Sgabor		cap-mmc-highspeed;
227189765Sgabor		cap-sdio-irq;
228189765Sgabor	};
229189765Sgabor
230189765Sgabor	uart0: serial@10030000 {
231189765Sgabor		compatible = "ingenic,jz4740-uart";
232189765Sgabor		reg = <0x10030000 0x100>;
233189765Sgabor
234189765Sgabor		interrupt-parent = <&intc>;
235189765Sgabor		interrupts = <9>;
236189765Sgabor
237189765Sgabor		clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
238189765Sgabor		clock-names = "baud", "module";
239189765Sgabor	};
240189765Sgabor
241189765Sgabor	uart1: serial@10031000 {
242189765Sgabor		compatible = "ingenic,jz4740-uart";
243189765Sgabor		reg = <0x10031000 0x100>;
244189765Sgabor
245189765Sgabor		interrupt-parent = <&intc>;
246189765Sgabor		interrupts = <8>;
247189765Sgabor
248189765Sgabor		clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
249189765Sgabor		clock-names = "baud", "module";
250189765Sgabor	};
251189765Sgabor
252189765Sgabor	adc: adc@10070000 {
253189765Sgabor		compatible = "ingenic,jz4740-adc";
254189765Sgabor		reg = <0x10070000 0x30>;
255189765Sgabor		#io-channel-cells = <1>;
256189765Sgabor
257189765Sgabor		clocks = <&cgu JZ4740_CLK_ADC>;
258189765Sgabor		clock-names = "adc";
259189765Sgabor
260200077Sgabor		interrupt-parent = <&intc>;
261200077Sgabor		interrupts = <12>;
262200077Sgabor	};
263200077Sgabor
264200077Sgabor	nemc: memory-controller@13010000 {
265200077Sgabor		compatible = "ingenic,jz4740-nemc";
266200077Sgabor		reg = <0x13010000 0x54>;
267200077Sgabor		#address-cells = <2>;
268200077Sgabor		#size-cells = <1>;
269200077Sgabor		ranges = <1 0 0x18000000 0x4000000>,
270200077Sgabor			 <2 0 0x14000000 0x4000000>,
271200077Sgabor			 <3 0 0x0c000000 0x4000000>,
272200077Sgabor			 <4 0 0x08000000 0x4000000>;
273200077Sgabor
274200077Sgabor		clocks = <&cgu JZ4740_CLK_MCLK>;
275200077Sgabor	};
276200077Sgabor
277200077Sgabor	ecc: ecc-controller@13010100 {
278200077Sgabor		compatible = "ingenic,jz4740-ecc";
279200077Sgabor		reg = <0x13010100 0x2C>;
280200077Sgabor
281200077Sgabor		clocks = <&cgu JZ4740_CLK_MCLK>;
282200077Sgabor	};
283200077Sgabor
284200077Sgabor	dmac: dma-controller@13020000 {
285200077Sgabor		compatible = "ingenic,jz4740-dma";
286200077Sgabor		reg = <0x13020000 0xbc>, <0x13020300 0x14>;
287200077Sgabor		#dma-cells = <2>;
288200077Sgabor
289200077Sgabor		interrupt-parent = <&intc>;
290200077Sgabor		interrupts = <20>;
291200077Sgabor
292200077Sgabor		clocks = <&cgu JZ4740_CLK_DMA>;
293200077Sgabor	};
294200077Sgabor
295200077Sgabor	uhc: usb@13030000 {
296		compatible = "ingenic,jz4740-ohci", "generic-ohci";
297		reg = <0x13030000 0x1000>;
298
299		clocks = <&cgu JZ4740_CLK_UHC>;
300		assigned-clocks = <&cgu JZ4740_CLK_UHC>;
301		assigned-clock-rates = <48000000>;
302
303		interrupt-parent = <&intc>;
304		interrupts = <3>;
305
306		status = "disabled";
307	};
308
309	udc: usb@13040000 {
310		compatible = "ingenic,jz4740-musb";
311		reg = <0x13040000 0x10000>;
312
313		interrupt-parent = <&intc>;
314		interrupts = <24>;
315		interrupt-names = "mc";
316
317		clocks = <&cgu JZ4740_CLK_UDC>;
318		clock-names = "udc";
319	};
320
321	lcd: lcd-controller@13050000 {
322		compatible = "ingenic,jz4740-lcd";
323		reg = <0x13050000 0x60>; /* LCDCMD1+4 */
324
325		interrupt-parent = <&intc>;
326		interrupts = <30>;
327
328		clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
329		clock-names = "lcd_pclk", "lcd";
330	};
331};
332