1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ 2/* 3 * Copyright (c) 2022 Collabora Ltd. 4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 5 */ 6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795 8#define _DT_BINDINGS_RESET_CONTROLLER_MT6795 9 10/* INFRACFG resets */ 11#define MT6795_INFRA_RST0_SCPSYS_RST 0 12#define MT6795_INFRA_RST0_PMIC_WRAP_RST 1 13#define MT6795_INFRA_RST1_MIPI_DSI_RST 2 14#define MT6795_INFRA_RST1_MIPI_CSI_RST 3 15#define MT6795_INFRA_RST1_MM_IOMMU_RST 4 16 17/* MMSYS resets */ 18#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 0 19#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 1 20#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 2 21#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 3 22#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 4 23#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 5 24#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 6 25#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 7 26#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 8 27#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 9 28#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 10 29#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 11 30#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 12 31#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 13 32 33/* PERICFG resets */ 34#define MT6795_PERI_NFI_SW_RST 0 35#define MT6795_PERI_THERM_SW_RST 1 36#define MT6795_PERI_MSDC1_SW_RST 2 37 38/* TOPRGU resets */ 39#define MT6795_TOPRGU_INFRA_SW_RST 0 40#define MT6795_TOPRGU_MM_SW_RST 1 41#define MT6795_TOPRGU_MFG_SW_RST 2 42#define MT6795_TOPRGU_VENC_SW_RST 3 43#define MT6795_TOPRGU_VDEC_SW_RST 4 44#define MT6795_TOPRGU_IMG_SW_RST 5 45#define MT6795_TOPRGU_DDRPHY_SW_RST 6 46#define MT6795_TOPRGU_MD_SW_RST 7 47#define MT6795_TOPRGU_INFRA_AO_SW_RST 8 48#define MT6795_TOPRGU_MD_LITE_SW_RST 9 49#define MT6795_TOPRGU_APMIXED_SW_RST 10 50#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 11 51#define MT6795_TOPRGU_SW_RST_NUM 12 52 53#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */ 54