1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Qualcomm SDX55 interconnect IDs 4 * 5 * Copyright (c) 2021, Linaro Ltd. 6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7 */ 8 9#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H 10#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H 11 12#define MASTER_LLCC 0 13#define SLAVE_EBI_CH0 1 14 15#define MASTER_TCU_0 0 16#define MASTER_SNOC_GC_MEM_NOC 1 17#define MASTER_AMPSS_M0 2 18#define SLAVE_LLCC 3 19#define SLAVE_MEM_NOC_SNOC 4 20#define SLAVE_MEM_NOC_PCIE_SNOC 5 21 22#define MASTER_AUDIO 0 23#define MASTER_BLSP_1 1 24#define MASTER_QDSS_BAM 2 25#define MASTER_QPIC 3 26#define MASTER_SNOC_CFG 4 27#define MASTER_SPMI_FETCHER 5 28#define MASTER_ANOC_SNOC 6 29#define MASTER_IPA 7 30#define MASTER_MEM_NOC_SNOC 8 31#define MASTER_MEM_NOC_PCIE_SNOC 9 32#define MASTER_CRYPTO_CORE_0 10 33#define MASTER_EMAC 11 34#define MASTER_IPA_PCIE 12 35#define MASTER_PCIE 13 36#define MASTER_QDSS_ETR 14 37#define MASTER_SDCC_1 15 38#define MASTER_USB3 16 39#define SLAVE_AOP 17 40#define SLAVE_AOSS 18 41#define SLAVE_APPSS 19 42#define SLAVE_AUDIO 20 43#define SLAVE_BLSP_1 21 44#define SLAVE_CLK_CTL 22 45#define SLAVE_CRYPTO_0_CFG 23 46#define SLAVE_CNOC_DDRSS 24 47#define SLAVE_ECC_CFG 25 48#define SLAVE_EMAC_CFG 26 49#define SLAVE_IMEM_CFG 27 50#define SLAVE_IPA_CFG 28 51#define SLAVE_CNOC_MSS 29 52#define SLAVE_PCIE_PARF 30 53#define SLAVE_PDM 31 54#define SLAVE_PRNG 32 55#define SLAVE_QDSS_CFG 33 56#define SLAVE_QPIC 34 57#define SLAVE_SDCC_1 35 58#define SLAVE_SNOC_CFG 36 59#define SLAVE_SPMI_FETCHER 37 60#define SLAVE_SPMI_VGI_COEX 38 61#define SLAVE_TCSR 39 62#define SLAVE_TLMM 40 63#define SLAVE_USB3 41 64#define SLAVE_USB3_PHY_CFG 42 65#define SLAVE_ANOC_SNOC 43 66#define SLAVE_SNOC_MEM_NOC_GC 44 67#define SLAVE_OCIMEM 45 68#define SLAVE_SERVICE_SNOC 46 69#define SLAVE_PCIE_0 47 70#define SLAVE_QDSS_STM 48 71#define SLAVE_TCU 49 72 73 74#endif 75