115423Swpaul/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 215423Swpaul/* 315423Swpaul * Copyright (c) 2021, The Linux Foundation. All rights reserved. 415423Swpaul * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 515423Swpaul */ 615423Swpaul 715423Swpaul#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H 815423Swpaul#define _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H 915423Swpaul 1015423Swpaul/* GCC clocks */ 1115423Swpaul#define GPLL0 0 1215423Swpaul#define GPLL0_OUT_EVEN 1 1315423Swpaul#define GPLL0_OUT_ODD 2 1415423Swpaul#define GPLL6 3 1515423Swpaul#define GPLL6_OUT_EVEN 4 1615423Swpaul#define GPLL7 5 1715423Swpaul#define GCC_AGGRE_CNOC_PERIPH_CENTER_AHB_CLK 6 1815423Swpaul#define GCC_AGGRE_NOC_CENTER_AHB_CLK 7 1915423Swpaul#define GCC_AGGRE_NOC_PCIE_SF_AXI_CLK 8 2015423Swpaul#define GCC_AGGRE_NOC_PCIE_TBU_CLK 9 2115423Swpaul#define GCC_AGGRE_NOC_WLAN_AXI_CLK 10 2215423Swpaul#define GCC_AGGRE_UFS_PHY_AXI_CLK 11 2315423Swpaul#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 2415423Swpaul#define GCC_BOOT_ROM_AHB_CLK 13 2515423Swpaul#define GCC_CAMERA_AHB_CLK 14 2615423Swpaul#define GCC_CAMERA_AXI_CLK 15 2715423Swpaul#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 16 2815423Swpaul#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 17 2915423Swpaul#define GCC_CAMERA_XO_CLK 18 3015423Swpaul#define GCC_CE1_AHB_CLK 19 3115423Swpaul#define GCC_CE1_AXI_CLK 20 3215423Swpaul#define GCC_CE1_CLK 21 33114601Sobrien#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 22 34114601Sobrien#define GCC_CPUSS_AHB_CLK 23 3530777Scharnier#define GCC_CPUSS_AHB_CLK_SRC 24 3630777Scharnier#define GCC_CPUSS_AHB_DIV_CLK_SRC 25 3715423Swpaul#define GCC_CPUSS_GNOC_CLK 26 3815423Swpaul#define GCC_CPUSS_RBCPR_CLK 27 39228722Sdim#define GCC_DDRSS_GPU_AXI_CLK 28 4030777Scharnier#define GCC_DISP_AHB_CLK 29 4115423Swpaul#define GCC_DISP_AXI_CLK 30 4230777Scharnier#define GCC_DISP_CC_SLEEP_CLK 31 4330777Scharnier#define GCC_DISP_CC_XO_CLK 32 4415423Swpaul#define GCC_DISP_GPLL0_CLK 33 4515423Swpaul#define GCC_DISP_THROTTLE_AXI_CLK 34 4615423Swpaul#define GCC_DISP_XO_CLK 35 4730777Scharnier#define GCC_GP1_CLK 36 4830777Scharnier#define GCC_GP1_CLK_SRC 37 4930777Scharnier#define GCC_GP2_CLK 38 5015423Swpaul#define GCC_GP2_CLK_SRC 39 5116133Swpaul#define GCC_GP3_CLK 40 5215423Swpaul#define GCC_GP3_CLK_SRC 41 5315423Swpaul#define GCC_GPU_CFG_AHB_CLK 42 5415423Swpaul#define GCC_GPU_GPLL0_CLK 43 5515423Swpaul#define GCC_GPU_GPLL0_DIV_CLK 44 5615423Swpaul#define GCC_GPU_MEMNOC_GFX_CLK 45 5790298Sdes#define GCC_GPU_SNOC_DVM_GFX_CLK 46 5890298Sdes#define GCC_NPU_AXI_CLK 47 5915423Swpaul#define GCC_NPU_BWMON_AXI_CLK 48 6030777Scharnier#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 49 6130777Scharnier#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 50 6230777Scharnier#define GCC_NPU_CFG_AHB_CLK 51 6350159Swpaul#define GCC_NPU_DMA_CLK 52 6430777Scharnier#define GCC_NPU_GPLL0_CLK 53 6515423Swpaul#define GCC_NPU_GPLL0_DIV_CLK 54 6615423Swpaul#define GCC_PCIE_0_AUX_CLK 55 6715423Swpaul#define GCC_PCIE_0_AUX_CLK_SRC 56 6815423Swpaul#define GCC_PCIE_0_CFG_AHB_CLK 57 6915423Swpaul#define GCC_PCIE_0_MSTR_AXI_CLK 58 7090298Sdes#define GCC_PCIE_0_PIPE_CLK 59 7190298Sdes#define GCC_PCIE_0_SLV_AXI_CLK 60 7215423Swpaul#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 61 7315423Swpaul#define GCC_PCIE_PHY_RCHNG_CLK 62 7415423Swpaul#define GCC_PCIE_PHY_RCHNG_CLK_SRC 63 7515423Swpaul#define GCC_PDM2_CLK 64 7615423Swpaul#define GCC_PDM2_CLK_SRC 65 7715423Swpaul#define GCC_PDM_AHB_CLK 66 7890298Sdes#define GCC_PDM_XO4_CLK 67 7990298Sdes#define GCC_PRNG_AHB_CLK 68 8015423Swpaul#define GCC_QUPV3_WRAP0_CORE_2X_CLK 69 8115423Swpaul#define GCC_QUPV3_WRAP0_CORE_CLK 70 8215423Swpaul#define GCC_QUPV3_WRAP0_S0_CLK 71 8315423Swpaul#define GCC_QUPV3_WRAP0_S0_CLK_SRC 72 8415423Swpaul#define GCC_QUPV3_WRAP0_S1_CLK 73 8515423Swpaul#define GCC_QUPV3_WRAP0_S1_CLK_SRC 74 8615423Swpaul#define GCC_QUPV3_WRAP0_S2_CLK 75 8715423Swpaul#define GCC_QUPV3_WRAP0_S2_CLK_SRC 76 8815423Swpaul#define GCC_QUPV3_WRAP0_S3_CLK 77 8915423Swpaul#define GCC_QUPV3_WRAP0_S3_CLK_SRC 78 9090297Sdes#define GCC_QUPV3_WRAP0_S4_CLK 79 91364084Sdim#define GCC_QUPV3_WRAP0_S4_CLK_SRC 80 92364084Sdim#define GCC_QUPV3_WRAP0_S5_CLK 81 9315423Swpaul#define GCC_QUPV3_WRAP0_S5_CLK_SRC 82 9415423Swpaul#define GCC_QUPV3_WRAP1_CORE_2X_CLK 83 9515423Swpaul#define GCC_QUPV3_WRAP1_CORE_CLK 84 9615423Swpaul#define GCC_QUPV3_WRAP1_S0_CLK 85 9715423Swpaul#define GCC_QUPV3_WRAP1_S0_CLK_SRC 86 9890298Sdes#define GCC_QUPV3_WRAP1_S1_CLK 87 9990298Sdes#define GCC_QUPV3_WRAP1_S1_CLK_SRC 88 10015423Swpaul#define GCC_QUPV3_WRAP1_S2_CLK 89 10115423Swpaul#define GCC_QUPV3_WRAP1_S2_CLK_SRC 90 10215423Swpaul#define GCC_QUPV3_WRAP1_S3_CLK 91 10315423Swpaul#define GCC_QUPV3_WRAP1_S3_CLK_SRC 92 10450159Swpaul#define GCC_QUPV3_WRAP1_S4_CLK 93 10515423Swpaul#define GCC_QUPV3_WRAP1_S4_CLK_SRC 94 10615423Swpaul#define GCC_QUPV3_WRAP1_S5_CLK 95 10715423Swpaul#define GCC_QUPV3_WRAP1_S5_CLK_SRC 96 10815423Swpaul#define GCC_QUPV3_WRAP_0_M_AHB_CLK 97 10915423Swpaul#define GCC_QUPV3_WRAP_0_S_AHB_CLK 98 11015423Swpaul#define GCC_QUPV3_WRAP_1_M_AHB_CLK 99 11119155Swpaul#define GCC_QUPV3_WRAP_1_S_AHB_CLK 100 11219155Swpaul#define GCC_SDCC1_AHB_CLK 101 11315423Swpaul#define GCC_SDCC1_APPS_CLK 102 11415423Swpaul#define GCC_SDCC1_APPS_CLK_SRC 103 11515423Swpaul#define GCC_SDCC1_ICE_CORE_CLK 104 11615423Swpaul#define GCC_SDCC1_ICE_CORE_CLK_SRC 105 11715423Swpaul#define GCC_SDCC2_AHB_CLK 106 11815423Swpaul#define GCC_SDCC2_APPS_CLK 107 11915423Swpaul#define GCC_SDCC2_APPS_CLK_SRC 108 12050746Ssheldonh#define GCC_SYS_NOC_CPUSS_AHB_CLK 109 12190297Sdes#define GCC_UFS_MEM_CLKREF_CLK 110 12250159Swpaul#define GCC_UFS_PHY_AHB_CLK 111 12350159Swpaul#define GCC_UFS_PHY_AXI_CLK 112 12450159Swpaul#define GCC_UFS_PHY_AXI_CLK_SRC 113 12515423Swpaul#define GCC_UFS_PHY_ICE_CORE_CLK 114 12615423Swpaul#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 115 12715423Swpaul#define GCC_UFS_PHY_PHY_AUX_CLK 116 12815423Swpaul#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 117 12915423Swpaul#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 118 13015423Swpaul#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 119 13119155Swpaul#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120 13219155Swpaul#define GCC_UFS_PHY_UNIPRO_CORE_CLK 121 13319155Swpaul#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 122 13419155Swpaul#define GCC_USB30_PRIM_MASTER_CLK 123 13519155Swpaul#define GCC_USB30_PRIM_MASTER_CLK_SRC 124 13619155Swpaul#define GCC_USB30_PRIM_MOCK_UTMI_CLK 125 13715423Swpaul#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 126 13815423Swpaul#define GCC_USB30_PRIM_MOCK_UTMI_DIV_CLK_SRC 127 13915423Swpaul#define GCC_USB3_PRIM_CLKREF_CLK 128 14015423Swpaul#define GCC_USB30_PRIM_SLEEP_CLK 129 14115423Swpaul#define GCC_USB3_PRIM_PHY_AUX_CLK 130 14215423Swpaul#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 131 14315423Swpaul#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 132 14415423Swpaul#define GCC_USB3_PRIM_PHY_PIPE_CLK 133 14515423Swpaul#define GCC_VIDEO_AHB_CLK 134 14615423Swpaul#define GCC_VIDEO_AXI_CLK 135 14715423Swpaul#define GCC_VIDEO_THROTTLE_AXI_CLK 136 14815423Swpaul#define GCC_VIDEO_XO_CLK 137 14915423Swpaul#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 138 15015423Swpaul#define GCC_UFS_PHY_AXI_HW_CTL_CLK 139 15115423Swpaul#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 140 15215423Swpaul#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 141 15315423Swpaul#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 142 15415423Swpaul#define GCC_RX5_PCIE_CLKREF_CLK 143 15515423Swpaul#define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC 144 15615423Swpaul#define GCC_NPU_PLL0_MAIN_DIV_CLK_SRC 145 15715423Swpaul 15815423Swpaul/* GCC resets */ 15915423Swpaul#define GCC_QUSB2PHY_PRIM_BCR 0 16015423Swpaul#define GCC_QUSB2PHY_SEC_BCR 1 16115423Swpaul#define GCC_SDCC1_BCR 2 16215423Swpaul#define GCC_SDCC2_BCR 3 16315423Swpaul#define GCC_UFS_PHY_BCR 4 16415423Swpaul#define GCC_USB30_PRIM_BCR 5 16515423Swpaul#define GCC_PCIE_0_BCR 6 16615423Swpaul#define GCC_PCIE_0_PHY_BCR 7 16715423Swpaul#define GCC_QUPV3_WRAPPER_0_BCR 8 16815423Swpaul#define GCC_QUPV3_WRAPPER_1_BCR 9 16915423Swpaul#define GCC_USB3_PHY_PRIM_BCR 10 17015423Swpaul#define GCC_USB3_DP_PHY_PRIM_BCR 11 17115423Swpaul 17215423Swpaul/* GCC GDSCs */ 17315423Swpaul#define USB30_PRIM_GDSC 0 17415423Swpaul#define UFS_PHY_GDSC 1 17515423Swpaul#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 17615423Swpaul#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 3 17715423Swpaul 17815423Swpaul#endif 17915423Swpaul