1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the AM62P5-SK 4 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Schematics: https://www.ti.com/lit/zip/sprr487 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/net/ti-dp83867.h> 14#include "k3-am62p5.dtsi" 15 16/ { 17 compatible = "ti,am62p5-sk", "ti,am62p5"; 18 model = "Texas Instruments AM62P5 SK"; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 mmc0 = &sdhci0; 25 mmc1 = &sdhci1; 26 mmc2 = &sdhci2; 27 spi0 = &ospi0; 28 ethernet0 = &cpsw_port1; 29 ethernet1 = &cpsw_port2; 30 }; 31 32 chosen { 33 stdout-path = &main_uart0; 34 }; 35 36 memory@80000000 { 37 /* 8G RAM */ 38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 39 <0x00000008 0x80000000 0x00000001 0x80000000>; 40 device_type = "memory"; 41 bootph-pre-ram; 42 }; 43 44 reserved-memory { 45 #address-cells = <2>; 46 #size-cells = <2>; 47 ranges; 48 49 secure_tfa_ddr: tfa@9e780000 { 50 reg = <0x00 0x9e780000 0x00 0x80000>; 51 no-map; 52 }; 53 54 secure_ddr: optee@9e800000 { 55 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 56 no-map; 57 }; 58 59 wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0x9c900000 0x00 0x01e00000>; 62 no-map; 63 }; 64 }; 65 66 vmain_pd: regulator-0 { 67 /* TPS65988 PD CONTROLLER OUTPUT */ 68 compatible = "regulator-fixed"; 69 regulator-name = "vmain_pd"; 70 regulator-min-microvolt = <5000000>; 71 regulator-max-microvolt = <5000000>; 72 regulator-always-on; 73 regulator-boot-on; 74 bootph-all; 75 }; 76 77 vcc_5v0: regulator-1 { 78 /* Output of TPS630702RNMR */ 79 compatible = "regulator-fixed"; 80 regulator-name = "vcc_5v0"; 81 regulator-min-microvolt = <5000000>; 82 regulator-max-microvolt = <5000000>; 83 vin-supply = <&vmain_pd>; 84 regulator-always-on; 85 regulator-boot-on; 86 bootph-all; 87 }; 88 89 vdd_mmc1: regulator-2 { 90 /* TPS22918DBVR */ 91 compatible = "regulator-fixed"; 92 regulator-name = "vdd_mmc1"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 regulator-boot-on; 96 enable-active-high; 97 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 98 bootph-all; 99 }; 100 101 vddshv_sdio: regulator-3 { 102 compatible = "regulator-gpio"; 103 regulator-name = "vddshv_sdio"; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&vddshv_sdio_pins_default>; 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <3300000>; 108 regulator-boot-on; 109 gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; 110 states = <1800000 0x0>, 111 <3300000 0x1>; 112 bootph-all; 113 }; 114 115 leds { 116 compatible = "gpio-leds"; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&usr_led_pins_default>; 119 120 led-0 { 121 label = "am62-sk:green:heartbeat"; 122 gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; 123 linux,default-trigger = "heartbeat"; 124 function = LED_FUNCTION_HEARTBEAT; 125 default-state = "off"; 126 }; 127 }; 128 129 tlv320_mclk: clk-0 { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 clock-frequency = <12288000>; 133 }; 134 135 codec_audio: sound { 136 compatible = "simple-audio-card"; 137 simple-audio-card,name = "AM62x-SKEVM"; 138 simple-audio-card,widgets = 139 "Headphone", "Headphone Jack", 140 "Line", "Line In", 141 "Microphone", "Microphone Jack"; 142 simple-audio-card,routing = 143 "Headphone Jack", "HPLOUT", 144 "Headphone Jack", "HPROUT", 145 "LINE1L", "Line In", 146 "LINE1R", "Line In", 147 "MIC3R", "Microphone Jack", 148 "Microphone Jack", "Mic Bias"; 149 simple-audio-card,format = "dsp_b"; 150 simple-audio-card,bitclock-master = <&sound_master>; 151 simple-audio-card,frame-master = <&sound_master>; 152 simple-audio-card,bitclock-inversion; 153 154 simple-audio-card,cpu { 155 sound-dai = <&mcasp1>; 156 }; 157 158 sound_master: simple-audio-card,codec { 159 sound-dai = <&tlv320aic3106>; 160 clocks = <&tlv320_mclk>; 161 }; 162 }; 163}; 164 165&main_gpio0 { 166 bootph-all; 167}; 168 169&main_gpio1 { 170 bootph-all; 171}; 172 173&main_pmx0 { 174 bootph-all; 175 176 main_i2c0_pins_default: main-i2c0-default-pins { 177 pinctrl-single,pins = < 178 AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ 179 AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ 180 >; 181 }; 182 183 main_i2c1_pins_default: main-i2c1-default-pins { 184 pinctrl-single,pins = < 185 AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ 186 AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ 187 >; 188 bootph-all; 189 }; 190 191 main_i2c2_pins_default: main-i2c2-default-pins { 192 pinctrl-single,pins = < 193 AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */ 194 AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */ 195 >; 196 }; 197 198 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { 199 pinctrl-single,pins = < 200 AM62PX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C22) UART0_RTSn.GPIO1_23 */ 201 >; 202 }; 203 204 main_mcasp1_pins_default: main-mcasp1-default-pins { 205 pinctrl-single,pins = < 206 AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ 207 AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ 208 AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ 209 AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */ 210 >; 211 }; 212 213 main_mdio1_pins_default: main-mdio1-default-pins { 214 pinctrl-single,pins = < 215 AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ 216 AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ 217 >; 218 }; 219 220 main_mmc1_pins_default: main-mmc1-default-pins { 221 pinctrl-single,pins = < 222 AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ 223 AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ 224 AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ 225 AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */ 226 AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */ 227 AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ 228 AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ 229 >; 230 bootph-all; 231 }; 232 233 main_mmc2_pins_default: main-mmc2-default-pins { 234 pinctrl-single,pins = < 235 AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ 236 AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ 237 AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ 238 AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ 239 AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ 240 AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ 241 AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */ 242 >; 243 bootph-all; 244 }; 245 246 main_rgmii1_pins_default: main-rgmii1-default-pins { 247 pinctrl-single,pins = < 248 AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ 249 AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ 250 AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ 251 AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ 252 AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ 253 AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ 254 AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ 255 AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ 256 AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ 257 AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ 258 AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ 259 AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ 260 >; 261 bootph-all; 262 }; 263 264 main_rgmii2_pins_default: main-rgmii2-default-pins { 265 pinctrl-single,pins = < 266 AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ 267 AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ 268 AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ 269 AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ 270 AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ 271 AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ 272 AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ 273 AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ 274 AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ 275 AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ 276 AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */ 277 AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ 278 >; 279 bootph-all; 280 }; 281 282 main_uart0_pins_default: main-uart0-default-pins { 283 pinctrl-single,pins = < 284 AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ 285 AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ 286 >; 287 bootph-all; 288 }; 289 290 main_uart1_pins_default: main-uart1-default-pins { 291 pinctrl-single,pins = < 292 AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ 293 AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */ 294 AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */ 295 AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ 296 >; 297 bootph-all; 298 }; 299 300 main_wlirq_pins_default: main-wlirq-default-pins { 301 pinctrl-single,pins = < 302 AM62PX_IOPAD(0x0128, PIN_INPUT, 7) /* (K25) MMC2_SDWP.GPIO0_72 */ 303 >; 304 }; 305 306 ospi0_pins_default: ospi0-default-pins { 307 pinctrl-single,pins = < 308 AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ 309 AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ 310 AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ 311 AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ 312 AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ 313 AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ 314 AM62PX_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */ 315 AM62PX_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */ 316 AM62PX_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */ 317 AM62PX_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */ 318 AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ 319 >; 320 bootph-all; 321 }; 322 323 usr_led_pins_default: usr-led-default-pins { 324 pinctrl-single,pins = < 325 AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */ 326 >; 327 }; 328 329 vddshv_sdio_pins_default: vddshvr-sdio-default-pins { 330 pinctrl-single,pins = < 331 AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */ 332 >; 333 bootph-all; 334 }; 335 336 wlan_en_pins_default: wlan-en-default-pins { 337 pinctrl-single,pins = < 338 AM62PX_IOPAD(0x0124, PIN_INPUT, 7) /* (J25) MMC2_SDCD.GPIO0_71 */ 339 >; 340 }; 341}; 342 343&main_i2c1 { 344 status = "okay"; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&main_i2c1_pins_default>; 347 clock-frequency = <100000>; 348 bootph-all; 349 350 tlv320aic3106: audio-codec@1b { 351 #sound-dai-cells = <0>; 352 compatible = "ti,tlv320aic3106"; 353 reg = <0x1b>; 354 ai3x-micbias-vg = <1>; /* 2.0V */ 355 }; 356 357 exp1: gpio@22 { 358 compatible = "ti,tca6424"; 359 reg = <0x22>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 gpio-line-names = "OLDI_INT#", "x8_NAND_DETECT", 363 "UART1_FET_SEL", "MMC1_SD_EN", 364 "VPP_EN", "EXP_PS_3V3_EN", 365 "UART1_FET_BUF_EN", "EXP_HAT_DETECT", 366 "DSI_GPIO0", "DSI_GPIO1", 367 "OLDI_EDID", "BT_UART_WAKE_SOC_3V3", 368 "USB_TYPEA_OC_INDICATION", "CSI_GPIO0", 369 "CSI_GPIO1", "WLAN_ALERTn", 370 "HDMI_INTn", "TEST_GPIO2", 371 "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", 372 "MCASP1_FET_SEL", "DSI_EDID", 373 "PD_I2C_IRQ", "IO_EXP_TEST_LED"; 374 375 interrupt-parent = <&main_gpio1>; 376 interrupts = <23 IRQ_TYPE_EDGE_FALLING>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 380 pinctrl-names = "default"; 381 pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; 382 bootph-all; 383 }; 384 385 exp2: gpio@23 { 386 compatible = "ti,tca6424"; 387 reg = <0x23>; 388 gpio-controller; 389 #gpio-cells = <2>; 390 gpio-line-names = "BT_EN_SOC", "EXP_PS_5V0_EN", 391 "", "", 392 "", "", 393 "", "", 394 "WL_LT_EN", "", 395 "TP3", "TP6", 396 "TP4", "TP7", 397 "TP5", "TP8", 398 "SoC_I2C2_MCAN_SEL", "GPIO_HDMI_RSTn", 399 "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 400 "GPIO_OLDI_RSTn", "GPIO_AUD_RSTn", 401 "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; 402 }; 403}; 404 405&main_i2c2 { 406 status = "okay"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&main_i2c2_pins_default>; 409 clock-frequency = <400000>; 410}; 411 412&sdhci0 { 413 status = "okay"; 414 ti,driver-strength-ohm = <50>; 415 disable-wp; 416 bootph-all; 417}; 418 419&sdhci1 { 420 /* SD/MMC */ 421 status = "okay"; 422 vmmc-supply = <&vdd_mmc1>; 423 vqmmc-supply = <&vddshv_sdio>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&main_mmc1_pins_default>; 426 disable-wp; 427 bootph-all; 428}; 429 430&cpsw3g { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&main_rgmii1_pins_default>, 433 <&main_rgmii2_pins_default>; 434}; 435 436&cpsw_port1 { 437 phy-mode = "rgmii-rxid"; 438 phy-handle = <&cpsw3g_phy0>; 439}; 440 441&cpsw_port2 { 442 phy-mode = "rgmii-rxid"; 443 phy-handle = <&cpsw3g_phy1>; 444}; 445 446&cpsw3g_mdio { 447 pinctrl-names = "default"; 448 pinctrl-0 = <&main_mdio1_pins_default>; 449 status = "okay"; 450 451 cpsw3g_phy0: ethernet-phy@0 { 452 reg = <0>; 453 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 454 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 455 ti,min-output-impedance; 456 }; 457 458 cpsw3g_phy1: ethernet-phy@1 { 459 reg = <1>; 460 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 461 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 462 ti,min-output-impedance; 463 }; 464}; 465 466&mcasp1 { 467 status = "okay"; 468 #sound-dai-cells = <0>; 469 470 pinctrl-names = "default"; 471 pinctrl-0 = <&main_mcasp1_pins_default>; 472 473 op-mode = <0>; /* MCASP_IIS_MODE */ 474 tdm-slots = <2>; 475 476 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 477 1 0 2 0 478 0 0 0 0 479 0 0 0 0 480 0 0 0 0 481 >; 482 tx-num-evt = <32>; 483 rx-num-evt = <32>; 484}; 485 486&fss { 487 bootph-all; 488}; 489 490&ospi0 { 491 status = "okay"; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&ospi0_pins_default>; 494 bootph-all; 495 496 flash@0{ 497 compatible = "jedec,spi-nor"; 498 reg = <0x0>; 499 spi-tx-bus-width = <8>; 500 spi-rx-bus-width = <8>; 501 spi-max-frequency = <25000000>; 502 cdns,tshsl-ns = <60>; 503 cdns,tsd2d-ns = <60>; 504 cdns,tchsh-ns = <60>; 505 cdns,tslch-ns = <60>; 506 cdns,read-delay = <4>; 507 bootph-all; 508 509 partitions { 510 compatible = "fixed-partitions"; 511 #address-cells = <1>; 512 #size-cells = <1>; 513 bootph-all; 514 515 partition@0 { 516 label = "ospi.tiboot3"; 517 reg = <0x00 0x80000>; 518 }; 519 520 partition@80000 { 521 label = "ospi.tispl"; 522 reg = <0x80000 0x200000>; 523 }; 524 525 partition@280000 { 526 label = "ospi.u-boot"; 527 reg = <0x280000 0x400000>; 528 }; 529 530 partition@680000 { 531 label = "ospi.env"; 532 reg = <0x680000 0x40000>; 533 }; 534 535 partition@6c0000 { 536 label = "ospi.env.backup"; 537 reg = <0x6c0000 0x40000>; 538 }; 539 540 partition@800000 { 541 label = "ospi.rootfs"; 542 reg = <0x800000 0x37c0000>; 543 }; 544 545 partition@3fc0000 { 546 label = "ospi.phypattern"; 547 reg = <0x3fc0000 0x40000>; 548 bootph-all; 549 }; 550 }; 551 }; 552}; 553 554&mailbox0_cluster0 { 555 mbox_r5_0: mbox-r5-0 { 556 ti,mbox-rx = <0 0 0>; 557 ti,mbox-tx = <1 0 0>; 558 }; 559}; 560 561&mailbox0_cluster1 { 562 mbox_mcu_r5_0: mbox-mcu-r5-0 { 563 ti,mbox-rx = <0 0 0>; 564 ti,mbox-tx = <1 0 0>; 565 }; 566}; 567 568&main_uart0 { 569 pinctrl-names = "default"; 570 pinctrl-0 = <&main_uart0_pins_default>; 571 status = "okay"; 572 bootph-all; 573}; 574 575&main_uart1 { 576 pinctrl-names = "default"; 577 pinctrl-0 = <&main_uart1_pins_default>; 578 /* Main UART1 is used by TIFS firmware */ 579 status = "reserved"; 580 bootph-all; 581}; 582 583&mcu_pmx0 { 584 bootph-all; 585 586 wkup_uart0_pins_default: wkup-uart0-default-pins { 587 pinctrl-single,pins = < 588 AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ 589 AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ 590 AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ 591 AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ 592 >; 593 bootph-all; 594 }; 595}; 596 597&wkup_uart0 { 598 /* WKUP UART0 is used by DM firmware */ 599 pinctrl-names = "default"; 600 pinctrl-0 = <&wkup_uart0_pins_default>; 601 status = "reserved"; 602 bootph-all; 603}; 604 605/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ 606&mcu_gpio0 { 607 status = "reserved"; 608}; 609 610&mcu_gpio_intr { 611 status = "reserved"; 612}; 613