1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Device Tree Source for AM62P SoC Family
4 *
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/soc/ti,sci_pm_domain.h>
12
13#include "k3-pinctrl.h"
14
15/ {
16	model = "Texas Instruments K3 AM62P5 SoC";
17	compatible = "ti,am62p5";
18	interrupt-parent = <&gic500>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	firmware {
23		optee {
24			compatible = "linaro,optee-tz";
25			method = "smc";
26		};
27
28		psci: psci {
29			compatible = "arm,psci-1.0";
30			method = "smc";
31		};
32	};
33
34	a53_timer0: timer-cl0-cpu0 {
35		compatible = "arm,armv8-timer";
36		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
37			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
38			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
39			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
40	};
41
42	pmu: pmu {
43		compatible = "arm,cortex-a53-pmu";
44		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
45	};
46
47	cbass_main: bus@f0000 {
48		compatible = "simple-bus";
49		#address-cells = <2>;
50		#size-cells = <2>;
51		bootph-all;
52
53		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
63			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
64			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
65			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
66			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
67			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
68			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
69			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
70			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
71			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
72			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
73			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
74			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
75			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
76			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
77			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
78			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
79
80			 /* MCU Domain Range */
81			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
82			 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
83			 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
84			 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
85			 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
86
87			 /* Wakeup Domain Range */
88			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
89			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
90			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
91			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
92			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
93
94		cbass_mcu: bus@4000000 {
95			compatible = "simple-bus";
96			#address-cells = <2>;
97			#size-cells = <2>;
98			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
99				 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
100				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
101				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
102				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
103			bootph-all;
104		};
105
106		cbass_wakeup: bus@b00000 {
107			compatible = "simple-bus";
108			#address-cells = <2>;
109			#size-cells = <2>;
110			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
111				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
112				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
113				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
114				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
115			bootph-all;
116		};
117	};
118
119	#include "k3-am62p-thermal.dtsi"
120};
121
122/* Now include peripherals for each bus segment */
123#include "k3-am62p-main.dtsi"
124#include "k3-am62p-mcu.dtsi"
125#include "k3-am62p-wakeup.dtsi"
126