1139778Simp// SPDX-License-Identifier: GPL-2.0-only OR MIT 2109471Sphk/* 313041Sasami * Device Tree Source for AM62 SoC Family 4109471Sphk * 5109471Sphk * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 613041Sasami */ 7109471Sphk 813041Sasami#include <dt-bindings/gpio/gpio.h> 9109471Sphk#include <dt-bindings/interrupt-controller/irq.h> 10109471Sphk#include <dt-bindings/interrupt-controller/arm-gic.h> 11109471Sphk#include <dt-bindings/soc/ti,sci_pm_domain.h> 12109471Sphk 1313041Sasami#include "k3-pinctrl.h" 1413041Sasami 1513041Sasami/ { 1613041Sasami model = "Texas Instruments K3 AM625 SoC"; 1713041Sasami compatible = "ti,am625"; 1813041Sasami interrupt-parent = <&gic500>; 1913041Sasami #address-cells = <2>; 2013041Sasami #size-cells = <2>; 2113041Sasami 2213041Sasami chosen { }; 2313041Sasami 2413041Sasami firmware { 25109471Sphk optee { 2613041Sasami compatible = "linaro,optee-tz"; 2713041Sasami method = "smc"; 2813041Sasami }; 2913041Sasami 3013041Sasami psci: psci { 3113041Sasami compatible = "arm,psci-1.0"; 3213041Sasami method = "smc"; 3313041Sasami }; 3413041Sasami }; 3513041Sasami 3613041Sasami a53_timer0: timer-cl0-cpu0 { 3713041Sasami compatible = "arm,armv8-timer"; 3813041Sasami interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 3913041Sasami <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 4013041Sasami <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 4113041Sasami <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 4213041Sasami }; 4313041Sasami 4413041Sasami pmu: pmu { 4513041Sasami compatible = "arm,cortex-a53-pmu"; 46109471Sphk interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 47109471Sphk }; 48109471Sphk 49109471Sphk cbass_main: bus@f0000 { 5013041Sasami bootph-all; 5113041Sasami compatible = "simple-bus"; 52116196Sobrien #address-cells = <2>; 53116196Sobrien #size-cells = <2>; 54116196Sobrien 5513041Sasami ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 5613041Sasami <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 5714730Sasami <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 5843076Speter <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 5960041Sphk <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 6013041Sasami <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 61223921Sae <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 62115729Sphk <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 6313041Sasami <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 64115731Sphk <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ 65115849Sphk <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 66115849Sphk <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 67115849Sphk <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ 68115731Sphk <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 69115849Sphk <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 70115849Sphk <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ 71115849Sphk <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 72115731Sphk <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 73115849Sphk <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 74115849Sphk <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 75115849Sphk <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ 76157740Scracauer <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 77157740Scracauer <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ 78115849Sphk <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 79115849Sphk <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 80115849Sphk 81115849Sphk /* MCU Domain Range */ 82115731Sphk <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 83115731Sphk 84115731Sphk /* Wakeup Domain Range */ 85115731Sphk <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 86115731Sphk <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 87115731Sphk <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; 88115731Sphk 89115731Sphk cbass_mcu: bus@4000000 { 90115731Sphk bootph-all; 91115731Sphk compatible = "simple-bus"; 92115731Sphk #address-cells = <2>; 93115731Sphk #size-cells = <2>; 94115731Sphk ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ 95115731Sphk }; 96115731Sphk 97115731Sphk cbass_wakeup: bus@b00000 { 98115731Sphk bootph-all; 99115731Sphk compatible = "simple-bus"; 100115731Sphk #address-cells = <2>; 101115731Sphk #size-cells = <2>; 102115731Sphk ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 103115731Sphk <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ 104115731Sphk <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; 105115731Sphk }; 106115731Sphk }; 107115731Sphk 108115731Sphk dss_vp1_clk: clock-divider-oldi { 109115731Sphk compatible = "fixed-factor-clock"; 110115731Sphk clocks = <&k3_clks 186 0>; 111115731Sphk #clock-cells = <0>; 112115731Sphk clock-div = <7>; 113115731Sphk clock-mult = <1>; 114115731Sphk }; 115115731Sphk 116115849Sphk #include "k3-am62-thermal.dtsi" 117115849Sphk}; 118115731Sphk 119115849Sphk/* Now include the peripherals for each bus segments */ 120119300Sps#include "k3-am62-main.dtsi" 121115849Sphk#include "k3-am62-mcu.dtsi" 122115849Sphk#include "k3-am62-wakeup.dtsi" 123115731Sphk