1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r9a06g032-sysctrl.h> 11 12/ { 13 compatible = "renesas,r9a06g032"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a7"; 24 reg = <0>; 25 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 26 }; 27 28 cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <1>; 32 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 33 enable-method = "renesas,r9a06g032-smp"; 34 cpu-release-addr = <0 0x4000c204>; 35 }; 36 }; 37 38 ext_jtag_clk: extjtagclk { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <0>; 42 }; 43 44 ext_mclk: extmclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <40000000>; 48 }; 49 50 ext_rgmii_ref: extrgmiiref { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <0>; 54 }; 55 56 ext_rtc_clk: extrtcclk { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <0>; 60 }; 61 62 soc { 63 compatible = "simple-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 interrupt-parent = <&gic>; 67 ranges; 68 69 rtc0: rtc@40006000 { 70 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; 71 reg = <0x40006000 0x1000>; 72 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 73 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 74 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 75 interrupt-names = "alarm", "timer", "pps"; 76 clocks = <&sysctrl R9A06G032_HCLK_RTC>; 77 clock-names = "hclk"; 78 power-domains = <&sysctrl>; 79 status = "disabled"; 80 }; 81 82 wdt0: watchdog@40008000 { 83 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 84 reg = <0x40008000 0x1000>; 85 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 87 status = "disabled"; 88 }; 89 90 wdt1: watchdog@40009000 { 91 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 92 reg = <0x40009000 0x1000>; 93 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; 94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 95 status = "disabled"; 96 }; 97 98 sysctrl: system-controller@4000c000 { 99 compatible = "renesas,r9a06g032-sysctrl"; 100 reg = <0x4000c000 0x1000>; 101 status = "okay"; 102 #clock-cells = <1>; 103 #power-domain-cells = <0>; 104 105 clocks = <&ext_mclk>, <&ext_rtc_clk>, 106 <&ext_jtag_clk>, <&ext_rgmii_ref>; 107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 111 dmamux: dma-router@a0 { 112 compatible = "renesas,rzn1-dmamux"; 113 reg = <0xa0 4>; 114 #dma-cells = <6>; 115 dma-requests = <32>; 116 dma-masters = <&dma0 &dma1>; 117 }; 118 }; 119 120 udc: usb@4001e000 { 121 compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; 122 reg = <0x4001e000 0x2000>; 123 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&sysctrl R9A06G032_HCLK_USBF>, 126 <&sysctrl R9A06G032_HCLK_USBPM>; 127 clock-names = "hclkf", "hclkpm"; 128 power-domains = <&sysctrl>; 129 status = "disabled"; 130 }; 131 132 pci_usb: pci@40030000 { 133 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; 134 device_type = "pci"; 135 clocks = <&sysctrl R9A06G032_HCLK_USBH>, 136 <&sysctrl R9A06G032_HCLK_USBPM>, 137 <&sysctrl R9A06G032_CLK_PCI_USB>; 138 clock-names = "hclkh", "hclkpm", "pciclk"; 139 power-domains = <&sysctrl>; 140 reg = <0x40030000 0xc00>, 141 <0x40020000 0x1100>; 142 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 145 bus-range = <0 0>; 146 #address-cells = <3>; 147 #size-cells = <2>; 148 #interrupt-cells = <1>; 149 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; 150 /* Should map all possible DDR as inbound ranges, but 151 * the IP only supports a 256MB, 512MB, or 1GB window. 152 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) 153 */ 154 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; 155 interrupt-map-mask = <0xf800 0 0 0x7>; 156 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 157 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 158 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 159 160 usb@1,0 { 161 reg = <0x800 0 0 0 0>; 162 phys = <&usbphy>; 163 phy-names = "usb"; 164 }; 165 166 usb@2,0 { 167 reg = <0x1000 0 0 0 0>; 168 phys = <&usbphy>; 169 phy-names = "usb"; 170 }; 171 }; 172 173 uart0: serial@40060000 { 174 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 175 reg = <0x40060000 0x400>; 176 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 177 reg-shift = <2>; 178 reg-io-width = <4>; 179 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; 180 clock-names = "baudclk", "apb_pclk"; 181 status = "disabled"; 182 }; 183 184 uart1: serial@40061000 { 185 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 186 reg = <0x40061000 0x400>; 187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 188 reg-shift = <2>; 189 reg-io-width = <4>; 190 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; 191 clock-names = "baudclk", "apb_pclk"; 192 status = "disabled"; 193 }; 194 195 uart2: serial@40062000 { 196 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 197 reg = <0x40062000 0x400>; 198 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 199 reg-shift = <2>; 200 reg-io-width = <4>; 201 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; 202 clock-names = "baudclk", "apb_pclk"; 203 status = "disabled"; 204 }; 205 206 uart3: serial@50000000 { 207 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 208 reg = <0x50000000 0x400>; 209 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 210 reg-shift = <2>; 211 reg-io-width = <4>; 212 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; 213 clock-names = "baudclk", "apb_pclk"; 214 dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; 215 dma-names = "rx", "tx"; 216 status = "disabled"; 217 }; 218 219 uart4: serial@50001000 { 220 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 221 reg = <0x50001000 0x400>; 222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; 226 clock-names = "baudclk", "apb_pclk"; 227 dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; 228 dma-names = "rx", "tx"; 229 status = "disabled"; 230 }; 231 232 uart5: serial@50002000 { 233 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 234 reg = <0x50002000 0x400>; 235 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; 239 clock-names = "baudclk", "apb_pclk"; 240 dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; 241 dma-names = "rx", "tx"; 242 status = "disabled"; 243 }; 244 245 uart6: serial@50003000 { 246 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 247 reg = <0x50003000 0x400>; 248 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 249 reg-shift = <2>; 250 reg-io-width = <4>; 251 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; 252 clock-names = "baudclk", "apb_pclk"; 253 dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; 254 dma-names = "rx", "tx"; 255 status = "disabled"; 256 }; 257 258 uart7: serial@50004000 { 259 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 260 reg = <0x50004000 0x400>; 261 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; 265 clock-names = "baudclk", "apb_pclk"; 266 dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; 267 dma-names = "rx", "tx"; 268 status = "disabled"; 269 }; 270 271 pinctrl: pinctrl@40067000 { 272 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; 273 reg = <0x40067000 0x1000>, <0x51000000 0x480>; 274 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; 275 clock-names = "bus"; 276 status = "okay"; 277 }; 278 279 nand_controller: nand-controller@40102000 { 280 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; 281 reg = <0x40102000 0x2000>; 282 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; 284 clock-names = "hclk", "eclk"; 285 power-domains = <&sysctrl>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 }; 290 291 dma0: dma-controller@40104000 { 292 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 293 reg = <0x40104000 0x1000>; 294 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 295 clock-names = "hclk"; 296 clocks = <&sysctrl R9A06G032_HCLK_DMA0>; 297 dma-channels = <8>; 298 dma-requests = <16>; 299 dma-masters = <1>; 300 #dma-cells = <3>; 301 block_size = <0xfff>; 302 data-width = <8>; 303 }; 304 305 dma1: dma-controller@40105000 { 306 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 307 reg = <0x40105000 0x1000>; 308 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 309 clock-names = "hclk"; 310 clocks = <&sysctrl R9A06G032_HCLK_DMA1>; 311 dma-channels = <8>; 312 dma-requests = <16>; 313 dma-masters = <1>; 314 #dma-cells = <3>; 315 block_size = <0xfff>; 316 data-width = <8>; 317 }; 318 319 gmac2: ethernet@44002000 { 320 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 321 reg = <0x44002000 0x2000>; 322 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 325 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 326 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; 327 clock-names = "stmmaceth"; 328 power-domains = <&sysctrl>; 329 snps,multicast-filter-bins = <256>; 330 snps,perfect-filter-entries = <128>; 331 tx-fifo-depth = <2048>; 332 rx-fifo-depth = <4096>; 333 status = "disabled"; 334 }; 335 336 eth_miic: eth-miic@44030000 { 337 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <0x44030000 0x10000>; 341 clocks = <&sysctrl R9A06G032_CLK_MII_REF>, 342 <&sysctrl R9A06G032_CLK_RGMII_REF>, 343 <&sysctrl R9A06G032_CLK_RMII_REF>, 344 <&sysctrl R9A06G032_HCLK_SWITCH_RG>; 345 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 346 power-domains = <&sysctrl>; 347 status = "disabled"; 348 349 mii_conv1: mii-conv@1 { 350 reg = <1>; 351 status = "disabled"; 352 }; 353 354 mii_conv2: mii-conv@2 { 355 reg = <2>; 356 status = "disabled"; 357 }; 358 359 mii_conv3: mii-conv@3 { 360 reg = <3>; 361 status = "disabled"; 362 }; 363 364 mii_conv4: mii-conv@4 { 365 reg = <4>; 366 status = "disabled"; 367 }; 368 369 mii_conv5: mii-conv@5 { 370 reg = <5>; 371 status = "disabled"; 372 }; 373 }; 374 375 switch: switch@44050000 { 376 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; 377 reg = <0x44050000 0x10000>; 378 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, 379 <&sysctrl R9A06G032_CLK_SWITCH>; 380 clock-names = "hclk", "clk"; 381 power-domains = <&sysctrl>; 382 status = "disabled"; 383 384 ethernet-ports { 385 #address-cells = <1>; 386 #size-cells = <0>; 387 388 switch_port0: port@0 { 389 reg = <0>; 390 pcs-handle = <&mii_conv5>; 391 status = "disabled"; 392 }; 393 394 switch_port1: port@1 { 395 reg = <1>; 396 pcs-handle = <&mii_conv4>; 397 status = "disabled"; 398 }; 399 400 switch_port2: port@2 { 401 reg = <2>; 402 pcs-handle = <&mii_conv3>; 403 status = "disabled"; 404 }; 405 406 switch_port3: port@3 { 407 reg = <3>; 408 pcs-handle = <&mii_conv2>; 409 status = "disabled"; 410 }; 411 412 switch_port4: port@4 { 413 reg = <4>; 414 ethernet = <&gmac2>; 415 label = "cpu"; 416 phy-mode = "internal"; 417 status = "disabled"; 418 fixed-link { 419 speed = <1000>; 420 full-duplex; 421 }; 422 }; 423 }; 424 }; 425 426 gic: interrupt-controller@44101000 { 427 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 428 interrupt-controller; 429 #interrupt-cells = <3>; 430 reg = <0x44101000 0x1000>, /* Distributer */ 431 <0x44102000 0x2000>, /* CPU interface */ 432 <0x44104000 0x2000>, /* Virt interface control */ 433 <0x44106000 0x2000>; /* Virt CPU interface */ 434 interrupts = 435 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 436 }; 437 438 can0: can@52104000 { 439 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 440 reg = <0x52104000 0x800>; 441 reg-io-width = <4>; 442 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&sysctrl R9A06G032_HCLK_CAN0>; 444 power-domains = <&sysctrl>; 445 status = "disabled"; 446 }; 447 448 can1: can@52105000 { 449 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 450 reg = <0x52105000 0x800>; 451 reg-io-width = <4>; 452 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&sysctrl R9A06G032_HCLK_CAN1>; 454 power-domains = <&sysctrl>; 455 status = "disabled"; 456 }; 457 }; 458 459 timer { 460 compatible = "arm,armv7-timer"; 461 interrupt-parent = <&gic>; 462 arm,cpu-registers-not-fw-configured; 463 always-on; 464 interrupts = 465 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 466 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 467 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 468 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 469 }; 470 471 usbphy: usb-phy { 472 #phy-cells = <0>; 473 compatible = "usb-nop-xceiv"; 474 status = "disabled"; 475 }; 476}; 477