1/* SPDX-License-Identifier: MIT */
2
3#ifndef __XEN_PUBLIC_PHYSDEV_H__
4#define __XEN_PUBLIC_PHYSDEV_H__
5
6/*
7 * Prototype for this hypercall is:
8 *  int physdev_op(int cmd, void *args)
9 * @cmd	 == PHYSDEVOP_??? (physdev operation).
10 * @args == Operation-specific extra arguments (NULL if none).
11 */
12
13/*
14 * Notify end-of-interrupt (EOI) for the specified IRQ.
15 * @arg == pointer to physdev_eoi structure.
16 */
17#define PHYSDEVOP_eoi			12
18struct physdev_eoi {
19	/* IN */
20	uint32_t irq;
21};
22
23/*
24 * Register a shared page for the hypervisor to indicate whether the guest
25 * must issue PHYSDEVOP_eoi. The semantics of PHYSDEVOP_eoi change slightly
26 * once the guest used this function in that the associated event channel
27 * will automatically get unmasked. The page registered is used as a bit
28 * array indexed by Xen's PIRQ value.
29 */
30#define PHYSDEVOP_pirq_eoi_gmfn_v1       17
31/*
32 * Register a shared page for the hypervisor to indicate whether the
33 * guest must issue PHYSDEVOP_eoi. This hypercall is very similar to
34 * PHYSDEVOP_pirq_eoi_gmfn_v1 but it doesn't change the semantics of
35 * PHYSDEVOP_eoi. The page registered is used as a bit array indexed by
36 * Xen's PIRQ value.
37 */
38#define PHYSDEVOP_pirq_eoi_gmfn_v2       28
39struct physdev_pirq_eoi_gmfn {
40    /* IN */
41    xen_ulong_t gmfn;
42};
43
44/*
45 * Query the status of an IRQ line.
46 * @arg == pointer to physdev_irq_status_query structure.
47 */
48#define PHYSDEVOP_irq_status_query	 5
49struct physdev_irq_status_query {
50	/* IN */
51	uint32_t irq;
52	/* OUT */
53	uint32_t flags; /* XENIRQSTAT_* */
54};
55
56/* Need to call PHYSDEVOP_eoi when the IRQ has been serviced? */
57#define _XENIRQSTAT_needs_eoi	(0)
58#define	 XENIRQSTAT_needs_eoi	(1U<<_XENIRQSTAT_needs_eoi)
59
60/* IRQ shared by multiple guests? */
61#define _XENIRQSTAT_shared	(1)
62#define	 XENIRQSTAT_shared	(1U<<_XENIRQSTAT_shared)
63
64/*
65 * Set the current VCPU's I/O privilege level.
66 * @arg == pointer to physdev_set_iopl structure.
67 */
68#define PHYSDEVOP_set_iopl		 6
69struct physdev_set_iopl {
70	/* IN */
71	uint32_t iopl;
72};
73
74/*
75 * Set the current VCPU's I/O-port permissions bitmap.
76 * @arg == pointer to physdev_set_iobitmap structure.
77 */
78#define PHYSDEVOP_set_iobitmap		 7
79struct physdev_set_iobitmap {
80	/* IN */
81	uint8_t * bitmap;
82	uint32_t nr_ports;
83};
84
85/*
86 * Read or write an IO-APIC register.
87 * @arg == pointer to physdev_apic structure.
88 */
89#define PHYSDEVOP_apic_read		 8
90#define PHYSDEVOP_apic_write		 9
91struct physdev_apic {
92	/* IN */
93	unsigned long apic_physbase;
94	uint32_t reg;
95	/* IN or OUT */
96	uint32_t value;
97};
98
99/*
100 * Allocate or free a physical upcall vector for the specified IRQ line.
101 * @arg == pointer to physdev_irq structure.
102 */
103#define PHYSDEVOP_alloc_irq_vector	10
104#define PHYSDEVOP_free_irq_vector	11
105struct physdev_irq {
106	/* IN */
107	uint32_t irq;
108	/* IN or OUT */
109	uint32_t vector;
110};
111
112#define MAP_PIRQ_TYPE_MSI		0x0
113#define MAP_PIRQ_TYPE_GSI		0x1
114#define MAP_PIRQ_TYPE_UNKNOWN		0x2
115#define MAP_PIRQ_TYPE_MSI_SEG		0x3
116#define MAP_PIRQ_TYPE_MULTI_MSI		0x4
117
118#define PHYSDEVOP_map_pirq		13
119struct physdev_map_pirq {
120    domid_t domid;
121    /* IN */
122    int type;
123    /* IN */
124    int index;
125    /* IN or OUT */
126    int pirq;
127    /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
128    int bus;
129    /* IN */
130    int devfn;
131    /* IN
132     * - For MSI-X contains entry number.
133     * - For MSI with ..._MULTI_MSI contains number of vectors.
134     * OUT (..._MULTI_MSI only)
135     * - Number of vectors allocated.
136     */
137    int entry_nr;
138    /* IN */
139    uint64_t table_base;
140};
141
142#define PHYSDEVOP_unmap_pirq		14
143struct physdev_unmap_pirq {
144    domid_t domid;
145    /* IN */
146    int pirq;
147};
148
149#define PHYSDEVOP_manage_pci_add	15
150#define PHYSDEVOP_manage_pci_remove	16
151struct physdev_manage_pci {
152	/* IN */
153	uint8_t bus;
154	uint8_t devfn;
155};
156
157#define PHYSDEVOP_restore_msi            19
158struct physdev_restore_msi {
159	/* IN */
160	uint8_t bus;
161	uint8_t devfn;
162};
163
164#define PHYSDEVOP_manage_pci_add_ext	20
165struct physdev_manage_pci_ext {
166	/* IN */
167	uint8_t bus;
168	uint8_t devfn;
169	unsigned is_extfn;
170	unsigned is_virtfn;
171	struct {
172		uint8_t bus;
173		uint8_t devfn;
174	} physfn;
175};
176
177/*
178 * Argument to physdev_op_compat() hypercall. Superceded by new physdev_op()
179 * hypercall since 0x00030202.
180 */
181struct physdev_op {
182	uint32_t cmd;
183	union {
184		struct physdev_irq_status_query	     irq_status_query;
185		struct physdev_set_iopl		     set_iopl;
186		struct physdev_set_iobitmap	     set_iobitmap;
187		struct physdev_apic		     apic_op;
188		struct physdev_irq		     irq_op;
189	} u;
190};
191
192#define PHYSDEVOP_setup_gsi    21
193struct physdev_setup_gsi {
194    int gsi;
195    /* IN */
196    uint8_t triggering;
197    /* IN */
198    uint8_t polarity;
199    /* IN */
200};
201
202#define PHYSDEVOP_get_nr_pirqs    22
203struct physdev_nr_pirqs {
204    /* OUT */
205    uint32_t nr_pirqs;
206};
207
208/* type is MAP_PIRQ_TYPE_GSI or MAP_PIRQ_TYPE_MSI
209 * the hypercall returns a free pirq */
210#define PHYSDEVOP_get_free_pirq    23
211struct physdev_get_free_pirq {
212    /* IN */
213    int type;
214    /* OUT */
215    uint32_t pirq;
216};
217
218#define XEN_PCI_DEV_EXTFN              0x1
219#define XEN_PCI_DEV_VIRTFN             0x2
220#define XEN_PCI_DEV_PXM                0x4
221
222#define XEN_PCI_MMCFG_RESERVED         0x1
223
224#define PHYSDEVOP_pci_mmcfg_reserved    24
225struct physdev_pci_mmcfg_reserved {
226    uint64_t address;
227    uint16_t segment;
228    uint8_t start_bus;
229    uint8_t end_bus;
230    uint32_t flags;
231};
232
233#define PHYSDEVOP_pci_device_add        25
234struct physdev_pci_device_add {
235    /* IN */
236    uint16_t seg;
237    uint8_t bus;
238    uint8_t devfn;
239    uint32_t flags;
240    struct {
241        uint8_t bus;
242        uint8_t devfn;
243    } physfn;
244#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
245    uint32_t optarr[];
246#elif defined(__GNUC__)
247    uint32_t optarr[0];
248#endif
249};
250
251#define PHYSDEVOP_pci_device_remove     26
252#define PHYSDEVOP_restore_msi_ext       27
253/*
254 * Dom0 should use these two to announce MMIO resources assigned to
255 * MSI-X capable devices won't (prepare) or may (release) change.
256 */
257#define PHYSDEVOP_prepare_msix          30
258#define PHYSDEVOP_release_msix          31
259struct physdev_pci_device {
260    /* IN */
261    uint16_t seg;
262    uint8_t bus;
263    uint8_t devfn;
264};
265
266#define PHYSDEVOP_DBGP_RESET_PREPARE    1
267#define PHYSDEVOP_DBGP_RESET_DONE       2
268
269#define PHYSDEVOP_DBGP_BUS_UNKNOWN      0
270#define PHYSDEVOP_DBGP_BUS_PCI          1
271
272#define PHYSDEVOP_dbgp_op               29
273struct physdev_dbgp_op {
274    /* IN */
275    uint8_t op;
276    uint8_t bus;
277    union {
278        struct physdev_pci_device pci;
279    } u;
280};
281
282/*
283 * Notify that some PIRQ-bound event channels have been unmasked.
284 * ** This command is obsolete since interface version 0x00030202 and is **
285 * ** unsupported by newer versions of Xen.				 **
286 */
287#define PHYSDEVOP_IRQ_UNMASK_NOTIFY	 4
288
289/*
290 * These all-capitals physdev operation names are superceded by the new names
291 * (defined above) since interface version 0x00030202.
292 */
293#define PHYSDEVOP_IRQ_STATUS_QUERY	 PHYSDEVOP_irq_status_query
294#define PHYSDEVOP_SET_IOPL		 PHYSDEVOP_set_iopl
295#define PHYSDEVOP_SET_IOBITMAP		 PHYSDEVOP_set_iobitmap
296#define PHYSDEVOP_APIC_READ		 PHYSDEVOP_apic_read
297#define PHYSDEVOP_APIC_WRITE		 PHYSDEVOP_apic_write
298#define PHYSDEVOP_ASSIGN_VECTOR		 PHYSDEVOP_alloc_irq_vector
299#define PHYSDEVOP_FREE_VECTOR		 PHYSDEVOP_free_irq_vector
300#define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi
301#define PHYSDEVOP_IRQ_SHARED		 XENIRQSTAT_shared
302
303#endif /* __XEN_PUBLIC_PHYSDEV_H__ */
304