1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 *     Dave Airlie <airlied@redhat.com>
8 *     Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 *    may be used to endorse or promote products derived from this software
23 *    without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38#ifndef VIRTIO_GPU_HW_H
39#define VIRTIO_GPU_HW_H
40
41#include <linux/types.h>
42
43/*
44 * VIRTIO_GPU_CMD_CTX_*
45 * VIRTIO_GPU_CMD_*_3D
46 */
47#define VIRTIO_GPU_F_VIRGL               0
48
49/*
50 * VIRTIO_GPU_CMD_GET_EDID
51 */
52#define VIRTIO_GPU_F_EDID                1
53/*
54 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
55 */
56#define VIRTIO_GPU_F_RESOURCE_UUID       2
57
58/*
59 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
60 */
61#define VIRTIO_GPU_F_RESOURCE_BLOB       3
62/*
63 * VIRTIO_GPU_CMD_CREATE_CONTEXT with
64 * context_init and multiple timelines
65 */
66#define VIRTIO_GPU_F_CONTEXT_INIT        4
67
68enum virtio_gpu_ctrl_type {
69	VIRTIO_GPU_UNDEFINED = 0,
70
71	/* 2d commands */
72	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
73	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
74	VIRTIO_GPU_CMD_RESOURCE_UNREF,
75	VIRTIO_GPU_CMD_SET_SCANOUT,
76	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
77	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
78	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
79	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
80	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
81	VIRTIO_GPU_CMD_GET_CAPSET,
82	VIRTIO_GPU_CMD_GET_EDID,
83	VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
84	VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
85	VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
86
87	/* 3d commands */
88	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
89	VIRTIO_GPU_CMD_CTX_DESTROY,
90	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
91	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
92	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
93	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
94	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
95	VIRTIO_GPU_CMD_SUBMIT_3D,
96	VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
97	VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
98
99	/* cursor commands */
100	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
101	VIRTIO_GPU_CMD_MOVE_CURSOR,
102
103	/* success responses */
104	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
105	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
106	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
107	VIRTIO_GPU_RESP_OK_CAPSET,
108	VIRTIO_GPU_RESP_OK_EDID,
109	VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
110	VIRTIO_GPU_RESP_OK_MAP_INFO,
111
112	/* error responses */
113	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
114	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
115	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
116	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
117	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
118	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
119};
120
121enum virtio_gpu_shm_id {
122	VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
123	/*
124	 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
125	 * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
126	 */
127	VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
128};
129
130#define VIRTIO_GPU_FLAG_FENCE         (1 << 0)
131/*
132 * If the following flag is set, then ring_idx contains the index
133 * of the command ring that needs to used when creating the fence
134 */
135#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
136
137struct virtio_gpu_ctrl_hdr {
138	__le32 type;
139	__le32 flags;
140	__le64 fence_id;
141	__le32 ctx_id;
142	__u8 ring_idx;
143	__u8 padding[3];
144};
145
146/* data passed in the cursor vq */
147
148struct virtio_gpu_cursor_pos {
149	__le32 scanout_id;
150	__le32 x;
151	__le32 y;
152	__le32 padding;
153};
154
155/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
156struct virtio_gpu_update_cursor {
157	struct virtio_gpu_ctrl_hdr hdr;
158	struct virtio_gpu_cursor_pos pos;  /* update & move */
159	__le32 resource_id;           /* update only */
160	__le32 hot_x;                 /* update only */
161	__le32 hot_y;                 /* update only */
162	__le32 padding;
163};
164
165/* data passed in the control vq, 2d related */
166
167struct virtio_gpu_rect {
168	__le32 x;
169	__le32 y;
170	__le32 width;
171	__le32 height;
172};
173
174/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
175struct virtio_gpu_resource_unref {
176	struct virtio_gpu_ctrl_hdr hdr;
177	__le32 resource_id;
178	__le32 padding;
179};
180
181/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
182struct virtio_gpu_resource_create_2d {
183	struct virtio_gpu_ctrl_hdr hdr;
184	__le32 resource_id;
185	__le32 format;
186	__le32 width;
187	__le32 height;
188};
189
190/* VIRTIO_GPU_CMD_SET_SCANOUT */
191struct virtio_gpu_set_scanout {
192	struct virtio_gpu_ctrl_hdr hdr;
193	struct virtio_gpu_rect r;
194	__le32 scanout_id;
195	__le32 resource_id;
196};
197
198/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
199struct virtio_gpu_resource_flush {
200	struct virtio_gpu_ctrl_hdr hdr;
201	struct virtio_gpu_rect r;
202	__le32 resource_id;
203	__le32 padding;
204};
205
206/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
207struct virtio_gpu_transfer_to_host_2d {
208	struct virtio_gpu_ctrl_hdr hdr;
209	struct virtio_gpu_rect r;
210	__le64 offset;
211	__le32 resource_id;
212	__le32 padding;
213};
214
215struct virtio_gpu_mem_entry {
216	__le64 addr;
217	__le32 length;
218	__le32 padding;
219};
220
221/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
222struct virtio_gpu_resource_attach_backing {
223	struct virtio_gpu_ctrl_hdr hdr;
224	__le32 resource_id;
225	__le32 nr_entries;
226};
227
228/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
229struct virtio_gpu_resource_detach_backing {
230	struct virtio_gpu_ctrl_hdr hdr;
231	__le32 resource_id;
232	__le32 padding;
233};
234
235/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
236#define VIRTIO_GPU_MAX_SCANOUTS 16
237struct virtio_gpu_resp_display_info {
238	struct virtio_gpu_ctrl_hdr hdr;
239	struct virtio_gpu_display_one {
240		struct virtio_gpu_rect r;
241		__le32 enabled;
242		__le32 flags;
243	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
244};
245
246/* data passed in the control vq, 3d related */
247
248struct virtio_gpu_box {
249	__le32 x, y, z;
250	__le32 w, h, d;
251};
252
253/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
254struct virtio_gpu_transfer_host_3d {
255	struct virtio_gpu_ctrl_hdr hdr;
256	struct virtio_gpu_box box;
257	__le64 offset;
258	__le32 resource_id;
259	__le32 level;
260	__le32 stride;
261	__le32 layer_stride;
262};
263
264/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
265#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
266struct virtio_gpu_resource_create_3d {
267	struct virtio_gpu_ctrl_hdr hdr;
268	__le32 resource_id;
269	__le32 target;
270	__le32 format;
271	__le32 bind;
272	__le32 width;
273	__le32 height;
274	__le32 depth;
275	__le32 array_size;
276	__le32 last_level;
277	__le32 nr_samples;
278	__le32 flags;
279	__le32 padding;
280};
281
282/* VIRTIO_GPU_CMD_CTX_CREATE */
283#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
284struct virtio_gpu_ctx_create {
285	struct virtio_gpu_ctrl_hdr hdr;
286	__le32 nlen;
287	__le32 context_init;
288	char debug_name[64];
289};
290
291/* VIRTIO_GPU_CMD_CTX_DESTROY */
292struct virtio_gpu_ctx_destroy {
293	struct virtio_gpu_ctrl_hdr hdr;
294};
295
296/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
297struct virtio_gpu_ctx_resource {
298	struct virtio_gpu_ctrl_hdr hdr;
299	__le32 resource_id;
300	__le32 padding;
301};
302
303/* VIRTIO_GPU_CMD_SUBMIT_3D */
304struct virtio_gpu_cmd_submit {
305	struct virtio_gpu_ctrl_hdr hdr;
306	__le32 size;
307	__le32 padding;
308};
309
310#define VIRTIO_GPU_CAPSET_VIRGL 1
311#define VIRTIO_GPU_CAPSET_VIRGL2 2
312/* 3 is reserved for gfxstream */
313#define VIRTIO_GPU_CAPSET_VENUS 4
314
315/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
316struct virtio_gpu_get_capset_info {
317	struct virtio_gpu_ctrl_hdr hdr;
318	__le32 capset_index;
319	__le32 padding;
320};
321
322/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
323struct virtio_gpu_resp_capset_info {
324	struct virtio_gpu_ctrl_hdr hdr;
325	__le32 capset_id;
326	__le32 capset_max_version;
327	__le32 capset_max_size;
328	__le32 padding;
329};
330
331/* VIRTIO_GPU_CMD_GET_CAPSET */
332struct virtio_gpu_get_capset {
333	struct virtio_gpu_ctrl_hdr hdr;
334	__le32 capset_id;
335	__le32 capset_version;
336};
337
338/* VIRTIO_GPU_RESP_OK_CAPSET */
339struct virtio_gpu_resp_capset {
340	struct virtio_gpu_ctrl_hdr hdr;
341	__u8 capset_data[];
342};
343
344/* VIRTIO_GPU_CMD_GET_EDID */
345struct virtio_gpu_cmd_get_edid {
346	struct virtio_gpu_ctrl_hdr hdr;
347	__le32 scanout;
348	__le32 padding;
349};
350
351/* VIRTIO_GPU_RESP_OK_EDID */
352struct virtio_gpu_resp_edid {
353	struct virtio_gpu_ctrl_hdr hdr;
354	__le32 size;
355	__le32 padding;
356	__u8 edid[1024];
357};
358
359#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
360
361struct virtio_gpu_config {
362	__le32 events_read;
363	__le32 events_clear;
364	__le32 num_scanouts;
365	__le32 num_capsets;
366};
367
368/* simple formats for fbcon/X use */
369enum virtio_gpu_formats {
370	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
371	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
372	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
373	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,
374
375	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
376	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,
377
378	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
379	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
380};
381
382/* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
383struct virtio_gpu_resource_assign_uuid {
384	struct virtio_gpu_ctrl_hdr hdr;
385	__le32 resource_id;
386	__le32 padding;
387};
388
389/* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
390struct virtio_gpu_resp_resource_uuid {
391	struct virtio_gpu_ctrl_hdr hdr;
392	__u8 uuid[16];
393};
394
395/* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
396struct virtio_gpu_resource_create_blob {
397	struct virtio_gpu_ctrl_hdr hdr;
398	__le32 resource_id;
399#define VIRTIO_GPU_BLOB_MEM_GUEST             0x0001
400#define VIRTIO_GPU_BLOB_MEM_HOST3D            0x0002
401#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST      0x0003
402
403#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE     0x0001
404#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE    0x0002
405#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
406	/* zero is invalid blob mem */
407	__le32 blob_mem;
408	__le32 blob_flags;
409	__le32 nr_entries;
410	__le64 blob_id;
411	__le64 size;
412	/*
413	 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
414	 */
415};
416
417/* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
418struct virtio_gpu_set_scanout_blob {
419	struct virtio_gpu_ctrl_hdr hdr;
420	struct virtio_gpu_rect r;
421	__le32 scanout_id;
422	__le32 resource_id;
423	__le32 width;
424	__le32 height;
425	__le32 format;
426	__le32 padding;
427	__le32 strides[4];
428	__le32 offsets[4];
429};
430
431/* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
432struct virtio_gpu_resource_map_blob {
433	struct virtio_gpu_ctrl_hdr hdr;
434	__le32 resource_id;
435	__le32 padding;
436	__le64 offset;
437};
438
439/* VIRTIO_GPU_RESP_OK_MAP_INFO */
440#define VIRTIO_GPU_MAP_CACHE_MASK     0x0f
441#define VIRTIO_GPU_MAP_CACHE_NONE     0x00
442#define VIRTIO_GPU_MAP_CACHE_CACHED   0x01
443#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
444#define VIRTIO_GPU_MAP_CACHE_WC       0x03
445struct virtio_gpu_resp_map_info {
446	struct virtio_gpu_ctrl_hdr hdr;
447	__u32 map_info;
448	__u32 padding;
449};
450
451/* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
452struct virtio_gpu_resource_unmap_blob {
453	struct virtio_gpu_ctrl_hdr hdr;
454	__le32 resource_id;
455	__le32 padding;
456};
457
458#endif
459