138032Speter/* SPDX-License-Identifier: GPL-2.0-or-later */ 2203004Sgshapiro#ifndef __SOUND_AK4114_H 364562Sgshapiro#define __SOUND_AK4114_H 438032Speter 538032Speter/* 638032Speter * Routines for Asahi Kasei AK4114 738032Speter * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 838032Speter */ 938032Speter 1038032Speter/* AK4114 registers */ 1138032Speter#define AK4114_REG_PWRDN 0x00 /* power down */ 1238032Speter#define AK4114_REG_FORMAT 0x01 /* format control */ 1338032Speter#define AK4114_REG_IO0 0x02 /* input/output control */ 1464562Sgshapiro#define AK4114_REG_IO1 0x03 /* input/output control */ 1538032Speter#define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */ 16249729Sgshapiro#define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */ 1764562Sgshapiro#define AK4114_REG_RCS0 0x06 /* receiver status 0 */ 1890792Sgshapiro#define AK4114_REG_RCS1 0x07 /* receiver status 1 */ 1990792Sgshapiro#define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */ 2090792Sgshapiro#define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */ 2190792Sgshapiro#define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */ 2290792Sgshapiro#define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */ 2338032Speter#define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */ 2438032Speter#define AK4114_REG_TXCSB0 0x0d /* TX channel status byte 0 */ 2538032Speter#define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */ 2638032Speter#define AK4114_REG_TXCSB2 0x0f /* TX channel status byte 2 */ 2738032Speter#define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */ 2838032Speter#define AK4114_REG_TXCSB4 0x11 /* TX channel status byte 4 */ 2964562Sgshapiro#define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */ 3064562Sgshapiro#define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */ 3190792Sgshapiro#define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */ 32110560Sgshapiro#define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */ 3364562Sgshapiro#define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */ 3490792Sgshapiro#define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */ 3538032Speter#define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */ 3638032Speter#define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */ 3790792Sgshapiro#define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */ 3838032Speter#define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */ 3964562Sgshapiro#define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */ 4064562Sgshapiro#define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */ 4138032Speter#define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */ 42168515Sgshapiro#define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */ 43168515Sgshapiro 4490792Sgshapiro/* sizes */ 4564562Sgshapiro#define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1) 4664562Sgshapiro#define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1) 4764562Sgshapiro#define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1) 4864562Sgshapiro 4964562Sgshapiro/* AK4117_REG_PWRDN bits */ 5064562Sgshapiro#define AK4114_CS12 (1<<7) /* Channel Status Select */ 5164562Sgshapiro#define AK4114_BCU (1<<6) /* Block Start & C/U Output Mode */ 5264562Sgshapiro#define AK4114_CM1 (1<<5) /* Master Clock Operation Select */ 5364562Sgshapiro#define AK4114_CM0 (1<<4) /* Master Clock Operation Select */ 5464562Sgshapiro#define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */ 5573188Sgshapiro#define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */ 5690792Sgshapiro#define AK4114_PWN (1<<1) /* 0 = power down, 1 = normal operation */ 5790792Sgshapiro#define AK4114_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */ 5864562Sgshapiro 5990792Sgshapiro/* AK4114_REQ_FORMAT bits */ 6064562Sgshapiro#define AK4114_MONO (1<<7) /* Double Sampling Frequency Mode: 0 = stereo, 1 = mono */ 6190792Sgshapiro#define AK4114_DIF2 (1<<6) /* Audio Data Control */ 6264562Sgshapiro#define AK4114_DIF1 (1<<5) /* Audio Data Control */ 6364562Sgshapiro#define AK4114_DIF0 (1<<4) /* Audio Data Control */ 6490792Sgshapiro#define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */ 6564562Sgshapiro#define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */ 6664562Sgshapiro#define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */ 6764562Sgshapiro#define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */ 6864562Sgshapiro#define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */ 6964562Sgshapiro#define AK4114_DIF_24I2S (AK4114_DIF2|AK4114_DIF0) /* STDO: I2S */ 7064562Sgshapiro#define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = Input */ 71132943Sgshapiro#define AK4114_DIF_I24I2S (AK4114_DIF2|AK4114_DIF1|AK4114_DIF0) /* STDO: I2S; LRCLK, BICK = Input */ 72132943Sgshapiro#define AK4114_DEAU (1<<3) /* Deemphasis Autodetect Enable (1 = enable) */ 7364562Sgshapiro#define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */ 74132943Sgshapiro#define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */ 75132943Sgshapiro#define AK4114_DEM_44KHZ (0) 76132943Sgshapiro#define AK4114_DEM_48KHZ (AK4114_DEM1) 77132943Sgshapiro#define AK4114_DEM_32KHZ (AK4114_DEM0|AK4114_DEM1) 7890792Sgshapiro#define AK4114_DEM_96KHZ (AK4114_DEM1) /* DFS must be set */ 7990792Sgshapiro#define AK4114_DFS (1<<0) /* 96kHz Deemphasis Control */ 8090792Sgshapiro 8190792Sgshapiro/* AK4114_REG_IO0 */ 8290792Sgshapiro#define AK4114_TX1E (1<<7) /* TX1 Output Enable (1 = enable) */ 8390792Sgshapiro#define AK4114_OPS12 (1<<6) /* Output Data Selector for TX1 pin */ 8490792Sgshapiro#define AK4114_OPS11 (1<<5) /* Output Data Selector for TX1 pin */ 8590792Sgshapiro#define AK4114_OPS10 (1<<4) /* Output Data Selector for TX1 pin */ 8690792Sgshapiro#define AK4114_TX0E (1<<3) /* TX0 Output Enable (1 = enable) */ 8790792Sgshapiro#define AK4114_OPS02 (1<<2) /* Output Data Selector for TX0 pin */ 8890792Sgshapiro#define AK4114_OPS01 (1<<1) /* Output Data Selector for TX0 pin */ 8938032Speter#define AK4114_OPS00 (1<<0) /* Output Data Selector for TX0 pin */ 9038032Speter 9138032Speter/* AK4114_REG_IO1 */ 9238032Speter#define AK4114_EFH1 (1<<7) /* Interrupt 0 pin Hold */ 9338032Speter#define AK4114_EFH0 (1<<6) /* Interrupt 0 pin Hold */ 9438032Speter#define AK4114_EFH_512 (0) 9590792Sgshapiro#define AK4114_EFH_1024 (AK4114_EFH0) 9690792Sgshapiro#define AK4114_EFH_2048 (AK4114_EFH1) 9738032Speter#define AK4114_EFH_4096 (AK4114_EFH1|AK4114_EFH0) 9838032Speter#define AK4114_UDIT (1<<5) /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */ 9938032Speter#define AK4114_TLR (1<<4) /* Double Sampling Frequency Select for DIT (0 = L channel, 1 = R channel) */ 10038032Speter#define AK4114_DIT (1<<3) /* TX1 out: 0 = Through Data (RX data), 1 = Transmit Data (DAUX data) */ 10138032Speter#define AK4114_IPS2 (1<<2) /* Input Recovery Data Select */ 10238032Speter#define AK4114_IPS1 (1<<1) /* Input Recovery Data Select */ 10338032Speter#define AK4114_IPS0 (1<<0) /* Input Recovery Data Select */ 10438032Speter#define AK4114_IPS(x) ((x)&7) 10538032Speter 10638032Speter/* AK4114_REG_INT0_MASK && AK4114_REG_INT1_MASK*/ 10738032Speter#define AK4117_MQI (1<<7) /* mask enable for QINT bit */ 10838032Speter#define AK4117_MAT (1<<6) /* mask enable for AUTO bit */ 10938032Speter#define AK4117_MCI (1<<5) /* mask enable for CINT bit */ 11038032Speter#define AK4117_MUL (1<<4) /* mask enable for UNLOCK bit */ 11138032Speter#define AK4117_MDTS (1<<3) /* mask enable for DTSCD bit */ 11238032Speter#define AK4117_MPE (1<<2) /* mask enable for PEM bit */ 11338032Speter#define AK4117_MAN (1<<1) /* mask enable for AUDN bit */ 11490792Sgshapiro#define AK4117_MPR (1<<0) /* mask enable for PAR bit */ 11590792Sgshapiro 11690792Sgshapiro/* AK4114_REG_RCS0 */ 11738032Speter#define AK4114_QINT (1<<7) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ 11838032Speter#define AK4114_AUTO (1<<6) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ 11938032Speter#define AK4114_CINT (1<<5) /* channel status buffer interrupt, 0 = no change, 1 = change */ 12038032Speter#define AK4114_UNLCK (1<<4) /* PLL lock status, 0 = lock, 1 = unlock */ 12138032Speter#define AK4114_DTSCD (1<<3) /* DTS-CD Detect, 0 = No detect, 1 = Detect */ 12238032Speter#define AK4114_PEM (1<<2) /* Pre-emphasis Detect, 0 = OFF, 1 = ON */ 12338032Speter#define AK4114_AUDION (1<<1) /* audio bit output, 0 = audio, 1 = non-audio */ 12438032Speter#define AK4114_PAR (1<<0) /* parity error or biphase error status, 0 = no error, 1 = error */ 12538032Speter 12638032Speter/* AK4114_REG_RCS1 */ 12738032Speter#define AK4114_FS3 (1<<7) /* sampling frequency detection */ 12838032Speter#define AK4114_FS2 (1<<6) 12938032Speter#define AK4114_FS1 (1<<5) 13038032Speter#define AK4114_FS0 (1<<4) 13164562Sgshapiro#define AK4114_FS_44100HZ (0) 13238032Speter#define AK4114_FS_48000HZ (AK4114_FS1) 13364562Sgshapiro#define AK4114_FS_32000HZ (AK4114_FS1|AK4114_FS0) 13438032Speter#define AK4114_FS_88200HZ (AK4114_FS3) 13590792Sgshapiro#define AK4114_FS_96000HZ (AK4114_FS3|AK4114_FS1) 13638032Speter#define AK4114_FS_176400HZ (AK4114_FS3|AK4114_FS2) 13738032Speter#define AK4114_FS_192000HZ (AK4114_FS3|AK4114_FS2|AK4114_FS1) 13838032Speter#define AK4114_V (1<<3) /* Validity of Channel Status, 0 = Valid, 1 = Invalid */ 13938032Speter#define AK4114_QCRC (1<<1) /* CRC for Q-subcode, 0 = no error, 1 = error */ 14038032Speter#define AK4114_CCRC (1<<0) /* CRC for channel status, 0 = no error, 1 = error */ 14138032Speter 14238032Speter/* flags for snd_ak4114_check_rate_and_errors() */ 14338032Speter#define AK4114_CHECK_NO_STAT (1<<0) /* no statistics */ 14438032Speter#define AK4114_CHECK_NO_RATE (1<<1) /* no rate check */ 14590792Sgshapiro 14690792Sgshapiro#define AK4114_CONTROLS 15 14738032Speter 14838032Spetertypedef void (ak4114_write_t)(void *private_data, unsigned char addr, unsigned char data); 14938032Spetertypedef unsigned char (ak4114_read_t)(void *private_data, unsigned char addr); 15038032Speter 15138032Speterenum { 15238032Speter AK4114_PARITY_ERRORS, 15338032Speter AK4114_V_BIT_ERRORS, 15438032Speter AK4114_QCRC_ERRORS, 15538032Speter AK4114_CCRC_ERRORS, 15638032Speter AK4114_NUM_ERRORS 15738032Speter}; 15838032Speter 15964562Sgshapirostruct ak4114 { 16090792Sgshapiro struct snd_card *card; 16190792Sgshapiro ak4114_write_t * write; 16264562Sgshapiro ak4114_read_t * read; 16390792Sgshapiro void * private_data; 16490792Sgshapiro atomic_t wq_processing; 16564562Sgshapiro struct mutex reinit_mutex; 16638032Speter spinlock_t lock; 16738032Speter unsigned char regmap[6]; 16838032Speter unsigned char txcsb[5]; 16938032Speter struct snd_kcontrol *kctls[AK4114_CONTROLS]; 17038032Speter struct snd_pcm_substream *playback_substream; 17138032Speter struct snd_pcm_substream *capture_substream; 17238032Speter unsigned long errors[AK4114_NUM_ERRORS]; 17338032Speter unsigned char rcs0; 17438032Speter unsigned char rcs1; 17538032Speter struct delayed_work work; 17638032Speter unsigned int check_flags; 17738032Speter void *change_callback_private; 17838032Speter void (*change_callback)(struct ak4114 *ak4114, unsigned char c0, unsigned char c1); 17938032Speter}; 18038032Speter 18138032Speterint snd_ak4114_create(struct snd_card *card, 18238032Speter ak4114_read_t *read, ak4114_write_t *write, 18338032Speter const unsigned char pgm[6], const unsigned char txcsb[5], 18438032Speter void *private_data, struct ak4114 **r_ak4114); 18538032Spetervoid snd_ak4114_reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char mask, unsigned char val); 18638032Spetervoid snd_ak4114_reinit(struct ak4114 *ak4114); 18738032Speterint snd_ak4114_build(struct ak4114 *ak4114, 18838032Speter struct snd_pcm_substream *playback_substream, 18938032Speter struct snd_pcm_substream *capture_substream); 19038032Speterint snd_ak4114_external_rate(struct ak4114 *ak4114); 19138032Speterint snd_ak4114_check_rate_and_errors(struct ak4114 *ak4114, unsigned int flags); 19238032Speter 19338032Speter#ifdef CONFIG_PM 19438032Spetervoid snd_ak4114_suspend(struct ak4114 *chip); 19538032Spetervoid snd_ak4114_resume(struct ak4114 *chip); 19638032Speter#else 19738032Speterstatic inline void snd_ak4114_suspend(struct ak4114 *chip) {} 19838032Speterstatic inline void snd_ak4114_resume(struct ak4114 *chip) {} 19938032Speter#endif 20038032Speter 20138032Speter#endif /* __SOUND_AK4114_H */ 20238032Speter 20338032Speter