1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * QUICC Engine (QE) Internal Memory Map. 4 * The Internal Memory Map for devices with QE on them. This 5 * is the superset of all QE devices (8360, etc.). 6 7 * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved. 8 * 9 * Authors: Shlomi Gridish <gridish@freescale.com> 10 * Li Yang <leoli@freescale.com> 11 */ 12#ifndef _ASM_POWERPC_IMMAP_QE_H 13#define _ASM_POWERPC_IMMAP_QE_H 14#ifdef __KERNEL__ 15 16#include <linux/types.h> 17 18#include <asm/io.h> 19 20#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */ 21 22/* QE I-RAM */ 23struct qe_iram { 24 __be32 iadd; /* I-RAM Address Register */ 25 __be32 idata; /* I-RAM Data Register */ 26 u8 res0[0x04]; 27 __be32 iready; /* I-RAM Ready Register */ 28 u8 res1[0x70]; 29} __attribute__ ((packed)); 30 31/* QE Interrupt Controller */ 32struct qe_ic_regs { 33 __be32 qicr; 34 __be32 qivec; 35 __be32 qripnr; 36 __be32 qipnr; 37 __be32 qipxcc; 38 __be32 qipycc; 39 __be32 qipwcc; 40 __be32 qipzcc; 41 __be32 qimr; 42 __be32 qrimr; 43 __be32 qicnr; 44 u8 res0[0x4]; 45 __be32 qiprta; 46 __be32 qiprtb; 47 u8 res1[0x4]; 48 __be32 qricr; 49 u8 res2[0x20]; 50 __be32 qhivec; 51 u8 res3[0x1C]; 52} __attribute__ ((packed)); 53 54/* Communications Processor */ 55struct cp_qe { 56 __be32 cecr; /* QE command register */ 57 __be32 ceccr; /* QE controller configuration register */ 58 __be32 cecdr; /* QE command data register */ 59 u8 res0[0xA]; 60 __be16 ceter; /* QE timer event register */ 61 u8 res1[0x2]; 62 __be16 cetmr; /* QE timers mask register */ 63 __be32 cetscr; /* QE time-stamp timer control register */ 64 __be32 cetsr1; /* QE time-stamp register 1 */ 65 __be32 cetsr2; /* QE time-stamp register 2 */ 66 u8 res2[0x8]; 67 __be32 cevter; /* QE virtual tasks event register */ 68 __be32 cevtmr; /* QE virtual tasks mask register */ 69 __be16 cercr; /* QE RAM control register */ 70 u8 res3[0x2]; 71 u8 res4[0x24]; 72 __be16 ceexe1; /* QE external request 1 event register */ 73 u8 res5[0x2]; 74 __be16 ceexm1; /* QE external request 1 mask register */ 75 u8 res6[0x2]; 76 __be16 ceexe2; /* QE external request 2 event register */ 77 u8 res7[0x2]; 78 __be16 ceexm2; /* QE external request 2 mask register */ 79 u8 res8[0x2]; 80 __be16 ceexe3; /* QE external request 3 event register */ 81 u8 res9[0x2]; 82 __be16 ceexm3; /* QE external request 3 mask register */ 83 u8 res10[0x2]; 84 __be16 ceexe4; /* QE external request 4 event register */ 85 u8 res11[0x2]; 86 __be16 ceexm4; /* QE external request 4 mask register */ 87 u8 res12[0x3A]; 88 __be32 ceurnr; /* QE microcode revision number register */ 89 u8 res13[0x244]; 90} __attribute__ ((packed)); 91 92/* QE Multiplexer */ 93struct qe_mux { 94 __be32 cmxgcr; /* CMX general clock route register */ 95 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */ 96 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */ 97 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */ 98 __be32 cmxucr[4]; /* CMX UCCx clock route registers */ 99 __be32 cmxupcr; /* CMX UPC clock route register */ 100 u8 res0[0x1C]; 101} __attribute__ ((packed)); 102 103/* QE Timers */ 104struct qe_timers { 105 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/ 106 u8 res0[0x3]; 107 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/ 108 u8 res1[0xB]; 109 __be16 gtmdr1; /* Timer 1 mode register */ 110 __be16 gtmdr2; /* Timer 2 mode register */ 111 __be16 gtrfr1; /* Timer 1 reference register */ 112 __be16 gtrfr2; /* Timer 2 reference register */ 113 __be16 gtcpr1; /* Timer 1 capture register */ 114 __be16 gtcpr2; /* Timer 2 capture register */ 115 __be16 gtcnr1; /* Timer 1 counter */ 116 __be16 gtcnr2; /* Timer 2 counter */ 117 __be16 gtmdr3; /* Timer 3 mode register */ 118 __be16 gtmdr4; /* Timer 4 mode register */ 119 __be16 gtrfr3; /* Timer 3 reference register */ 120 __be16 gtrfr4; /* Timer 4 reference register */ 121 __be16 gtcpr3; /* Timer 3 capture register */ 122 __be16 gtcpr4; /* Timer 4 capture register */ 123 __be16 gtcnr3; /* Timer 3 counter */ 124 __be16 gtcnr4; /* Timer 4 counter */ 125 __be16 gtevr1; /* Timer 1 event register */ 126 __be16 gtevr2; /* Timer 2 event register */ 127 __be16 gtevr3; /* Timer 3 event register */ 128 __be16 gtevr4; /* Timer 4 event register */ 129 __be16 gtps; /* Timer 1 prescale register */ 130 u8 res2[0x46]; 131} __attribute__ ((packed)); 132 133/* BRG */ 134struct qe_brg { 135 __be32 brgc[16]; /* BRG configuration registers */ 136 u8 res0[0x40]; 137} __attribute__ ((packed)); 138 139/* SPI */ 140struct spi { 141 u8 res0[0x20]; 142 __be32 spmode; /* SPI mode register */ 143 u8 res1[0x2]; 144 u8 spie; /* SPI event register */ 145 u8 res2[0x1]; 146 u8 res3[0x2]; 147 u8 spim; /* SPI mask register */ 148 u8 res4[0x1]; 149 u8 res5[0x1]; 150 u8 spcom; /* SPI command register */ 151 u8 res6[0x2]; 152 __be32 spitd; /* SPI transmit data register (cpu mode) */ 153 __be32 spird; /* SPI receive data register (cpu mode) */ 154 u8 res7[0x8]; 155} __attribute__ ((packed)); 156 157/* SI */ 158struct si1 { 159 __be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */ 160 u8 siglmr1_h; /* SI1 global mode register high */ 161 u8 res0[0x1]; 162 u8 sicmdr1_h; /* SI1 command register high */ 163 u8 res2[0x1]; 164 u8 sistr1_h; /* SI1 status register high */ 165 u8 res3[0x1]; 166 __be16 sirsr1_h; /* SI1 RAM shadow address register high */ 167 u8 sitarc1; /* SI1 RAM counter Tx TDMA */ 168 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ 169 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ 170 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ 171 u8 sirarc1; /* SI1 RAM counter Rx TDMA */ 172 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ 173 u8 sircrc1; /* SI1 RAM counter Rx TDMC */ 174 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ 175 u8 res4[0x8]; 176 __be16 siemr1; /* SI1 TDME mode register 16 bits */ 177 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */ 178 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */ 179 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */ 180 u8 siglmg1_l; /* SI1 global mode register low 8 bits */ 181 u8 res5[0x1]; 182 u8 sicmdr1_l; /* SI1 command register low 8 bits */ 183 u8 res6[0x1]; 184 u8 sistr1_l; /* SI1 status register low 8 bits */ 185 u8 res7[0x1]; 186 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/ 187 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ 188 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ 189 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ 190 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ 191 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ 192 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ 193 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ 194 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ 195 u8 res8[0x8]; 196 __be32 siml1; /* SI1 multiframe limit register */ 197 u8 siedm1; /* SI1 extended diagnostic mode register */ 198 u8 res9[0xBB]; 199} __attribute__ ((packed)); 200 201/* SI Routing Tables */ 202struct sir { 203 u8 tx[0x400]; 204 u8 rx[0x400]; 205 u8 res0[0x800]; 206} __attribute__ ((packed)); 207 208/* USB Controller */ 209struct qe_usb_ctlr { 210 u8 usb_usmod; 211 u8 usb_usadr; 212 u8 usb_uscom; 213 u8 res1[1]; 214 __be16 usb_usep[4]; 215 u8 res2[4]; 216 __be16 usb_usber; 217 u8 res3[2]; 218 __be16 usb_usbmr; 219 u8 res4[1]; 220 u8 usb_usbs; 221 __be16 usb_ussft; 222 u8 res5[2]; 223 __be16 usb_usfrn; 224 u8 res6[0x22]; 225} __attribute__ ((packed)); 226 227/* MCC */ 228struct qe_mcc { 229 __be32 mcce; /* MCC event register */ 230 __be32 mccm; /* MCC mask register */ 231 __be32 mccf; /* MCC configuration register */ 232 __be32 merl; /* MCC emergency request level register */ 233 u8 res0[0xF0]; 234} __attribute__ ((packed)); 235 236/* QE UCC Slow */ 237struct ucc_slow { 238 __be32 gumr_l; /* UCCx general mode register (low) */ 239 __be32 gumr_h; /* UCCx general mode register (high) */ 240 __be16 upsmr; /* UCCx protocol-specific mode register */ 241 u8 res0[0x2]; 242 __be16 utodr; /* UCCx transmit on demand register */ 243 __be16 udsr; /* UCCx data synchronization register */ 244 __be16 ucce; /* UCCx event register */ 245 u8 res1[0x2]; 246 __be16 uccm; /* UCCx mask register */ 247 u8 res2[0x1]; 248 u8 uccs; /* UCCx status register */ 249 u8 res3[0x24]; 250 __be16 utpt; 251 u8 res4[0x52]; 252 u8 guemr; /* UCC general extended mode register */ 253} __attribute__ ((packed)); 254 255/* QE UCC Fast */ 256struct ucc_fast { 257 __be32 gumr; /* UCCx general mode register */ 258 __be32 upsmr; /* UCCx protocol-specific mode register */ 259 __be16 utodr; /* UCCx transmit on demand register */ 260 u8 res0[0x2]; 261 __be16 udsr; /* UCCx data synchronization register */ 262 u8 res1[0x2]; 263 __be32 ucce; /* UCCx event register */ 264 __be32 uccm; /* UCCx mask register */ 265 u8 uccs; /* UCCx status register */ 266 u8 res2[0x7]; 267 __be32 urfb; /* UCC receive FIFO base */ 268 __be16 urfs; /* UCC receive FIFO size */ 269 u8 res3[0x2]; 270 __be16 urfet; /* UCC receive FIFO emergency threshold */ 271 __be16 urfset; /* UCC receive FIFO special emergency 272 threshold */ 273 __be32 utfb; /* UCC transmit FIFO base */ 274 __be16 utfs; /* UCC transmit FIFO size */ 275 u8 res4[0x2]; 276 __be16 utfet; /* UCC transmit FIFO emergency threshold */ 277 u8 res5[0x2]; 278 __be16 utftt; /* UCC transmit FIFO transmit threshold */ 279 u8 res6[0x2]; 280 __be16 utpt; /* UCC transmit polling timer */ 281 u8 res7[0x2]; 282 __be32 urtry; /* UCC retry counter register */ 283 u8 res8[0x4C]; 284 u8 guemr; /* UCC general extended mode register */ 285} __attribute__ ((packed)); 286 287struct ucc { 288 union { 289 struct ucc_slow slow; 290 struct ucc_fast fast; 291 u8 res[0x200]; /* UCC blocks are 512 bytes each */ 292 }; 293} __attribute__ ((packed)); 294 295/* MultiPHY UTOPIA POS Controllers (UPC) */ 296struct upc { 297 __be32 upgcr; /* UTOPIA/POS general configuration register */ 298 __be32 uplpa; /* UTOPIA/POS last PHY address */ 299 __be32 uphec; /* ATM HEC register */ 300 __be32 upuc; /* UTOPIA/POS UCC configuration */ 301 __be32 updc1; /* UTOPIA/POS device 1 configuration */ 302 __be32 updc2; /* UTOPIA/POS device 2 configuration */ 303 __be32 updc3; /* UTOPIA/POS device 3 configuration */ 304 __be32 updc4; /* UTOPIA/POS device 4 configuration */ 305 __be32 upstpa; /* UTOPIA/POS STPA threshold */ 306 u8 res0[0xC]; 307 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */ 308 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */ 309 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */ 310 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */ 311 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */ 312 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */ 313 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */ 314 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */ 315 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */ 316 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */ 317 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */ 318 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */ 319 __be32 upde1; /* UTOPIA/POS device 1 event */ 320 __be32 upde2; /* UTOPIA/POS device 2 event */ 321 __be32 upde3; /* UTOPIA/POS device 3 event */ 322 __be32 upde4; /* UTOPIA/POS device 4 event */ 323 __be16 uprp1; 324 __be16 uprp2; 325 __be16 uprp3; 326 __be16 uprp4; 327 u8 res1[0x8]; 328 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */ 329 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */ 330 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */ 331 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */ 332 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */ 333 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */ 334 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */ 335 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */ 336 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */ 337 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */ 338 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */ 339 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */ 340 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */ 341 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */ 342 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */ 343 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */ 344 __be32 uper1; /* Device 1 port enable register */ 345 __be32 uper2; /* Device 2 port enable register */ 346 __be32 uper3; /* Device 3 port enable register */ 347 __be32 uper4; /* Device 4 port enable register */ 348 u8 res2[0x150]; 349} __attribute__ ((packed)); 350 351/* SDMA */ 352struct sdma { 353 __be32 sdsr; /* Serial DMA status register */ 354 __be32 sdmr; /* Serial DMA mode register */ 355 __be32 sdtr1; /* SDMA system bus threshold register */ 356 __be32 sdtr2; /* SDMA secondary bus threshold register */ 357 __be32 sdhy1; /* SDMA system bus hysteresis register */ 358 __be32 sdhy2; /* SDMA secondary bus hysteresis register */ 359 __be32 sdta1; /* SDMA system bus address register */ 360 __be32 sdta2; /* SDMA secondary bus address register */ 361 __be32 sdtm1; /* SDMA system bus MSNUM register */ 362 __be32 sdtm2; /* SDMA secondary bus MSNUM register */ 363 u8 res0[0x10]; 364 __be32 sdaqr; /* SDMA address bus qualify register */ 365 __be32 sdaqmr; /* SDMA address bus qualify mask register */ 366 u8 res1[0x4]; 367 __be32 sdebcr; /* SDMA CAM entries base register */ 368 u8 res2[0x38]; 369} __attribute__ ((packed)); 370 371/* Debug Space */ 372struct dbg { 373 __be32 bpdcr; /* Breakpoint debug command register */ 374 __be32 bpdsr; /* Breakpoint debug status register */ 375 __be32 bpdmr; /* Breakpoint debug mask register */ 376 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */ 377 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */ 378 u8 res0[0x8]; 379 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */ 380 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */ 381 u8 res1[0x8]; 382 __be32 bprmir; /* Breakpoint request mode immediate register */ 383 __be32 bprmsr; /* Breakpoint request mode serial register */ 384 __be32 bpemr; /* Breakpoint exit mode register */ 385 u8 res2[0x48]; 386} __attribute__ ((packed)); 387 388/* 389 * RISC Special Registers (Trap and Breakpoint). These are described in 390 * the QE Developer's Handbook. 391 */ 392struct rsp { 393 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */ 394 u8 res0[64]; 395 __be32 ibcr0; 396 __be32 ibs0; 397 __be32 ibcnr0; 398 u8 res1[4]; 399 __be32 ibcr1; 400 __be32 ibs1; 401 __be32 ibcnr1; 402 __be32 npcr; 403 __be32 dbcr; 404 __be32 dbar; 405 __be32 dbamr; 406 __be32 dbsr; 407 __be32 dbcnr; 408 u8 res2[12]; 409 __be32 dbdr_h; 410 __be32 dbdr_l; 411 __be32 dbdmr_h; 412 __be32 dbdmr_l; 413 __be32 bsr; 414 __be32 bor; 415 __be32 bior; 416 u8 res3[4]; 417 __be32 iatr[4]; 418 __be32 eccr; /* Exception control configuration register */ 419 __be32 eicr; 420 u8 res4[0x100-0xf8]; 421} __attribute__ ((packed)); 422 423struct qe_immap { 424 struct qe_iram iram; /* I-RAM */ 425 struct qe_ic_regs ic; /* Interrupt Controller */ 426 struct cp_qe cp; /* Communications Processor */ 427 struct qe_mux qmx; /* QE Multiplexer */ 428 struct qe_timers qet; /* QE Timers */ 429 struct spi spi[0x2]; /* spi */ 430 struct qe_mcc mcc; /* mcc */ 431 struct qe_brg brg; /* brg */ 432 struct qe_usb_ctlr usb; /* USB */ 433 struct si1 si1; /* SI */ 434 u8 res11[0x800]; 435 struct sir sir; /* SI Routing Tables */ 436 struct ucc ucc1; /* ucc1 */ 437 struct ucc ucc3; /* ucc3 */ 438 struct ucc ucc5; /* ucc5 */ 439 struct ucc ucc7; /* ucc7 */ 440 u8 res12[0x600]; 441 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/ 442 struct ucc ucc2; /* ucc2 */ 443 struct ucc ucc4; /* ucc4 */ 444 struct ucc ucc6; /* ucc6 */ 445 struct ucc ucc8; /* ucc8 */ 446 u8 res13[0x600]; 447 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/ 448 struct sdma sdma; /* SDMA */ 449 struct dbg dbg; /* 0x104080 - 0x1040FF 450 Debug Space */ 451 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF 452 RISC Special Registers 453 (Trap and Breakpoint) */ 454 u8 res14[0x300]; /* 0x104300 - 0x1045FF */ 455 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */ 456 u8 res16[0x8000]; /* 0x108000 - 0x110000 */ 457 u8 muram[0xC000]; /* 0x110000 - 0x11C000 458 Multi-user RAM */ 459 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ 460 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ 461} __attribute__ ((packed)); 462 463extern struct qe_immap __iomem *qe_immr; 464 465#endif /* __KERNEL__ */ 466#endif /* _ASM_POWERPC_IMMAP_QE_H */ 467