1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2022 Amlogic, Inc. All rights reserved.
4 */
5
6#ifndef __MESON_DDR_PMU_H__
7#define __MESON_DDR_PMU_H__
8
9#define MAX_CHANNEL_NUM		8
10
11enum {
12	ALL_CHAN_COUNTER_ID,
13	CHAN1_COUNTER_ID,
14	CHAN2_COUNTER_ID,
15	CHAN3_COUNTER_ID,
16	CHAN4_COUNTER_ID,
17	CHAN5_COUNTER_ID,
18	CHAN6_COUNTER_ID,
19	CHAN7_COUNTER_ID,
20	CHAN8_COUNTER_ID,
21	COUNTER_MAX_ID,
22};
23
24struct dmc_info;
25
26struct dmc_counter {
27	u64 all_cnt;	/* The count of all requests come in/out ddr controller */
28	union {
29		u64 all_req;
30		struct {
31			u64 all_idle_cnt;
32			u64 all_16bit_cnt;
33		};
34	};
35	u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
36};
37
38struct dmc_hw_info {
39	void (*enable)(struct dmc_info *info);
40	void (*disable)(struct dmc_info *info);
41	/* Bind an axi line to a bandwidth-monitor channel */
42	void (*set_axi_filter)(struct dmc_info *info, int axi_id, int chann);
43	int (*irq_handler)(struct dmc_info *info,
44			   struct dmc_counter *counter);
45	void (*get_counters)(struct dmc_info *info,
46			     struct dmc_counter *counter);
47
48	int dmc_nr;			/* The number of dmc controller */
49	int chann_nr;			/* The number of dmc bandwidth monitor channels */
50	struct attribute **fmt_attr;
51	const u64 capability[2];
52};
53
54struct dmc_info {
55	const struct dmc_hw_info *hw_info;
56
57	void __iomem *ddr_reg[4];
58	unsigned long timer_value;	/* Timer value in TIMER register */
59	void __iomem *pll_reg;
60	int irq_num;			/* irq vector number */
61};
62
63int meson_ddr_pmu_create(struct platform_device *pdev);
64int meson_ddr_pmu_remove(struct platform_device *pdev);
65
66#endif /* __MESON_DDR_PMU_H__ */
67