1/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3/*
4 *   cx25840.h - definition for cx25840/1/2/3 inputs
5 *
6 *   Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
7 */
8
9#ifndef _CX25840_H_
10#define _CX25840_H_
11
12/*
13 * Note that the cx25840 driver requires that the bridge driver calls the
14 * v4l2_subdev's load_fw operation in order to load the driver's firmware.
15 * This will load the firmware on the first invocation (further ones are NOP).
16 * Without this the audio standard detection will fail and you will
17 * only get mono.
18 * Alternatively, you can call the reset operation (this can be done
19 * multiple times if needed, each invocation will fully reinitialize
20 * the device).
21 *
22 * Since loading the firmware is often problematic when the driver is
23 * compiled into the kernel I recommend postponing calling this function
24 * until the first open of the video device. Another reason for
25 * postponing it is that loading this firmware takes a long time (seconds)
26 * due to the slow i2c bus speed. So it will speed up the boot process if
27 * you can avoid loading the fw as long as the video device isn't used.
28 */
29
30enum cx25840_video_input {
31	/* Composite video inputs In1-In8 */
32	CX25840_COMPOSITE1 = 1,
33	CX25840_COMPOSITE2,
34	CX25840_COMPOSITE3,
35	CX25840_COMPOSITE4,
36	CX25840_COMPOSITE5,
37	CX25840_COMPOSITE6,
38	CX25840_COMPOSITE7,
39	CX25840_COMPOSITE8,
40
41	/*
42	 * S-Video inputs consist of one luma input (In1-In8) ORed with one
43	 * chroma input (In5-In8)
44	 */
45	CX25840_SVIDEO_LUMA1 = 0x10,
46	CX25840_SVIDEO_LUMA2 = 0x20,
47	CX25840_SVIDEO_LUMA3 = 0x30,
48	CX25840_SVIDEO_LUMA4 = 0x40,
49	CX25840_SVIDEO_LUMA5 = 0x50,
50	CX25840_SVIDEO_LUMA6 = 0x60,
51	CX25840_SVIDEO_LUMA7 = 0x70,
52	CX25840_SVIDEO_LUMA8 = 0x80,
53	CX25840_SVIDEO_CHROMA4 = 0x400,
54	CX25840_SVIDEO_CHROMA5 = 0x500,
55	CX25840_SVIDEO_CHROMA6 = 0x600,
56	CX25840_SVIDEO_CHROMA7 = 0x700,
57	CX25840_SVIDEO_CHROMA8 = 0x800,
58
59	/* S-Video aliases for common luma/chroma combinations */
60	CX25840_SVIDEO1 = 0x510,
61	CX25840_SVIDEO2 = 0x620,
62	CX25840_SVIDEO3 = 0x730,
63	CX25840_SVIDEO4 = 0x840,
64
65	/* Allow frames to specify specific input configurations */
66	CX25840_VIN1_CH1  = 0x80000000,
67	CX25840_VIN2_CH1  = 0x80000001,
68	CX25840_VIN3_CH1  = 0x80000002,
69	CX25840_VIN4_CH1  = 0x80000003,
70	CX25840_VIN5_CH1  = 0x80000004,
71	CX25840_VIN6_CH1  = 0x80000005,
72	CX25840_VIN7_CH1  = 0x80000006,
73	CX25840_VIN8_CH1  = 0x80000007,
74	CX25840_VIN4_CH2  = 0x80000000,
75	CX25840_VIN5_CH2  = 0x80000010,
76	CX25840_VIN6_CH2  = 0x80000020,
77	CX25840_NONE_CH2  = 0x80000030,
78	CX25840_VIN7_CH3  = 0x80000000,
79	CX25840_VIN8_CH3  = 0x80000040,
80	CX25840_NONE0_CH3 = 0x80000080,
81	CX25840_NONE1_CH3 = 0x800000c0,
82	CX25840_SVIDEO_ON = 0x80000100,
83	CX25840_COMPONENT_ON = 0x80000200,
84	CX25840_DIF_ON = 0x80000400,
85};
86
87/*
88 * The defines below are used to set the chip video output settings
89 * in the generic mode that can be enabled by calling the subdevice
90 * init core op.
91 *
92 * The requested settings can be passed to the init core op as
93 * @val parameter and to the s_routing video op as @config parameter.
94 *
95 * For details please refer to the section 3.7 Video Output Formatting and
96 * to Video Out Control 1 to 4 registers in the section 5.6 Video Decoder Core
97 * of the chip datasheet.
98 */
99#define CX25840_VCONFIG_FMT_SHIFT 0
100#define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
101#define CX25840_VCONFIG_FMT_BT601 BIT(0)
102#define CX25840_VCONFIG_FMT_BT656 BIT(1)
103#define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
104#define CX25840_VCONFIG_FMT_VIP2 BIT(2)
105
106#define CX25840_VCONFIG_RES_SHIFT 3
107#define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
108#define CX25840_VCONFIG_RES_8BIT BIT(3)
109#define CX25840_VCONFIG_RES_10BIT BIT(4)
110
111#define CX25840_VCONFIG_VBIRAW_SHIFT 5
112#define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
113#define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5)
114#define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6)
115
116#define CX25840_VCONFIG_ANCDATA_SHIFT 7
117#define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
118#define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7)
119#define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8)
120
121#define CX25840_VCONFIG_TASKBIT_SHIFT 9
122#define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
123#define CX25840_VCONFIG_TASKBIT_ZERO BIT(9)
124#define CX25840_VCONFIG_TASKBIT_ONE BIT(10)
125
126#define CX25840_VCONFIG_ACTIVE_SHIFT 11
127#define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
128#define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11)
129#define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12)
130
131#define CX25840_VCONFIG_VALID_SHIFT 13
132#define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
133#define CX25840_VCONFIG_VALID_NORMAL BIT(13)
134#define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14)
135
136#define CX25840_VCONFIG_HRESETW_SHIFT 15
137#define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
138#define CX25840_VCONFIG_HRESETW_NORMAL BIT(15)
139#define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16)
140
141#define CX25840_VCONFIG_CLKGATE_SHIFT 17
142#define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
143#define CX25840_VCONFIG_CLKGATE_NONE BIT(17)
144#define CX25840_VCONFIG_CLKGATE_VALID BIT(18)
145#define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)
146
147#define CX25840_VCONFIG_DCMODE_SHIFT 19
148#define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
149#define CX25840_VCONFIG_DCMODE_DWORDS BIT(19)
150#define CX25840_VCONFIG_DCMODE_BYTES BIT(20)
151
152#define CX25840_VCONFIG_IDID0S_SHIFT 21
153#define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)
154#define CX25840_VCONFIG_IDID0S_NORMAL BIT(21)
155#define CX25840_VCONFIG_IDID0S_LINECNT BIT(22)
156
157#define CX25840_VCONFIG_VIPCLAMP_SHIFT 23
158#define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)
159#define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23)
160#define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24)
161
162enum cx25840_audio_input {
163	/* Audio inputs: serial or In4-In8 */
164	CX25840_AUDIO_SERIAL,
165	CX25840_AUDIO4 = 4,
166	CX25840_AUDIO5,
167	CX25840_AUDIO6,
168	CX25840_AUDIO7,
169	CX25840_AUDIO8,
170};
171
172enum cx25840_io_pin {
173	CX25840_PIN_DVALID_PRGM0 = 0,
174	CX25840_PIN_FIELD_PRGM1,
175	CX25840_PIN_HRESET_PRGM2,
176	CX25840_PIN_VRESET_HCTL_PRGM3,
177	CX25840_PIN_IRQ_N_PRGM4,
178	CX25840_PIN_IR_TX_PRGM6,
179	CX25840_PIN_IR_RX_PRGM5,
180	CX25840_PIN_GPIO0_PRGM8,
181	CX25840_PIN_GPIO1_PRGM9,
182	CX25840_PIN_SA_SDIN,		/* Alternate GP Input only */
183	CX25840_PIN_SA_SDOUT,		/* Alternate GP Input only */
184	CX25840_PIN_PLL_CLK_PRGM7,
185	CX25840_PIN_CHIP_SEL_VIPCLK,	/* Output only */
186};
187
188enum cx25840_io_pad {
189	/* Output pads, these must match the actual chip register values */
190	CX25840_PAD_DEFAULT = 0,
191	CX25840_PAD_ACTIVE,
192	CX25840_PAD_VACTIVE,
193	CX25840_PAD_CBFLAG,
194	CX25840_PAD_VID_DATA_EXT0,
195	CX25840_PAD_VID_DATA_EXT1,
196	CX25840_PAD_GPO0,
197	CX25840_PAD_GPO1,
198	CX25840_PAD_GPO2,
199	CX25840_PAD_GPO3,
200	CX25840_PAD_IRQ_N,
201	CX25840_PAD_AC_SYNC,
202	CX25840_PAD_AC_SDOUT,
203	CX25840_PAD_PLL_CLK,
204	CX25840_PAD_VRESET,
205	CX25840_PAD_RESERVED,
206	/* Pads for PLL_CLK output only */
207	CX25840_PAD_XTI_X5_DLL,
208	CX25840_PAD_AUX_PLL,
209	CX25840_PAD_VID_PLL,
210	CX25840_PAD_XTI,
211	/* Input Pads */
212	CX25840_PAD_GPI0,
213	CX25840_PAD_GPI1,
214	CX25840_PAD_GPI2,
215	CX25840_PAD_GPI3,
216};
217
218enum cx25840_io_pin_strength {
219	CX25840_PIN_DRIVE_MEDIUM = 0,
220	CX25840_PIN_DRIVE_SLOW,
221	CX25840_PIN_DRIVE_FAST,
222};
223
224enum cx23885_io_pin {
225	CX23885_PIN_IR_RX_GPIO19,
226	CX23885_PIN_IR_TX_GPIO20,
227	CX23885_PIN_I2S_SDAT_GPIO21,
228	CX23885_PIN_I2S_WCLK_GPIO22,
229	CX23885_PIN_I2S_BCLK_GPIO23,
230	CX23885_PIN_IRQ_N_GPIO16,
231};
232
233enum cx23885_io_pad {
234	CX23885_PAD_IR_RX,
235	CX23885_PAD_GPIO19,
236	CX23885_PAD_IR_TX,
237	CX23885_PAD_GPIO20,
238	CX23885_PAD_I2S_SDAT,
239	CX23885_PAD_GPIO21,
240	CX23885_PAD_I2S_WCLK,
241	CX23885_PAD_GPIO22,
242	CX23885_PAD_I2S_BCLK,
243	CX23885_PAD_GPIO23,
244	CX23885_PAD_IRQ_N,
245	CX23885_PAD_GPIO16,
246};
247
248/*
249 * pvr150_workaround activates a workaround for a hardware bug that is
250 * present in Hauppauge PVR-150 (and possibly PVR-500) cards that have
251 * certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The
252 * audio autodetect fails on some channels for these models and the workaround
253 * is to select the audio standard explicitly. Many thanks to Hauppauge for
254 * providing this information.
255 *
256 * This platform data only needs to be supplied by the ivtv driver.
257 */
258struct cx25840_platform_data {
259	int pvr150_workaround;
260};
261
262#endif
263