1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __SUNGEM_PHY_H__ 3#define __SUNGEM_PHY_H__ 4 5#include <linux/types.h> 6 7struct mii_phy; 8 9/* Operations supported by any kind of PHY */ 10struct mii_phy_ops 11{ 12 int (*init)(struct mii_phy *phy); 13 int (*suspend)(struct mii_phy *phy); 14 int (*setup_aneg)(struct mii_phy *phy, u32 advertise); 15 int (*setup_forced)(struct mii_phy *phy, int speed, int fd); 16 int (*poll_link)(struct mii_phy *phy); 17 int (*read_link)(struct mii_phy *phy); 18 int (*enable_fiber)(struct mii_phy *phy, int autoneg); 19}; 20 21/* Structure used to statically define an mii/gii based PHY */ 22struct mii_phy_def 23{ 24 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */ 25 u32 phy_id_mask; /* Significant bits */ 26 u32 features; /* Ethtool SUPPORTED_* defines */ 27 int magic_aneg; /* Autoneg does all speed test for us */ 28 const char* name; 29 const struct mii_phy_ops* ops; 30}; 31 32enum { 33 BCM54XX_COPPER, 34 BCM54XX_FIBER, 35 BCM54XX_GBIC, 36 BCM54XX_SGMII, 37 BCM54XX_UNKNOWN, 38}; 39 40/* An instance of a PHY, partially borrowed from mii_if_info */ 41struct mii_phy 42{ 43 struct mii_phy_def* def; 44 u32 advertising; 45 int mii_id; 46 47 /* 1: autoneg enabled, 0: disabled */ 48 int autoneg; 49 50 /* forced speed & duplex (no autoneg) 51 * partner speed & duplex & pause (autoneg) 52 */ 53 int speed; 54 int duplex; 55 int pause; 56 57 /* Provided by host chip */ 58 struct net_device *dev; 59 int (*mdio_read) (struct net_device *dev, int mii_id, int reg); 60 void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val); 61 void *platform_data; 62}; 63 64/* Pass in a struct mii_phy with dev, mdio_read and mdio_write 65 * filled, the remaining fields will be filled on return 66 */ 67extern int sungem_phy_probe(struct mii_phy *phy, int mii_id); 68 69 70/* MII definitions missing from mii.h */ 71 72#define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */ 73#define LPA_PAUSE 0x0400 74 75/* More PHY registers (model specific) */ 76 77/* MII BCM5201 MULTIPHY interrupt register */ 78#define MII_BCM5201_INTERRUPT 0x1A 79#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 80 81#define MII_BCM5201_AUXMODE2 0x1B 82#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 83 84#define MII_BCM5201_MULTIPHY 0x1E 85 86/* MII BCM5201 MULTIPHY register bits */ 87#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 88#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 89 90/* MII BCM5221 Additional registers */ 91#define MII_BCM5221_TEST 0x1f 92#define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080 93#define MII_BCM5221_SHDOW_AUX_STAT2 0x1b 94#define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020 95#define MII_BCM5221_SHDOW_AUX_MODE4 0x1a 96#define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001 97#define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004 98 99/* MII BCM5241 Additional registers */ 100#define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR 0x0008 101 102/* MII BCM5400 1000-BASET Control register */ 103#define MII_BCM5400_GB_CONTROL 0x09 104#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 105 106/* MII BCM5400 AUXCONTROL register */ 107#define MII_BCM5400_AUXCONTROL 0x18 108#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 109 110/* MII BCM5400 AUXSTATUS register */ 111#define MII_BCM5400_AUXSTATUS 0x19 112#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 113#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 114 115/* 1000BT control (Marvell & BCM54xx at least) */ 116#define MII_1000BASETCONTROL 0x09 117#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 118#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 119 120/* Marvell 88E1011 PHY control */ 121#define MII_M1011_PHY_SPEC_CONTROL 0x10 122#define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20 123#define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40 124 125/* Marvell 88E1011 PHY status */ 126#define MII_M1011_PHY_SPEC_STATUS 0x11 127#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 128#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 129#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 130#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 131#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 132#define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008 133#define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004 134 135#endif /* __SUNGEM_PHY_H__ */ 136