1/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef __ASM_ARCH_OMAP_IO_H
3#define __ASM_ARCH_OMAP_IO_H
4
5#ifndef __ASSEMBLER__
6#include <linux/types.h>
7
8#ifdef CONFIG_ARCH_OMAP1
9/*
10 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
11 */
12extern u8 omap_readb(u32 pa);
13extern u16 omap_readw(u32 pa);
14extern u32 omap_readl(u32 pa);
15extern void omap_writeb(u8 v, u32 pa);
16extern void omap_writew(u16 v, u32 pa);
17extern void omap_writel(u32 v, u32 pa);
18#elif defined(CONFIG_COMPILE_TEST)
19static inline u8 omap_readb(u32 pa)  { return 0; }
20static inline u16 omap_readw(u32 pa) { return 0; }
21static inline u32 omap_readl(u32 pa) { return 0; }
22static inline void omap_writeb(u8 v, u32 pa)   { }
23static inline void omap_writew(u16 v, u32 pa)  { }
24static inline void omap_writel(u32 v, u32 pa)  { }
25#endif
26#endif
27
28/*
29 * ----------------------------------------------------------------------------
30 * System control registers
31 * ----------------------------------------------------------------------------
32 */
33#define MOD_CONF_CTRL_0		0xfffe1080
34#define MOD_CONF_CTRL_1		0xfffe1110
35
36/*
37 * ---------------------------------------------------------------------------
38 * UPLD
39 * ---------------------------------------------------------------------------
40 */
41#define ULPD_REG_BASE		(0xfffe0800)
42#define ULPD_IT_STATUS		(ULPD_REG_BASE + 0x14)
43#define ULPD_SETUP_ANALOG_CELL_3	(ULPD_REG_BASE + 0x24)
44#define ULPD_CLOCK_CTRL		(ULPD_REG_BASE + 0x30)
45#	define DIS_USB_PVCI_CLK		(1 << 5)	/* no USB/FAC synch */
46#	define USB_MCLK_EN		(1 << 4)	/* enable W4_USB_CLKO */
47#define ULPD_SOFT_REQ		(ULPD_REG_BASE + 0x34)
48#	define SOFT_UDC_REQ		(1 << 4)
49#	define SOFT_USB_CLK_REQ		(1 << 3)
50#	define SOFT_DPLL_REQ		(1 << 0)
51#define ULPD_DPLL_CTRL		(ULPD_REG_BASE + 0x3c)
52#define ULPD_STATUS_REQ		(ULPD_REG_BASE + 0x40)
53#define ULPD_APLL_CTRL		(ULPD_REG_BASE + 0x4c)
54#define ULPD_POWER_CTRL		(ULPD_REG_BASE + 0x50)
55#define ULPD_SOFT_DISABLE_REQ_REG	(ULPD_REG_BASE + 0x68)
56#	define DIS_MMC2_DPLL_REQ	(1 << 11)
57#	define DIS_MMC1_DPLL_REQ	(1 << 10)
58#	define DIS_UART3_DPLL_REQ	(1 << 9)
59#	define DIS_UART2_DPLL_REQ	(1 << 8)
60#	define DIS_UART1_DPLL_REQ	(1 << 7)
61#	define DIS_USB_HOST_DPLL_REQ	(1 << 6)
62#define ULPD_SDW_CLK_DIV_CTRL_SEL	(ULPD_REG_BASE + 0x74)
63#define ULPD_CAM_CLK_CTRL	(ULPD_REG_BASE + 0x7c)
64
65/*
66 * ----------------------------------------------------------------------------
67 * Clocks
68 * ----------------------------------------------------------------------------
69 */
70#define CLKGEN_REG_BASE		(0xfffece00)
71#define ARM_CKCTL		(CLKGEN_REG_BASE + 0x0)
72#define ARM_IDLECT1		(CLKGEN_REG_BASE + 0x4)
73#define ARM_IDLECT2		(CLKGEN_REG_BASE + 0x8)
74#define ARM_EWUPCT		(CLKGEN_REG_BASE + 0xC)
75#define ARM_RSTCT1		(CLKGEN_REG_BASE + 0x10)
76#define ARM_RSTCT2		(CLKGEN_REG_BASE + 0x14)
77#define ARM_SYSST		(CLKGEN_REG_BASE + 0x18)
78#define ARM_IDLECT3		(CLKGEN_REG_BASE + 0x24)
79
80#define CK_RATEF		1
81#define CK_IDLEF		2
82#define CK_ENABLEF		4
83#define CK_SELECTF		8
84#define SETARM_IDLE_SHIFT
85
86/* DPLL control registers */
87#define DPLL_CTL		(0xfffecf00)
88
89/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
90#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
91#define DSP_CKCTL		(DSP_CONFIG_REG_BASE + 0x0)
92#define DSP_IDLECT1		(DSP_CONFIG_REG_BASE + 0x4)
93#define DSP_IDLECT2		(DSP_CONFIG_REG_BASE + 0x8)
94#define DSP_RSTCT2		(DSP_CONFIG_REG_BASE + 0x14)
95
96/*
97 * ----------------------------------------------------------------------------
98 * Pulse-Width Light
99 * ----------------------------------------------------------------------------
100 */
101#define OMAP_PWL_BASE			0xfffb5800
102#define OMAP_PWL_ENABLE			(OMAP_PWL_BASE + 0x00)
103#define OMAP_PWL_CLK_ENABLE		(OMAP_PWL_BASE + 0x04)
104
105/*
106 * ----------------------------------------------------------------------------
107 * Pin multiplexing registers
108 * ----------------------------------------------------------------------------
109 */
110#define FUNC_MUX_CTRL_0		0xfffe1000
111#define FUNC_MUX_CTRL_1		0xfffe1004
112#define FUNC_MUX_CTRL_2		0xfffe1008
113#define COMP_MODE_CTRL_0	0xfffe100c
114#define FUNC_MUX_CTRL_3		0xfffe1010
115#define FUNC_MUX_CTRL_4		0xfffe1014
116#define FUNC_MUX_CTRL_5		0xfffe1018
117#define FUNC_MUX_CTRL_6		0xfffe101C
118#define FUNC_MUX_CTRL_7		0xfffe1020
119#define FUNC_MUX_CTRL_8		0xfffe1024
120#define FUNC_MUX_CTRL_9		0xfffe1028
121#define FUNC_MUX_CTRL_A		0xfffe102C
122#define FUNC_MUX_CTRL_B		0xfffe1030
123#define FUNC_MUX_CTRL_C		0xfffe1034
124#define FUNC_MUX_CTRL_D		0xfffe1038
125#define PULL_DWN_CTRL_0		0xfffe1040
126#define PULL_DWN_CTRL_1		0xfffe1044
127#define PULL_DWN_CTRL_2		0xfffe1048
128#define PULL_DWN_CTRL_3		0xfffe104c
129#define PULL_DWN_CTRL_4		0xfffe10ac
130
131/* OMAP-1610 specific multiplexing registers */
132#define FUNC_MUX_CTRL_E		0xfffe1090
133#define FUNC_MUX_CTRL_F		0xfffe1094
134#define FUNC_MUX_CTRL_10	0xfffe1098
135#define FUNC_MUX_CTRL_11	0xfffe109c
136#define FUNC_MUX_CTRL_12	0xfffe10a0
137#define PU_PD_SEL_0		0xfffe10b4
138#define PU_PD_SEL_1		0xfffe10b8
139#define PU_PD_SEL_2		0xfffe10bc
140#define PU_PD_SEL_3		0xfffe10c0
141#define PU_PD_SEL_4		0xfffe10c4
142
143#endif
144