11590Srgrimes/* SPDX-License-Identifier: GPL-2.0-only */ 239230Sgibbs/* 339230Sgibbs * Definitions for the registers, addresses, and platform data of the 439230Sgibbs * DS1685/DS1687-series RTC chips. 539230Sgibbs * 639230Sgibbs * This Driver also works for the DS17X85/DS17X87 RTC chips. Functionally 739230Sgibbs * similar to the DS1685/DS1687, they support a few extra features which 839230Sgibbs * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC 939230Sgibbs * write counter. 1039230Sgibbs * 1139230Sgibbs * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>. 1239230Sgibbs * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>. 1339230Sgibbs * 1439230Sgibbs * References: 1539230Sgibbs * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. 1639230Sgibbs * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. 1739230Sgibbs * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. 1839230Sgibbs * Application Note 90, Using the Multiplex Bus RTC Extended Features. 1939230Sgibbs */ 2039230Sgibbs 2139230Sgibbs#ifndef _LINUX_RTC_DS1685_H_ 2239230Sgibbs#define _LINUX_RTC_DS1685_H_ 2339230Sgibbs 2439230Sgibbs#include <linux/rtc.h> 2539230Sgibbs#include <linux/platform_device.h> 2639230Sgibbs#include <linux/workqueue.h> 2739230Sgibbs 2839230Sgibbs/** 291590Srgrimes * struct ds1685_priv - DS1685 private data structure. 301590Srgrimes * @dev: pointer to the rtc_device structure. 311590Srgrimes * @regs: iomapped base address pointer of the RTC registers. 321590Srgrimes * @regstep: padding/step size between registers (optional). 331590Srgrimes * @baseaddr: base address of the RTC device. 341590Srgrimes * @size: resource size. 351590Srgrimes * @lock: private lock variable for spin locking/unlocking. 361590Srgrimes * @work: private workqueue. 371590Srgrimes * @irq: IRQ number assigned to the RTC device. 381590Srgrimes * @prepare_poweroff: pointer to platform pre-poweroff function. 391590Srgrimes * @wake_alarm: pointer to platform wake alarm function. 401590Srgrimes * @post_ram_clear: pointer to platform post ram-clear function. 411590Srgrimes */ 421590Srgrimesstruct ds1685_priv { 431590Srgrimes struct rtc_device *dev; 441590Srgrimes void __iomem *regs; 451590Srgrimes void __iomem *data; 461590Srgrimes u32 regstep; 471590Srgrimes int irq_num; 481590Srgrimes bool bcd_mode; 491590Srgrimes u8 (*read)(struct ds1685_priv *, int); 501590Srgrimes void (*write)(struct ds1685_priv *, int, u8); 511590Srgrimes void (*prepare_poweroff)(void); 521590Srgrimes void (*wake_alarm)(void); 531590Srgrimes void (*post_ram_clear)(void); 541590Srgrimes}; 551590Srgrimes 561590Srgrimes 571590Srgrimes/** 581590Srgrimes * struct ds1685_rtc_platform_data - platform data structure. 591590Srgrimes * @plat_prepare_poweroff: platform-specific pre-poweroff function. 601590Srgrimes * @plat_wake_alarm: platform-specific wake alarm function. 6187715Smarkm * @plat_post_ram_clear: platform-specific post ram-clear function. 621590Srgrimes * 6387715Smarkm * If your platform needs to use a custom padding/step size between 6487715Smarkm * registers, or uses one or more of the extended interrupts and needs special 6587715Smarkm * handling, then include this header file in your platform definition and 6687715Smarkm * set regstep and the plat_* pointers as appropriate. 6787715Smarkm */ 6887715Smarkmstruct ds1685_rtc_platform_data { 691590Srgrimes const u32 regstep; 7074671Stmm const bool bcd_mode; 71111007Sphk const bool no_irq; 721590Srgrimes const bool uie_unsupported; 7387715Smarkm void (*plat_prepare_poweroff)(void); 7487715Smarkm void (*plat_wake_alarm)(void); 751590Srgrimes void (*plat_post_ram_clear)(void); 761590Srgrimes enum { 7787715Smarkm ds1685_reg_direct, 7887715Smarkm ds1685_reg_indirect 7987715Smarkm } access_type; 801590Srgrimes}; 811590Srgrimes 8240060Sobrien 831590Srgrimes/* 8439230Sgibbs * Time Registers. 851590Srgrimes */ 861590Srgrimes#define RTC_SECS 0x00 /* Seconds 00-59 */ 871590Srgrimes#define RTC_SECS_ALARM 0x01 /* Alarm Seconds 00-59 */ 881590Srgrimes#define RTC_MINS 0x02 /* Minutes 00-59 */ 8939230Sgibbs#define RTC_MINS_ALARM 0x03 /* Alarm Minutes 00-59 */ 901590Srgrimes#define RTC_HRS 0x04 /* Hours 01-12 AM/PM || 00-23 */ 9192922Simp#define RTC_HRS_ALARM 0x05 /* Alarm Hours 01-12 AM/PM || 00-23 */ 9292922Simp#define RTC_WDAY 0x06 /* Day of Week 01-07 */ 9392922Simp#define RTC_MDAY 0x07 /* Day of Month 01-31 */ 9492922Simp#define RTC_MONTH 0x08 /* Month 01-12 */ 9592922Simp#define RTC_YEAR 0x09 /* Year 00-99 */ 961590Srgrimes#define RTC_CENTURY 0x48 /* Century 00-99 */ 971590Srgrimes#define RTC_MDAY_ALARM 0x49 /* Alarm Day of Month 01-31 */ 981590Srgrimes 991590Srgrimes 100158160Sbde/* 1011590Srgrimes * Bit masks for the Time registers in BCD Mode (DM = 0). 1021590Srgrimes */ 1031590Srgrimes#define RTC_SECS_BCD_MASK 0x7f /* - x x x x x x x */ 1041590Srgrimes#define RTC_MINS_BCD_MASK 0x7f /* - x x x x x x x */ 1051590Srgrimes#define RTC_HRS_12_BCD_MASK 0x1f /* - - - x x x x x */ 1061590Srgrimes#define RTC_HRS_24_BCD_MASK 0x3f /* - - x x x x x x */ 1071590Srgrimes#define RTC_MDAY_BCD_MASK 0x3f /* - - x x x x x x */ 1081590Srgrimes#define RTC_MONTH_BCD_MASK 0x1f /* - - - x x x x x */ 1091590Srgrimes#define RTC_YEAR_BCD_MASK 0xff /* x x x x x x x x */ 1101590Srgrimes 1111590Srgrimes/* 1121590Srgrimes * Bit masks for the Time registers in BIN Mode (DM = 1). 1131590Srgrimes */ 1141590Srgrimes#define RTC_SECS_BIN_MASK 0x3f /* - - x x x x x x */ 1151590Srgrimes#define RTC_MINS_BIN_MASK 0x3f /* - - x x x x x x */ 1161590Srgrimes#define RTC_HRS_12_BIN_MASK 0x0f /* - - - - x x x x */ 11783131Sken#define RTC_HRS_24_BIN_MASK 0x1f /* - - - x x x x x */ 1181590Srgrimes#define RTC_MDAY_BIN_MASK 0x1f /* - - - x x x x x */ 11939230Sgibbs#define RTC_MONTH_BIN_MASK 0x0f /* - - - - x x x x */ 12039230Sgibbs#define RTC_YEAR_BIN_MASK 0x7f /* - x x x x x x x */ 12139230Sgibbs 12239230Sgibbs/* 12339230Sgibbs * Bit masks common for the Time registers in BCD or BIN Mode. 12439230Sgibbs */ 12539230Sgibbs#define RTC_WDAY_MASK 0x07 /* - - - - - x x x */ 12639230Sgibbs#define RTC_CENTURY_MASK 0xff /* x x x x x x x x */ 12739230Sgibbs#define RTC_MDAY_ALARM_MASK 0xff /* x x x x x x x x */ 12839230Sgibbs#define RTC_HRS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */ 12939230Sgibbs 13039230Sgibbs 13139230Sgibbs 1321590Srgrimes/* 1331590Srgrimes * Control Registers. 1341590Srgrimes */ 1351590Srgrimes#define RTC_CTRL_A 0x0a /* Control Register A */ 1361590Srgrimes#define RTC_CTRL_B 0x0b /* Control Register B */ 1371590Srgrimes#define RTC_CTRL_C 0x0c /* Control Register C */ 13839230Sgibbs#define RTC_CTRL_D 0x0d /* Control Register D */ 13969141Srwatson#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */ 14039230Sgibbs#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */ 14169141Srwatson 14287715Smarkm 14387715Smarkm/* 14469141Srwatson * Bit names in Control Register A. 14569141Srwatson */ 14669141Srwatson#define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */ 14739230Sgibbs#define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */ 14839230Sgibbs#define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */ 14939230Sgibbs#define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */ 150121836Stjr#define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */ 151121836Stjr#define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */ 15239230Sgibbs#define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */ 15339230Sgibbs#define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */ 15439230Sgibbs#define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */ 15539230Sgibbs 15639230Sgibbs/* 15739230Sgibbs * Bit names in Control Register B. 15839230Sgibbs */ 15939230Sgibbs#define RTC_CTRL_B_SET BIT(7) /* SET Bit */ 16083131Sken#define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */ 16139230Sgibbs#define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */ 16239230Sgibbs#define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */ 16339230Sgibbs#define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */ 16439230Sgibbs#define RTC_CTRL_B_DM BIT(2) /* Data Mode */ 16539230Sgibbs#define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */ 16639230Sgibbs#define RTC_CTRL_B_DSE BIT(0) /* Daylight Savings Enable */ 16739230Sgibbs#define RTC_CTRL_B_PAU_MASK 0x70 /* PIE + AIE + UIE */ 16839230Sgibbs 16939230Sgibbs 17039230Sgibbs/* 17139230Sgibbs * Bit names in Control Register C. 17239230Sgibbs * 1731590Srgrimes * BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot 1741590Srgrimes * be written to. 1751590Srgrimes */ 1761590Srgrimes#define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */ 1771590Srgrimes#define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */ 1781590Srgrimes#define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */ 1791590Srgrimes#define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */ 1801590Srgrimes#define RTC_CTRL_C_PAU_MASK 0x70 /* PF + AF + UF */ 1811590Srgrimes 1821590Srgrimes 1831590Srgrimes/* 1841590Srgrimes * Bit names in Control Register D. 1851590Srgrimes * 1861590Srgrimes * BIT(0) through BIT(6) are unused, always return 0, and cannot 1871590Srgrimes * be written to. 1881590Srgrimes */ 1894930Sbde#define RTC_CTRL_D_VRT BIT(7) /* Valid RAM and Time */ 1901590Srgrimes 1911590Srgrimes 1921590Srgrimes/* 1931590Srgrimes * Bit names in Extended Control Register 4A. 1941590Srgrimes * 1951590Srgrimes * On the DS1685/DS1687/DS1689/DS1693, BIT(4) and BIT(5) are reserved for 1961590Srgrimes * future use. They can be read from and written to, but have no effect 1971590Srgrimes * on the RTC's operation. 1981590Srgrimes * 1991590Srgrimes * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows 2001590Srgrimes * access to the extended NV-SRAM by automatically incrementing the address 20187715Smarkm * register when they are read from or written to. 20239230Sgibbs */ 2031590Srgrimes#define RTC_CTRL_4A_VRT2 BIT(7) /* Auxillary Battery Status */ 20439230Sgibbs#define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */ 20550635Speter#define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */ 20639230Sgibbs#define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */ 20739230Sgibbs#define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */ 2081590Srgrimes#define RTC_CTRL_4A_KF BIT(0) /* Kickstart Flag */ 2091590Srgrimes#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) 2101590Srgrimes#define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */ 2111590Srgrimes#endif 2121590Srgrimes#define RTC_CTRL_4A_RWK_MASK 0x07 /* RF + WF + KF */ 21350635Speter 2141590Srgrimes 2151590Srgrimes/* 2161590Srgrimes * Bit names in Extended Control Register 4B. 2171590Srgrimes */ 2181590Srgrimes#define RTC_CTRL_4B_ABE BIT(7) /* Auxillary Battery Enable */ 2191590Srgrimes#define RTC_CTRL_4B_E32K BIT(6) /* Enable 32.768Hz on SQW Pin */ 22087715Smarkm#define RTC_CTRL_4B_CS BIT(5) /* Crystal Select */ 22139230Sgibbs#define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */ 22239230Sgibbs#define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */ 22387715Smarkm#define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */ 22487715Smarkm#define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */ 22550635Speter#define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */ 2261590Srgrimes#define RTC_CTRL_4B_RWK_MASK 0x07 /* RIE + WIE + KSE */ 2271590Srgrimes 22839230Sgibbs 22939230Sgibbs/* 23087715Smarkm * Misc register names in Bank 1. 23187715Smarkm * 23287715Smarkm * The DV0 bit in Control Register A must be set to 1 for these registers 2331590Srgrimes * to become available, including Extended Control Registers 4A & 4B. 23487715Smarkm */ 2351590Srgrimes#define RTC_BANK1_SSN_MODEL 0x40 /* Model Number */ 2361590Srgrimes#define RTC_BANK1_SSN_BYTE_1 0x41 /* 1st Byte of Serial Number */ 2371590Srgrimes#define RTC_BANK1_SSN_BYTE_2 0x42 /* 2nd Byte of Serial Number */ 2381590Srgrimes#define RTC_BANK1_SSN_BYTE_3 0x43 /* 3rd Byte of Serial Number */ 2391590Srgrimes#define RTC_BANK1_SSN_BYTE_4 0x44 /* 4th Byte of Serial Number */ 2401590Srgrimes#define RTC_BANK1_SSN_BYTE_5 0x45 /* 5th Byte of Serial Number */ 2411590Srgrimes#define RTC_BANK1_SSN_BYTE_6 0x46 /* 6th Byte of Serial Number */ 2421590Srgrimes#define RTC_BANK1_SSN_CRC 0x47 /* Serial CRC Byte */ 2431590Srgrimes#define RTC_BANK1_RAM_DATA_PORT 0x53 /* Extended RAM Data Port */ 24439230Sgibbs 2451590Srgrimes 2461590Srgrimes/* 24761147Sphk * Model-specific registers in Bank 1. 24839230Sgibbs * 24939230Sgibbs * The addresses below differ depending on the model of the RTC chip 25039230Sgibbs * selected in the kernel configuration. Not all of these features are 25150635Speter * supported in the main driver at present. 2521590Srgrimes * 25339230Sgibbs * DS1685/DS1687 - Extended NV-SRAM address (LSB only). 25439230Sgibbs * DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N. 25539230Sgibbs * DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter. 25639230Sgibbs */ 2571590Srgrimes#if defined(CONFIG_RTC_DRV_DS1685) 25839230Sgibbs#define RTC_BANK1_RAM_ADDR 0x50 /* NV-SRAM Addr */ 25939230Sgibbs#elif defined(CONFIG_RTC_DRV_DS1689) 2601590Srgrimes#define RTC_BANK1_VCC_CTR_LSB 0x54 /* Vcc Counter Addr (LSB) */ 2611590Srgrimes#define RTC_BANK1_VCC_CTR_MSB 0x57 /* Vcc Counter Addr (MSB) */ 2621590Srgrimes#define RTC_BANK1_VBAT_CTR_LSB 0x58 /* Vbat Counter Addr (LSB) */ 2631590Srgrimes#define RTC_BANK1_VBAT_CTR_MSB 0x5b /* Vbat Counter Addr (MSB) */ 2641590Srgrimes#define RTC_BANK1_PWR_CTR_LSB 0x5c /* Pwr Cycle Counter Addr (LSB) */ 2651590Srgrimes#define RTC_BANK1_PWR_CTR_MSB 0x5d /* Pwr Cycle Counter Addr (MSB) */ 2661590Srgrimes#define RTC_BANK1_UNIQ_SN 0x60 /* Customer-specific S/N */ 2671590Srgrimes#else /* DS17x85/DS17x87 */ 26887715Smarkm#define RTC_BANK1_RAM_ADDR_LSB 0x50 /* NV-SRAM Addr (LSB) */ 26987715Smarkm#define RTC_BANK1_RAM_ADDR_MSB 0x51 /* NV-SRAM Addr (MSB) */ 2701590Srgrimes#define RTC_BANK1_WRITE_CTR 0x5e /* RTC Write Counter */ 27139230Sgibbs#endif 2721590Srgrimes 2731590Srgrimes 2741590Srgrimes/* 27539230Sgibbs * Model numbers. 2761590Srgrimes * 2771590Srgrimes * The DS1688/DS1691 and DS1689/DS1693 chips share the same model number 2781590Srgrimes * and the manual doesn't indicate any major differences. As such, they 2794930Sbde * are regarded as the same chip in this driver. 2801590Srgrimes */ 2814930Sbde#define RTC_MODEL_DS1685 0x71 /* DS1685/DS1687 */ 2821590Srgrimes#define RTC_MODEL_DS17285 0x72 /* DS17285/DS17287 */ 2831590Srgrimes#define RTC_MODEL_DS1689 0x73 /* DS1688/DS1691/DS1689/DS1693 */ 2841590Srgrimes#define RTC_MODEL_DS17485 0x74 /* DS17485/DS17487 */ 28539230Sgibbs#define RTC_MODEL_DS17885 0x78 /* DS17885/DS17887 */ 28639230Sgibbs 28750635Speter 2881590Srgrimes/* 28939230Sgibbs * Periodic Interrupt Rates / Square-Wave Output Frequency 2901590Srgrimes * 2911590Srgrimes * Periodic rates are selected by setting the RS3-RS0 bits in Control 2921590Srgrimes * Register A and enabled via either the E32K bit in Extended Control 29387715Smarkm * Register 4B or the SQWE bit in Control Register B. 2941590Srgrimes * 2951590Srgrimes * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz 2961590Srgrimes * on the SQW pin of the RTC chip. While there are 16 possible selections, 2971590Srgrimes * the 1-of-16 decoder is only able to divide the base 32768Hz signal into 13 29839230Sgibbs * smaller frequencies. The values 0x01 and 0x02 are not used and are 29939230Sgibbs * synonymous with 0x08 and 0x09, respectively. 30087715Smarkm * 30187715Smarkm * When E32K is set to a logic 1, periodic interrupts are disabled and reading 30250635Speter * /dev/rtc will return -EINVAL. This also applies if the periodic interrupt 3031590Srgrimes * frequency is set to 0Hz. 3041590Srgrimes * 3051590Srgrimes * Not currently used by the rtc-ds1685 driver because the RTC core removed 3061590Srgrimes * support for hardware-generated periodic-interrupts in favour of 3071590Srgrimes * hrtimer-generated interrupts. But these defines are kept around for use 3081590Srgrimes * in userland, as documentation to the hardware, and possible future use if 30987715Smarkm * hardware-generated periodic interrupts are ever added back. 31087715Smarkm */ 3111590Srgrimes /* E32K RS3 RS2 RS1 RS0 */ 3121590Srgrimes#define RTC_SQW_8192HZ 0x03 /* 0 0 0 1 1 */ 3131590Srgrimes#define RTC_SQW_4096HZ 0x04 /* 0 0 1 0 0 */ 3141590Srgrimes#define RTC_SQW_2048HZ 0x05 /* 0 0 1 0 1 */ 31587715Smarkm#define RTC_SQW_1024HZ 0x06 /* 0 0 1 1 0 */ 31687715Smarkm#define RTC_SQW_512HZ 0x07 /* 0 0 1 1 1 */ 3171590Srgrimes#define RTC_SQW_256HZ 0x08 /* 0 1 0 0 0 */ 31839230Sgibbs#define RTC_SQW_128HZ 0x09 /* 0 1 0 0 1 */ 31939230Sgibbs#define RTC_SQW_64HZ 0x0a /* 0 1 0 1 0 */ 32039230Sgibbs#define RTC_SQW_32HZ 0x0b /* 0 1 0 1 1 */ 32139230Sgibbs#define RTC_SQW_16HZ 0x0c /* 0 1 1 0 0 */ 32239230Sgibbs#define RTC_SQW_8HZ 0x0d /* 0 1 1 0 1 */ 32339230Sgibbs#define RTC_SQW_4HZ 0x0e /* 0 1 1 1 0 */ 3241590Srgrimes#define RTC_SQW_2HZ 0x0f /* 0 1 1 1 1 */ 325112288Sphk#define RTC_SQW_0HZ 0x00 /* 0 0 0 0 0 */ 32639230Sgibbs#define RTC_SQW_32768HZ 32768 /* 1 - - - - */ 32783131Sken#define RTC_MAX_USER_FREQ 8192 32883131Sken 32983131Sken 33083131Sken/* 33183131Sken * NVRAM data & addresses: 33239230Sgibbs * - 50 bytes of NVRAM are available just past the clock registers. 33339230Sgibbs * - 64 additional bytes are available in Bank0. 3341590Srgrimes * 33587715Smarkm * Extended, battery-backed NV-SRAM: 33639230Sgibbs * - DS1685/DS1687 - 128 bytes. 33739230Sgibbs * - DS1689/DS1693 - 0 bytes. 33839230Sgibbs * - DS17285/DS17287 - 2048 bytes. 3391590Srgrimes * - DS17485/DS17487 - 4096 bytes. 34087715Smarkm * - DS17885/DS17887 - 8192 bytes. 34161148Sphk */ 34287715Smarkm#define NVRAM_TIME_BASE 0x0e /* NVRAM Addr in Time regs */ 34361148Sphk#define NVRAM_BANK0_BASE 0x40 /* NVRAM Addr in Bank0 regs */ 34439230Sgibbs#define NVRAM_SZ_TIME 50 34587715Smarkm#define NVRAM_SZ_BANK0 64 34661148Sphk#if defined(CONFIG_RTC_DRV_DS1685) 3471590Srgrimes# define NVRAM_SZ_EXTND 128 34839230Sgibbs#elif defined(CONFIG_RTC_DRV_DS1689) 34939230Sgibbs# define NVRAM_SZ_EXTND 0 35039230Sgibbs#elif defined(CONFIG_RTC_DRV_DS17285) 3511590Srgrimes# define NVRAM_SZ_EXTND 2048 3521590Srgrimes#elif defined(CONFIG_RTC_DRV_DS17485) 3531590Srgrimes# define NVRAM_SZ_EXTND 4096 3541590Srgrimes#elif defined(CONFIG_RTC_DRV_DS17885) 3551590Srgrimes# define NVRAM_SZ_EXTND 8192 3561590Srgrimes#endif 35787715Smarkm#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0) 35887715Smarkm#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_EXTND) 3591590Srgrimes 36087715Smarkm 3611590Srgrimes/* 36287715Smarkm * Function Prototypes. 36387715Smarkm */ 36487715Smarkmextern void __noreturn 3651590Srgrimesds1685_rtc_poweroff(struct platform_device *pdev); 3661590Srgrimes 36787715Smarkm#endif /* _LINUX_RTC_DS1685_H_ */ 3681590Srgrimes