1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *  linux/include/linux/mtd/onenand_regs.h
4 *
5 *  OneNAND Register header file
6 *
7 *  Copyright (C) 2005-2007 Samsung Electronics
8 *  Kyungmin Park <kyungmin.park@samsung.com>
9 */
10
11#ifndef __ONENAND_REG_H
12#define __ONENAND_REG_H
13
14/* Memory Address Map Translation (Word order) */
15#define ONENAND_MEMORY_MAP(x)		((x) << 1)
16
17/*
18 * External BufferRAM area
19 */
20#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
21#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
22#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
23
24/*
25 * OneNAND Registers
26 */
27#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
28#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
29#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
30#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
31#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
32#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
33#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
34
35#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
36#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
37#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
38#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
39#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
40#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
41#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
42#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
43
44#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
45#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
46#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
47#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
48#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
49#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
50#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
51#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
52#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
53
54#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
55#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
56#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
57#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
58#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
59#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
60#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
61#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
62#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
63
64/*
65 * Device ID Register F001h (R)
66 */
67#define DEVICE_IS_FLEXONENAND		(1 << 9)
68#define FLEXONENAND_PI_MASK		(0x3ff)
69#define FLEXONENAND_PI_UNLOCK_SHIFT	(14)
70#define ONENAND_DEVICE_DENSITY_MASK	(0xf)
71#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
72#define ONENAND_DEVICE_IS_DDP		(1 << 3)
73#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
74#define ONENAND_DEVICE_VCC_MASK		(0x3)
75
76#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
77#define ONENAND_DEVICE_DENSITY_1Gb	(0x003)
78#define ONENAND_DEVICE_DENSITY_2Gb	(0x004)
79#define ONENAND_DEVICE_DENSITY_4Gb	(0x005)
80#define ONENAND_DEVICE_DENSITY_8Gb	(0x006)
81
82/*
83 * Version ID Register F002h (R)
84 */
85#define ONENAND_VERSION_PROCESS_SHIFT	(8)
86
87/*
88 * Technology Register F006h (R)
89 */
90#define ONENAND_TECHNOLOGY_IS_MLC	(1 << 0)
91
92/*
93 * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
94 */
95#define ONENAND_DDP_SHIFT		(15)
96#define ONENAND_DDP_CHIP0		(0)
97#define ONENAND_DDP_CHIP1		(1 << ONENAND_DDP_SHIFT)
98
99/*
100 * Start Address 8 F107h (R/W)
101 */
102/* Note: It's actually 0x3f in case of SLC */
103#define ONENAND_FPA_MASK		(0x7f)
104#define ONENAND_FPA_SHIFT		(2)
105#define ONENAND_FSA_MASK		(0x03)
106
107/*
108 * Start Buffer Register F200h (R/W)
109 */
110#define ONENAND_BSA_MASK		(0x03)
111#define ONENAND_BSA_SHIFT		(8)
112#define ONENAND_BSA_BOOTRAM		(0 << 2)
113#define ONENAND_BSA_DATARAM0		(2 << 2)
114#define ONENAND_BSA_DATARAM1		(3 << 2)
115/* Note: It's actually 0x03 in case of SLC */
116#define ONENAND_BSC_MASK		(0x07)
117
118/*
119 * Command Register F220h (R/W)
120 */
121#define ONENAND_CMD_READ		(0x00)
122#define ONENAND_CMD_READOOB		(0x13)
123#define ONENAND_CMD_PROG		(0x80)
124#define ONENAND_CMD_PROGOOB		(0x1A)
125#define ONENAND_CMD_2X_PROG		(0x7D)
126#define ONENAND_CMD_2X_CACHE_PROG	(0x7F)
127#define ONENAND_CMD_UNLOCK		(0x23)
128#define ONENAND_CMD_LOCK		(0x2A)
129#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
130#define ONENAND_CMD_UNLOCK_ALL		(0x27)
131#define ONENAND_CMD_ERASE		(0x94)
132#define ONENAND_CMD_MULTIBLOCK_ERASE	(0x95)
133#define ONENAND_CMD_ERASE_VERIFY	(0x71)
134#define ONENAND_CMD_RESET		(0xF0)
135#define ONENAND_CMD_OTP_ACCESS		(0x65)
136#define ONENAND_CMD_READID		(0x90)
137#define FLEXONENAND_CMD_PI_UPDATE	(0x05)
138#define FLEXONENAND_CMD_PI_ACCESS	(0x66)
139#define FLEXONENAND_CMD_RECOVER_LSB	(0x05)
140
141/* NOTE: Those are not *REAL* commands */
142#define ONENAND_CMD_BUFFERRAM		(0x1978)
143#define FLEXONENAND_CMD_READ_PI		(0x1985)
144
145/*
146 * System Configuration 1 Register F221h (R, R/W)
147 */
148#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
149#define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
150#define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
151#define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
152#define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
153#define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
154#define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
155#define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
156#define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
157#define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
158#define ONENAND_SYS_CFG1_BL_32		(4 << 9)
159#define ONENAND_SYS_CFG1_BL_16		(3 << 9)
160#define ONENAND_SYS_CFG1_BL_8		(2 << 9)
161#define ONENAND_SYS_CFG1_BL_4		(1 << 9)
162#define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
163#define ONENAND_SYS_CFG1_BL_SHIFT	(9)
164#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
165#define ONENAND_SYS_CFG1_RDY		(1 << 7)
166#define ONENAND_SYS_CFG1_INT		(1 << 6)
167#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
168#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
169#define ONENAND_SYS_CFG1_VHF		(1 << 3)
170#define ONENAND_SYS_CFG1_HF		(1 << 2)
171#define ONENAND_SYS_CFG1_SYNC_WRITE	(1 << 1)
172
173/*
174 * Controller Status Register F240h (R)
175 */
176#define ONENAND_CTRL_ONGO		(1 << 15)
177#define ONENAND_CTRL_LOCK		(1 << 14)
178#define ONENAND_CTRL_LOAD		(1 << 13)
179#define ONENAND_CTRL_PROGRAM		(1 << 12)
180#define ONENAND_CTRL_ERASE		(1 << 11)
181#define ONENAND_CTRL_ERROR		(1 << 10)
182#define ONENAND_CTRL_RSTB		(1 << 7)
183#define ONENAND_CTRL_OTP_L		(1 << 6)
184#define ONENAND_CTRL_OTP_BL		(1 << 5)
185
186/*
187 * Interrupt Status Register F241h (R)
188 */
189#define ONENAND_INT_MASTER		(1 << 15)
190#define ONENAND_INT_READ		(1 << 7)
191#define ONENAND_INT_WRITE		(1 << 6)
192#define ONENAND_INT_ERASE		(1 << 5)
193#define ONENAND_INT_RESET		(1 << 4)
194#define ONENAND_INT_CLEAR		(0 << 0)
195
196/*
197 * NAND Flash Write Protection Status Register F24Eh (R)
198 */
199#define ONENAND_WP_US			(1 << 2)
200#define ONENAND_WP_LS			(1 << 1)
201#define ONENAND_WP_LTS			(1 << 0)
202
203/*
204 * ECC Status Reigser FF00h (R)
205 */
206#define ONENAND_ECC_1BIT		(1 << 0)
207#define ONENAND_ECC_1BIT_ALL		(0x5555)
208#define ONENAND_ECC_2BIT		(1 << 1)
209#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
210#define FLEXONENAND_UNCORRECTABLE_ERROR	(0x1010)
211#define ONENAND_ECC_3BIT		(1 << 2)
212#define ONENAND_ECC_4BIT		(1 << 3)
213#define ONENAND_ECC_4BIT_UNCORRECTABLE	(0x1010)
214
215/*
216 * One-Time Programmable (OTP)
217 */
218#define FLEXONENAND_OTP_LOCK_OFFSET		(2048)
219#define ONENAND_OTP_LOCK_OFFSET		(14)
220
221#endif	/* __ONENAND_REG_H */
222