1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * twl4030.h - header for TWL4030 PM and audio CODEC device 4 * 5 * Copyright (C) 2005-2006 Texas Instruments, Inc. 6 * 7 * Based on tlv320aic23.c: 8 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 9 */ 10 11#ifndef __TWL_H_ 12#define __TWL_H_ 13 14#include <linux/types.h> 15#include <linux/input/matrix_keypad.h> 16 17/* 18 * Using the twl4030 core we address registers using a pair 19 * { module id, relative register offset } 20 * which that core then maps to the relevant 21 * { i2c slave, absolute register address } 22 * 23 * The module IDs are meaningful only to the twl4030 core code, 24 * which uses them as array indices to look up the first register 25 * address each module uses within a given i2c slave. 26 */ 27 28/* Module IDs for similar functionalities found in twl4030/twl6030 */ 29enum twl_module_ids { 30 TWL_MODULE_USB, 31 TWL_MODULE_PIH, 32 TWL_MODULE_MAIN_CHARGE, 33 TWL_MODULE_PM_MASTER, 34 TWL_MODULE_PM_RECEIVER, 35 36 TWL_MODULE_RTC, 37 TWL_MODULE_PWM, 38 TWL_MODULE_LED, 39 TWL_MODULE_SECURED_REG, 40 41 TWL_MODULE_LAST, 42}; 43 44/* Modules only available in twl4030 series */ 45enum twl4030_module_ids { 46 TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST, 47 TWL4030_MODULE_GPIO, 48 TWL4030_MODULE_INTBR, 49 TWL4030_MODULE_TEST, 50 TWL4030_MODULE_KEYPAD, 51 52 TWL4030_MODULE_MADC, 53 TWL4030_MODULE_INTERRUPTS, 54 TWL4030_MODULE_PRECHARGE, 55 TWL4030_MODULE_BACKUP, 56 TWL4030_MODULE_INT, 57 58 TWL5031_MODULE_ACCESSORY, 59 TWL5031_MODULE_INTERRUPTS, 60 61 TWL4030_MODULE_LAST, 62}; 63 64/* Modules only available in twl6030 series */ 65enum twl6030_module_ids { 66 TWL6030_MODULE_ID0 = TWL_MODULE_LAST, 67 TWL6030_MODULE_ID1, 68 TWL6030_MODULE_ID2, 69 TWL6030_MODULE_GPADC, 70 TWL6030_MODULE_GASGAUGE, 71 72 /* A few extra registers before the registers shared with the 6030 */ 73 TWL6032_MODULE_CHARGE, 74 TWL6030_MODULE_LAST, 75}; 76 77/* Until the clients has been converted to use TWL_MODULE_LED */ 78#define TWL4030_MODULE_LED TWL_MODULE_LED 79 80#define GPIO_INTR_OFFSET 0 81#define KEYPAD_INTR_OFFSET 1 82#define BCI_INTR_OFFSET 2 83#define MADC_INTR_OFFSET 3 84#define USB_INTR_OFFSET 4 85#define CHARGERFAULT_INTR_OFFSET 5 86#define BCI_PRES_INTR_OFFSET 9 87#define USB_PRES_INTR_OFFSET 10 88#define RTC_INTR_OFFSET 11 89 90/* 91 * Offset from TWL6030_IRQ_BASE / pdata->irq_base 92 */ 93#define PWR_INTR_OFFSET 0 94#define HOTDIE_INTR_OFFSET 12 95#define SMPSLDO_INTR_OFFSET 13 96#define BATDETECT_INTR_OFFSET 14 97#define SIMDETECT_INTR_OFFSET 15 98#define MMCDETECT_INTR_OFFSET 16 99#define GASGAUGE_INTR_OFFSET 17 100#define USBOTG_INTR_OFFSET 4 101#define CHARGER_INTR_OFFSET 2 102#define RSV_INTR_OFFSET 0 103 104/* INT register offsets */ 105#define REG_INT_STS_A 0x00 106#define REG_INT_STS_B 0x01 107#define REG_INT_STS_C 0x02 108 109#define REG_INT_MSK_LINE_A 0x03 110#define REG_INT_MSK_LINE_B 0x04 111#define REG_INT_MSK_LINE_C 0x05 112 113#define REG_INT_MSK_STS_A 0x06 114#define REG_INT_MSK_STS_B 0x07 115#define REG_INT_MSK_STS_C 0x08 116 117/* MASK INT REG GROUP A */ 118#define TWL6030_PWR_INT_MASK 0x07 119#define TWL6030_RTC_INT_MASK 0x18 120#define TWL6030_HOTDIE_INT_MASK 0x20 121#define TWL6030_SMPSLDOA_INT_MASK 0xC0 122 123/* MASK INT REG GROUP B */ 124#define TWL6030_SMPSLDOB_INT_MASK 0x01 125#define TWL6030_BATDETECT_INT_MASK 0x02 126#define TWL6030_SIMDETECT_INT_MASK 0x04 127#define TWL6030_MMCDETECT_INT_MASK 0x08 128#define TWL6030_GPADC_INT_MASK 0x60 129#define TWL6030_GASGAUGE_INT_MASK 0x80 130 131/* MASK INT REG GROUP C */ 132#define TWL6030_USBOTG_INT_MASK 0x0F 133#define TWL6030_CHARGER_CTRL_INT_MASK 0x10 134#define TWL6030_CHARGER_FAULT_INT_MASK 0x60 135 136#define TWL6030_MMCCTRL 0xEE 137#define VMMC_AUTO_OFF (0x1 << 3) 138#define SW_FC (0x1 << 2) 139#define STS_MMC 0x1 140 141#define TWL6030_CFG_INPUT_PUPD3 0xF2 142#define MMC_PU (0x1 << 3) 143#define MMC_PD (0x1 << 2) 144 145#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF) 146#define TWL_SIL_REV(rev) ((rev) >> 24) 147#define TWL_SIL_5030 0x09002F 148#define TWL5030_REV_1_0 0x00 149#define TWL5030_REV_1_1 0x10 150#define TWL5030_REV_1_2 0x30 151 152#define TWL4030_CLASS_ID 0x4030 153#define TWL6030_CLASS_ID 0x6030 154unsigned int twl_rev(void); 155#define GET_TWL_REV (twl_rev()) 156#define TWL_CLASS_IS(class, id) \ 157static inline int twl_class_is_ ##class(void) \ 158{ \ 159 return ((id) == (GET_TWL_REV)) ? 1 : 0; \ 160} 161 162TWL_CLASS_IS(4030, TWL4030_CLASS_ID) 163TWL_CLASS_IS(6030, TWL6030_CLASS_ID) 164 165/* Set the regcache bypass for the regmap associated with the nodule */ 166int twl_set_regcache_bypass(u8 mod_no, bool enable); 167 168/* 169 * Read and write several 8-bit registers at once. 170 */ 171int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 172int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 173 174/* 175 * Read and write single 8-bit registers 176 */ 177static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { 178 return twl_i2c_write(mod_no, &val, reg, 1); 179} 180 181static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { 182 return twl_i2c_read(mod_no, val, reg, 1); 183} 184 185static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { 186 __le16 value; 187 188 value = cpu_to_le16(val); 189 return twl_i2c_write(mod_no, (u8 *) &value, reg, 2); 190} 191 192static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { 193 int ret; 194 __le16 value; 195 196 ret = twl_i2c_read(mod_no, (u8 *) &value, reg, 2); 197 *val = le16_to_cpu(value); 198 return ret; 199} 200 201int twl_get_type(void); 202int twl_get_version(void); 203int twl_get_hfclk_rate(void); 204 205int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); 206int twl6030_interrupt_mask(u8 bit_mask, u8 offset); 207 208/* Card detect Configuration for MMC1 Controller on OMAP4 */ 209#ifdef CONFIG_TWL4030_CORE 210int twl6030_mmc_card_detect_config(void); 211#else 212static inline int twl6030_mmc_card_detect_config(void) 213{ 214 pr_debug("twl6030_mmc_card_detect_config not supported\n"); 215 return 0; 216} 217#endif 218 219/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ 220#ifdef CONFIG_TWL4030_CORE 221int twl6030_mmc_card_detect(struct device *dev, int slot); 222#else 223static inline int twl6030_mmc_card_detect(struct device *dev, int slot) 224{ 225 pr_debug("Call back twl6030_mmc_card_detect not supported\n"); 226 return -EIO; 227} 228#endif 229/*----------------------------------------------------------------------*/ 230 231/* 232 * NOTE: at up to 1024 registers, this is a big chip. 233 * 234 * Avoid putting register declarations in this file, instead of into 235 * a driver-private file, unless some of the registers in a block 236 * need to be shared with other drivers. One example is blocks that 237 * have Secondary IRQ Handler (SIH) registers. 238 */ 239 240#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) 241#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) 242#define TWL4030_SIH_CTRL_COR_MASK BIT(2) 243 244/*----------------------------------------------------------------------*/ 245 246/* 247 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) 248 */ 249 250#define REG_GPIODATAIN1 0x0 251#define REG_GPIODATAIN2 0x1 252#define REG_GPIODATAIN3 0x2 253#define REG_GPIODATADIR1 0x3 254#define REG_GPIODATADIR2 0x4 255#define REG_GPIODATADIR3 0x5 256#define REG_GPIODATAOUT1 0x6 257#define REG_GPIODATAOUT2 0x7 258#define REG_GPIODATAOUT3 0x8 259#define REG_CLEARGPIODATAOUT1 0x9 260#define REG_CLEARGPIODATAOUT2 0xA 261#define REG_CLEARGPIODATAOUT3 0xB 262#define REG_SETGPIODATAOUT1 0xC 263#define REG_SETGPIODATAOUT2 0xD 264#define REG_SETGPIODATAOUT3 0xE 265#define REG_GPIO_DEBEN1 0xF 266#define REG_GPIO_DEBEN2 0x10 267#define REG_GPIO_DEBEN3 0x11 268#define REG_GPIO_CTRL 0x12 269#define REG_GPIOPUPDCTR1 0x13 270#define REG_GPIOPUPDCTR2 0x14 271#define REG_GPIOPUPDCTR3 0x15 272#define REG_GPIOPUPDCTR4 0x16 273#define REG_GPIOPUPDCTR5 0x17 274#define REG_GPIO_ISR1A 0x19 275#define REG_GPIO_ISR2A 0x1A 276#define REG_GPIO_ISR3A 0x1B 277#define REG_GPIO_IMR1A 0x1C 278#define REG_GPIO_IMR2A 0x1D 279#define REG_GPIO_IMR3A 0x1E 280#define REG_GPIO_ISR1B 0x1F 281#define REG_GPIO_ISR2B 0x20 282#define REG_GPIO_ISR3B 0x21 283#define REG_GPIO_IMR1B 0x22 284#define REG_GPIO_IMR2B 0x23 285#define REG_GPIO_IMR3B 0x24 286#define REG_GPIO_EDR1 0x28 287#define REG_GPIO_EDR2 0x29 288#define REG_GPIO_EDR3 0x2A 289#define REG_GPIO_EDR4 0x2B 290#define REG_GPIO_EDR5 0x2C 291#define REG_GPIO_SIH_CTRL 0x2D 292 293/* Up to 18 signals are available as GPIOs, when their 294 * pins are not assigned to another use (such as ULPI/USB). 295 */ 296#define TWL4030_GPIO_MAX 18 297 298/*----------------------------------------------------------------------*/ 299 300/*Interface Bit Register (INTBR) offsets 301 *(Use TWL_4030_MODULE_INTBR) 302 */ 303 304#define REG_IDCODE_7_0 0x00 305#define REG_IDCODE_15_8 0x01 306#define REG_IDCODE_16_23 0x02 307#define REG_IDCODE_31_24 0x03 308#define REG_GPPUPDCTR1 0x0F 309#define REG_UNLOCK_TEST_REG 0x12 310 311/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ 312 313#define I2C_SCL_CTRL_PU BIT(0) 314#define I2C_SDA_CTRL_PU BIT(2) 315#define SR_I2C_SCL_CTRL_PU BIT(4) 316#define SR_I2C_SDA_CTRL_PU BIT(6) 317 318#define TWL_EEPROM_R_UNLOCK 0x49 319 320/*----------------------------------------------------------------------*/ 321 322/* 323 * Keypad register offsets (use TWL4030_MODULE_KEYPAD) 324 * ... SIH/interrupt only 325 */ 326 327#define TWL4030_KEYPAD_KEYP_ISR1 0x11 328#define TWL4030_KEYPAD_KEYP_IMR1 0x12 329#define TWL4030_KEYPAD_KEYP_ISR2 0x13 330#define TWL4030_KEYPAD_KEYP_IMR2 0x14 331#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */ 332#define TWL4030_KEYPAD_KEYP_EDR 0x16 333#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 334 335/*----------------------------------------------------------------------*/ 336 337/* 338 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) 339 * ... SIH/interrupt only 340 */ 341 342#define TWL4030_MADC_ISR1 0x61 343#define TWL4030_MADC_IMR1 0x62 344#define TWL4030_MADC_ISR2 0x63 345#define TWL4030_MADC_IMR2 0x64 346#define TWL4030_MADC_SIR 0x65 /* test register */ 347#define TWL4030_MADC_EDR 0x66 348#define TWL4030_MADC_SIH_CTRL 0x67 349 350/*----------------------------------------------------------------------*/ 351 352/* 353 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) 354 */ 355 356#define TWL4030_INTERRUPTS_BCIISR1A 0x0 357#define TWL4030_INTERRUPTS_BCIISR2A 0x1 358#define TWL4030_INTERRUPTS_BCIIMR1A 0x2 359#define TWL4030_INTERRUPTS_BCIIMR2A 0x3 360#define TWL4030_INTERRUPTS_BCIISR1B 0x4 361#define TWL4030_INTERRUPTS_BCIISR2B 0x5 362#define TWL4030_INTERRUPTS_BCIIMR1B 0x6 363#define TWL4030_INTERRUPTS_BCIIMR2B 0x7 364#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */ 365#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */ 366#define TWL4030_INTERRUPTS_BCIEDR1 0xa 367#define TWL4030_INTERRUPTS_BCIEDR2 0xb 368#define TWL4030_INTERRUPTS_BCIEDR3 0xc 369#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd 370 371/*----------------------------------------------------------------------*/ 372 373/* 374 * Power Interrupt block register offsets (use TWL4030_MODULE_INT) 375 */ 376 377#define TWL4030_INT_PWR_ISR1 0x0 378#define TWL4030_INT_PWR_IMR1 0x1 379#define TWL4030_INT_PWR_ISR2 0x2 380#define TWL4030_INT_PWR_IMR2 0x3 381#define TWL4030_INT_PWR_SIR 0x4 /* test register */ 382#define TWL4030_INT_PWR_EDR1 0x5 383#define TWL4030_INT_PWR_EDR2 0x6 384#define TWL4030_INT_PWR_SIH_CTRL 0x7 385 386/*----------------------------------------------------------------------*/ 387 388/* 389 * Accessory Interrupts 390 */ 391#define TWL5031_ACIIMR_LSB 0x05 392#define TWL5031_ACIIMR_MSB 0x06 393#define TWL5031_ACIIDR_LSB 0x07 394#define TWL5031_ACIIDR_MSB 0x08 395#define TWL5031_ACCISR1 0x0F 396#define TWL5031_ACCIMR1 0x10 397#define TWL5031_ACCISR2 0x11 398#define TWL5031_ACCIMR2 0x12 399#define TWL5031_ACCSIR 0x13 400#define TWL5031_ACCEDR1 0x14 401#define TWL5031_ACCSIHCTRL 0x15 402 403/*----------------------------------------------------------------------*/ 404 405/* 406 * Battery Charger Controller 407 */ 408 409#define TWL5031_INTERRUPTS_BCIISR1 0x0 410#define TWL5031_INTERRUPTS_BCIIMR1 0x1 411#define TWL5031_INTERRUPTS_BCIISR2 0x2 412#define TWL5031_INTERRUPTS_BCIIMR2 0x3 413#define TWL5031_INTERRUPTS_BCISIR 0x4 414#define TWL5031_INTERRUPTS_BCIEDR1 0x5 415#define TWL5031_INTERRUPTS_BCIEDR2 0x6 416#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 417 418/*----------------------------------------------------------------------*/ 419 420/* 421 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) 422 */ 423 424#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00 425#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01 426#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02 427#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03 428#define TWL4030_PM_MASTER_STS_BOOT 0x04 429#define TWL4030_PM_MASTER_CFG_BOOT 0x05 430#define TWL4030_PM_MASTER_SHUNDAN 0x06 431#define TWL4030_PM_MASTER_BOOT_BCI 0x07 432#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08 433#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09 434#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b 435#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c 436#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d 437#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e 438#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f 439#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10 440#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11 441#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12 442#define TWL4030_PM_MASTER_STS_P123_STATE 0x13 443#define TWL4030_PM_MASTER_PB_CFG 0x14 444#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15 445#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16 446#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c 447#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d 448#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e 449#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f 450#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20 451#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21 452#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22 453#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23 454#define TWL4030_PM_MASTER_MEMORY_DATA 0x24 455 456#define TWL4030_PM_MASTER_KEY_CFG1 0xc0 457#define TWL4030_PM_MASTER_KEY_CFG2 0x0c 458 459#define TWL4030_PM_MASTER_KEY_TST1 0xe0 460#define TWL4030_PM_MASTER_KEY_TST2 0x0e 461 462#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 463 464#define TWL6030_PHOENIX_DEV_ON 0x06 465/*----------------------------------------------------------------------*/ 466 467/* Power bus message definitions */ 468 469/* The TWL4030/5030 splits its power-management resources (the various 470 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and 471 * P3. These groups can then be configured to transition between sleep, wait-on 472 * and active states by sending messages to the power bus. See Section 5.4.2 473 * Power Resources of TWL4030 TRM 474 */ 475 476/* Processor groups */ 477#define DEV_GRP_NULL 0x0 478#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ 479#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ 480#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ 481 482/* Resource groups */ 483#define RES_GRP_RES 0x0 /* Reserved */ 484#define RES_GRP_PP 0x1 /* Power providers */ 485#define RES_GRP_RC 0x2 /* Reset and control */ 486#define RES_GRP_PP_RC 0x3 487#define RES_GRP_PR 0x4 /* Power references */ 488#define RES_GRP_PP_PR 0x5 489#define RES_GRP_RC_PR 0x6 490#define RES_GRP_ALL 0x7 /* All resource groups */ 491 492#define RES_TYPE2_R0 0x0 493#define RES_TYPE2_R1 0x1 494#define RES_TYPE2_R2 0x2 495 496#define RES_TYPE_R0 0x0 497#define RES_TYPE_ALL 0x7 498 499/* Resource states */ 500#define RES_STATE_WRST 0xF 501#define RES_STATE_ACTIVE 0xE 502#define RES_STATE_SLEEP 0x8 503#define RES_STATE_OFF 0x0 504 505/* Power resources */ 506 507/* Power providers */ 508#define RES_VAUX1 1 509#define RES_VAUX2 2 510#define RES_VAUX3 3 511#define RES_VAUX4 4 512#define RES_VMMC1 5 513#define RES_VMMC2 6 514#define RES_VPLL1 7 515#define RES_VPLL2 8 516#define RES_VSIM 9 517#define RES_VDAC 10 518#define RES_VINTANA1 11 519#define RES_VINTANA2 12 520#define RES_VINTDIG 13 521#define RES_VIO 14 522#define RES_VDD1 15 523#define RES_VDD2 16 524#define RES_VUSB_1V5 17 525#define RES_VUSB_1V8 18 526#define RES_VUSB_3V1 19 527#define RES_VUSBCP 20 528#define RES_REGEN 21 529/* Reset and control */ 530#define RES_NRES_PWRON 22 531#define RES_CLKEN 23 532#define RES_SYSEN 24 533#define RES_HFCLKOUT 25 534#define RES_32KCLKOUT 26 535#define RES_RESET 27 536/* Power Reference */ 537#define RES_MAIN_REF 28 538 539#define TOTAL_RESOURCES 28 540/* 541 * Power Bus Message Format ... these can be sent individually by Linux, 542 * but are usually part of downloaded scripts that are run when various 543 * power events are triggered. 544 * 545 * Broadcast Message (16 Bits): 546 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] 547 * RES_STATE[3:0] 548 * 549 * Singular Message (16 Bits): 550 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] 551 */ 552 553#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ 554 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ 555 | (type) << 4 | (state)) 556 557#define MSG_SINGULAR(devgrp, id, state) \ 558 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) 559 560#define MSG_BROADCAST_ALL(devgrp, state) \ 561 ((devgrp) << 5 | (state)) 562 563#define MSG_BROADCAST_REF MSG_BROADCAST_ALL 564#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL 565#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL 566/*----------------------------------------------------------------------*/ 567 568struct twl4030_clock_init_data { 569 bool ck32k_lowpwr_enable; 570}; 571 572struct twl4030_bci_platform_data { 573 int *battery_tmp_tbl; 574 unsigned int tblsize; 575 int bb_uvolt; /* voltage to charge backup battery */ 576 int bb_uamp; /* current for backup battery charging */ 577}; 578 579/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ 580struct twl4030_gpio_platform_data { 581 /* package the two LED signals as output-only GPIOs? */ 582 bool use_leds; 583 584 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */ 585 u8 mmc_cd; 586 587 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */ 588 u32 debounce; 589 590 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup 591 * should be enabled. Else, if that bit is set in "pulldowns", 592 * that pulldown is enabled. Don't waste power by letting any 593 * digital inputs float... 594 */ 595 u32 pullups; 596 u32 pulldowns; 597}; 598 599struct twl4030_madc_platform_data { 600 int irq_line; 601}; 602 603/* Boards have unique mappings of {row, col} --> keycode. 604 * Column and row are 8 bits each, but range only from 0..7. 605 * a PERSISTENT_KEY is "always on" and never reported. 606 */ 607#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED) 608 609struct twl4030_keypad_data { 610 const struct matrix_keymap_data *keymap_data; 611 unsigned rows; 612 unsigned cols; 613 bool rep; 614}; 615 616enum twl4030_usb_mode { 617 T2_USB_MODE_ULPI = 1, 618 T2_USB_MODE_CEA2011_3PIN = 2, 619}; 620 621struct twl4030_usb_data { 622 enum twl4030_usb_mode usb_mode; 623 unsigned long features; 624 625 int (*phy_init)(struct device *dev); 626 int (*phy_exit)(struct device *dev); 627 /* Power on/off the PHY */ 628 int (*phy_power)(struct device *dev, int iD, int on); 629 /* enable/disable phy clocks */ 630 int (*phy_set_clock)(struct device *dev, int on); 631 /* suspend/resume of phy */ 632 int (*phy_suspend)(struct device *dev, int suspend); 633}; 634 635struct twl4030_ins { 636 u16 pmb_message; 637 u8 delay; 638}; 639 640struct twl4030_script { 641 struct twl4030_ins *script; 642 unsigned size; 643 u8 flags; 644#define TWL4030_WRST_SCRIPT (1<<0) 645#define TWL4030_WAKEUP12_SCRIPT (1<<1) 646#define TWL4030_WAKEUP3_SCRIPT (1<<2) 647#define TWL4030_SLEEP_SCRIPT (1<<3) 648}; 649 650struct twl4030_resconfig { 651 u8 resource; 652 u8 devgroup; /* Processor group that Power resource belongs to */ 653 u8 type; /* Power resource addressed, 6 / broadcast message */ 654 u8 type2; /* Power resource addressed, 3 / broadcast message */ 655 u8 remap_off; /* off state remapping */ 656 u8 remap_sleep; /* sleep state remapping */ 657}; 658 659struct twl4030_power_data { 660 struct twl4030_script **scripts; 661 unsigned num; 662 struct twl4030_resconfig *resource_config; 663 struct twl4030_resconfig *board_config; 664#define TWL4030_RESCONFIG_UNDEF ((u8)-1) 665 bool use_poweroff; /* Board is wired for TWL poweroff */ 666 bool ac_charger_quirk; /* Disable AC charger on board */ 667}; 668 669extern int twl4030_remove_script(u8 flags); 670extern void twl4030_power_off(void); 671 672struct twl4030_codec_data { 673 unsigned int digimic_delay; /* in ms */ 674 unsigned int ramp_delay_value; 675 unsigned int offset_cncl_path; 676 unsigned int hs_extmute:1; 677 int hs_extmute_gpio; 678}; 679 680struct twl4030_vibra_data { 681 unsigned int coexist; 682}; 683 684struct twl4030_audio_data { 685 unsigned int audio_mclk; 686 struct twl4030_codec_data *codec; 687 struct twl4030_vibra_data *vibra; 688 689 /* twl6040 */ 690 int audpwron_gpio; /* audio power-on gpio */ 691 int naudint_irq; /* audio interrupt */ 692 unsigned int irq_base; 693}; 694 695struct twl_regulator_driver_data { 696 int (*set_voltage)(void *data, int target_uV); 697 int (*get_voltage)(void *data); 698 void *data; 699 unsigned long features; 700}; 701/* chip-specific feature flags, for twl_regulator_driver_data.features */ 702#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */ 703#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */ 704#define TWL5031 BIT(2) /* twl5031 has different registers */ 705#define TWL6030_CLASS BIT(3) /* TWL6030 class */ 706#define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */ 707#define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible 708 * but not officially supported. 709 * This flag is necessary to 710 * enable them. 711 */ 712 713/*----------------------------------------------------------------------*/ 714 715int twl4030_sih_setup(struct device *dev, int module, int irq_base); 716 717/* Offsets to Power Registers */ 718#define TWL4030_VDAC_DEV_GRP 0x3B 719#define TWL4030_VDAC_DEDICATED 0x3E 720#define TWL4030_VAUX1_DEV_GRP 0x17 721#define TWL4030_VAUX1_DEDICATED 0x1A 722#define TWL4030_VAUX2_DEV_GRP 0x1B 723#define TWL4030_VAUX2_DEDICATED 0x1E 724#define TWL4030_VAUX3_DEV_GRP 0x1F 725#define TWL4030_VAUX3_DEDICATED 0x22 726 727/*----------------------------------------------------------------------*/ 728 729/* Linux-specific regulator identifiers ... for now, we only support 730 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 731 * need to tie into hardware based voltage scaling (cpufreq etc), while 732 * VIO is generally fixed. 733 */ 734 735/* TWL4030 SMPS/LDO's */ 736/* EXTERNAL dc-to-dc buck converters */ 737#define TWL4030_REG_VDD1 0 738#define TWL4030_REG_VDD2 1 739#define TWL4030_REG_VIO 2 740 741/* EXTERNAL LDOs */ 742#define TWL4030_REG_VDAC 3 743#define TWL4030_REG_VPLL1 4 744#define TWL4030_REG_VPLL2 5 /* not on all chips */ 745#define TWL4030_REG_VMMC1 6 746#define TWL4030_REG_VMMC2 7 /* not on all chips */ 747#define TWL4030_REG_VSIM 8 /* not on all chips */ 748#define TWL4030_REG_VAUX1 9 /* not on all chips */ 749#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */ 750#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */ 751#define TWL4030_REG_VAUX3 12 /* not on all chips */ 752#define TWL4030_REG_VAUX4 13 /* not on all chips */ 753 754/* INTERNAL LDOs */ 755#define TWL4030_REG_VINTANA1 14 756#define TWL4030_REG_VINTANA2 15 757#define TWL4030_REG_VINTDIG 16 758#define TWL4030_REG_VUSB1V5 17 759#define TWL4030_REG_VUSB1V8 18 760#define TWL4030_REG_VUSB3V1 19 761 762/* TWL6030 SMPS/LDO's */ 763/* EXTERNAL dc-to-dc buck convertor controllable via SR */ 764#define TWL6030_REG_VDD1 30 765#define TWL6030_REG_VDD2 31 766#define TWL6030_REG_VDD3 32 767 768/* Non SR compliant dc-to-dc buck convertors */ 769#define TWL6030_REG_VMEM 33 770#define TWL6030_REG_V2V1 34 771#define TWL6030_REG_V1V29 35 772#define TWL6030_REG_V1V8 36 773 774/* EXTERNAL LDOs */ 775#define TWL6030_REG_VAUX1_6030 37 776#define TWL6030_REG_VAUX2_6030 38 777#define TWL6030_REG_VAUX3_6030 39 778#define TWL6030_REG_VMMC 40 779#define TWL6030_REG_VPP 41 780#define TWL6030_REG_VUSIM 42 781#define TWL6030_REG_VANA 43 782#define TWL6030_REG_VCXIO 44 783#define TWL6030_REG_VDAC 45 784#define TWL6030_REG_VUSB 46 785 786/* INTERNAL LDOs */ 787#define TWL6030_REG_VRTC 47 788#define TWL6030_REG_CLK32KG 48 789 790/* LDOs on 6025 have different names */ 791#define TWL6032_REG_LDO2 49 792#define TWL6032_REG_LDO4 50 793#define TWL6032_REG_LDO3 51 794#define TWL6032_REG_LDO5 52 795#define TWL6032_REG_LDO1 53 796#define TWL6032_REG_LDO7 54 797#define TWL6032_REG_LDO6 55 798#define TWL6032_REG_LDOLN 56 799#define TWL6032_REG_LDOUSB 57 800 801/* 6025 DCDC supplies */ 802#define TWL6032_REG_SMPS3 58 803#define TWL6032_REG_SMPS4 59 804#define TWL6032_REG_VIO 60 805 806 807#endif /* End of __TWL4030_H */ 808