12061Sjkh/* SPDX-License-Identifier: GPL-2.0 */ 250479Speter/* 32061Sjkh * Copyright (C) 2022 Renesas Electronics Corporation 438666Sjb */ 532427Sjb#ifndef __MFD_RZ_MTU3_H__ 6111131Sru#define __MFD_RZ_MTU3_H__ 7111131Sru 8217733Sbz#include <linux/clk.h> 9217733Sbz#include <linux/device.h> 1038666Sjb#include <linux/mutex.h> 1138666Sjb 1238666Sjb/* 8-bit shared register offsets macros */ 13159363Strhodes#define RZ_MTU3_TSTRA 0x080 /* Timer start register A */ 1464049Salex#define RZ_MTU3_TSTRB 0x880 /* Timer start register B */ 1564049Salex 16116679Ssimokawa/* 16-bit shared register offset macros */ 1766071Smarkm#define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */ 18116679Ssimokawa#define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */ 1973504Sobrien#define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */ 20204661Simp#define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */ 21232907Sjmallett#define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */ 22158962Snetchild#define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */ 23223148Sru#define RZ_MTU3_TCNTSA 0x020 /* Timer subcounter A */ 24295380Sngie#define RZ_MTU3_TCNTSB 0x820 /* Timer subcounter B */ 25169597Sdes 26169597Sdes/* 27169597Sdes * MTU5 contains 3 timer counter registers and is totaly different 28169597Sdes * from other channels, so we must separate its offset 29231821Spluknet */ 30169597Sdes 31169597Sdes/* 8-bit register offset macros of MTU3 channels except MTU5 */ 32169597Sdes#define RZ_MTU3_TIER 0 /* Timer interrupt register */ 33217815Sbz#define RZ_MTU3_NFCR 1 /* Noise filter control register */ 34217815Sbz#define RZ_MTU3_TSR 2 /* Timer status register */ 35218524Sjhb#define RZ_MTU3_TCR 3 /* Timer control register */ 36264460Sbrueffer#define RZ_MTU3_TCR2 4 /* Timer control register 2 */ 37264460Sbrueffer 38264460Sbrueffer/* Timer mode register 1 */ 39264460Sbrueffer#define RZ_MTU3_TMDR1 5 40268503Simp#define RZ_MTU3_TMDR1_MD GENMASK(3, 0) 41270155Simp#define RZ_MTU3_TMDR1_MD_NORMAL FIELD_PREP(RZ_MTU3_TMDR1_MD, 0) 42270155Simp#define RZ_MTU3_TMDR1_MD_PWMMODE1 FIELD_PREP(RZ_MTU3_TMDR1_MD, 2) 43253002Salfred 44253002Salfred#define RZ_MTU3_TIOR 6 /* Timer I/O control register */ 45253002Salfred#define RZ_MTU3_TIORH 6 /* Timer I/O control register H */ 46253002Salfred#define RZ_MTU3_TIORL 7 /* Timer I/O control register L */ 47253002Salfred/* Only MTU3/4/6/7 have TBTM registers */ 48253003Salfred#define RZ_MTU3_TBTM 8 /* Timer buffer operation transfer mode register */ 4932427Sjb 5038666Sjb/* 8-bit MTU5 register offset macros */ 51108451Sschweikh#define RZ_MTU3_TSTR 2 /* MTU5 Timer start register */ 5238666Sjb#define RZ_MTU3_TCNTCMPCLR 3 /* MTU5 Timer compare match clear register */ 5338666Sjb#define RZ_MTU3_TCRU 4 /* Timer control register U */ 5438666Sjb#define RZ_MTU3_TCR2U 5 /* Timer control register 2U */ 5538666Sjb#define RZ_MTU3_TIORU 6 /* Timer I/O control register U */ 5617308Speter#define RZ_MTU3_TCRV 7 /* Timer control register V */ 57217273Simp#define RZ_MTU3_TCR2V 8 /* Timer control register 2V */ 58217294Simp#define RZ_MTU3_TIORV 9 /* Timer I/O control register V */ 5919175Sbde#define RZ_MTU3_TCRW 10 /* Timer control register W */ 6096205Sjwd#define RZ_MTU3_TCR2W 11 /* Timer control register 2W */ 61292217Semaste#define RZ_MTU3_TIORW 12 /* Timer I/O control register W */ 62292217Semaste 6338042Sbde/* 16-bit register offset macros of MTU3 channels except MTU5 */ 6496205Sjwd#define RZ_MTU3_TCNT 0 /* Timer counter */ 6596205Sjwd#define RZ_MTU3_TGRA 1 /* Timer general register A */ 6638042Sbde#define RZ_MTU3_TGRB 2 /* Timer general register B */ 6796205Sjwd#define RZ_MTU3_TGRC 3 /* Timer general register C */ 68159363Strhodes#define RZ_MTU3_TGRD 4 /* Timer general register D */ 69159363Strhodes#define RZ_MTU3_TGRE 5 /* Timer general register E */ 7017308Speter#define RZ_MTU3_TGRF 6 /* Timer general register F */ 7196205Sjwd/* Timer A/D converter start request registers */ 7296205Sjwd#define RZ_MTU3_TADCR 7 /* control register */ 7317308Speter#define RZ_MTU3_TADCORA 8 /* cycle set register A */ 74148330Snetchild#define RZ_MTU3_TADCORB 9 /* cycle set register B */ 75148330Snetchild#define RZ_MTU3_TADCOBRA 10 /* cycle set buffer register A */ 76148330Snetchild#define RZ_MTU3_TADCOBRB 11 /* cycle set buffer register B */ 77148330Snetchild 78159831Sobrien/* 16-bit MTU5 register offset macros */ 79148330Snetchild#define RZ_MTU3_TCNTU 0 /* MTU5 Timer counter U */ 80148330Snetchild#define RZ_MTU3_TGRU 1 /* MTU5 Timer general register U */ 81148330Snetchild#define RZ_MTU3_TCNTV 2 /* MTU5 Timer counter V */ 82251107Screes#define RZ_MTU3_TGRV 3 /* MTU5 Timer general register V */ 83251107Screes#define RZ_MTU3_TCNTW 4 /* MTU5 Timer counter W */ 84148330Snetchild#define RZ_MTU3_TGRW 5 /* MTU5 Timer general register W */ 85148330Snetchild 8696205Sjwd/* 32-bit register offset */ 8796205Sjwd#define RZ_MTU3_TCNTLW 0 /* Timer longword counter */ 8896205Sjwd#define RZ_MTU3_TGRALW 1 /* Timer longword general register A */ 89268191Smarcel#define RZ_MTU3_TGRBLW 2 /* Timer longowrd general register B */ 90162147Sru 9198723Sdillon#define RZ_MTU3_TMDR3 0x191 /* MTU1 Timer Mode Register 3 */ 9298723Sdillon 9398723Sdillon/* Macros for setting registers */ 9438666Sjb#define RZ_MTU3_TCR_CCLR GENMASK(7, 5) 9538666Sjb#define RZ_MTU3_TCR_CKEG GENMASK(4, 3) 9617308Speter#define RZ_MTU3_TCR_TPCS GENMASK(2, 0) 97123311Speter#define RZ_MTU3_TCR_CCLR_TGRA BIT(5) 98123311Speter#define RZ_MTU3_TCR_CCLR_TGRC FIELD_PREP(RZ_MTU3_TCR_CCLR, 5) 99123311Speter#define RZ_MTU3_TCR_CKEG_RISING FIELD_PREP(RZ_MTU3_TCR_CKEG, 0) 100123311Speter 101175833Sjhb#define RZ_MTU3_TIOR_IOB GENMASK(7, 4) 102175833Sjhb#define RZ_MTU3_TIOR_IOA GENMASK(3, 0) 103284454Simp#define RZ_MTU3_TIOR_OC_RETAIN 0 104290526Sbdrewery#define RZ_MTU3_TIOR_OC_INIT_OUT_LO_HI_OUT 2 105290526Sbdrewery#define RZ_MTU3_TIOR_OC_INIT_OUT_HI_TOGGLE_OUT 7 106302067Sbdrewery 107290526Sbdrewery#define RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH \ 108301472Sbdrewery FIELD_PREP(RZ_MTU3_TIOR_IOA, RZ_MTU3_TIOR_OC_INIT_OUT_LO_HI_OUT) 109290526Sbdrewery#define RZ_MTU3_TIOR_OC_IOB_TOGGLE \ 110284454Simp FIELD_PREP(RZ_MTU3_TIOR_IOB, RZ_MTU3_TIOR_OC_INIT_OUT_HI_TOGGLE_OUT) 111284454Simp 112290816Ssjgenum rz_mtu3_channels { 113284345Ssjg RZ_MTU3_CHAN_0, 114284345Ssjg RZ_MTU3_CHAN_1, 115284345Ssjg RZ_MTU3_CHAN_2, 116284345Ssjg RZ_MTU3_CHAN_3, 117169597Sdes RZ_MTU3_CHAN_4, 118295380Sngie RZ_MTU3_CHAN_5, 119295380Sngie RZ_MTU3_CHAN_6, 120169597Sdes RZ_MTU3_CHAN_7, 121219177Snwhitehorn RZ_MTU3_CHAN_8, 122219177Snwhitehorn RZ_MTU_NUM_CHANNELS 123238051Sobrien}; 124219177Snwhitehorn 125219177Snwhitehorn/** 126158962Snetchild * struct rz_mtu3_channel - MTU3 channel private data 127295380Sngie * 128123311Speter * @dev: device handle 129297434Sbdrewery * @channel_number: channel number 130297988Sbdrewery * @lock: Lock to protect channel state 131296779Simp * @is_busy: channel state 132298107Sgjb */ 133298107Sgjbstruct rz_mtu3_channel { 134303359Sbdrewery struct device *dev; 135303359Sbdrewery unsigned int channel_number; 136209128Sraj struct mutex lock; 137301887Sbdrewery bool is_busy; 138301887Sbdrewery}; 139156740Sru 1402061Sjkh/** 14197769Sru * struct rz_mtu3 - MTU3 core private data 14297252Sru * 143119579Sru * @clk: MTU3 module clock 14497252Sru * @rz_mtu3_channel: HW channels 145301887Sbdrewery * @priv_data: MTU3 core driver private data 146301887Sbdrewery */ 147301887Sbdrewerystruct rz_mtu3 { 148301887Sbdrewery struct clk *clk; 149301887Sbdrewery struct rz_mtu3_channel channels[RZ_MTU_NUM_CHANNELS]; 150301887Sbdrewery 151301887Sbdrewery void *priv_data; 152301887Sbdrewery}; 153301887Sbdrewery 154302088Sbdrewerystatic inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch) 155303359Sbdrewery{ 156303359Sbdrewery mutex_lock(&ch->lock); 157302088Sbdrewery if (ch->is_busy) { 158301887Sbdrewery mutex_unlock(&ch->lock); 15995730Sru return false; 16095793Sru } 161111617Sru 162295161Sbdrewery ch->is_busy = true; 163296014Sbdrewery mutex_unlock(&ch->lock); 16495730Sru 165116679Ssimokawa return true; 16695730Sru} 167116679Ssimokawa 16895730Srustatic inline void rz_mtu3_release_channel(struct rz_mtu3_channel *ch) 169110035Sru{ 170107516Sru mutex_lock(&ch->lock); 171296549Sbdrewery ch->is_busy = false; 172293288Sbdrewery mutex_unlock(&ch->lock); 173293288Sbdrewery} 174293288Sbdrewery 175293288Sbdrewerybool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch); 176293288Sbdreweryvoid rz_mtu3_disable(struct rz_mtu3_channel *ch); 177293288Sbdreweryint rz_mtu3_enable(struct rz_mtu3_channel *ch); 178253616Ssjg 179253616Ssjgu8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 off); 180253616Ssjgu16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 off); 181253616Ssjgu32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 off); 182253616Ssjgu16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 off); 183253616Ssjg 184301466Sbdreweryvoid rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u8 val); 185301466Sbdreweryvoid rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u16 val); 186301466Sbdreweryvoid rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val); 187301466Sbdreweryvoid rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val); 188296646Sbdreweryvoid rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 off, 189296646Sbdrewery u16 pos, u8 val); 190301466Sbdrewery 191253616Ssjg#endif /* __MFD_RZ_MTU3_H__ */ 192253616Ssjg