155714Skris/* SPDX-License-Identifier: GPL-2.0-or-later */ 255714Skris/* 355714Skris * DaVinci Voice Codec Core Interface for TI platforms 455714Skris * 555714Skris * Copyright (C) 2010 Texas Instruments, Inc 655714Skris * 755714Skris * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com> 8280297Sjkim */ 955714Skris 1055714Skris#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_ 1155714Skris#define __LINUX_MFD_DAVINCI_VOICECODEC_H_ 1255714Skris 1355714Skris#include <linux/kernel.h> 1455714Skris#include <linux/platform_device.h> 15280297Sjkim#include <linux/mfd/core.h> 1655714Skris#include <linux/platform_data/edma.h> 1755714Skris 1855714Skrisstruct regmap; 1955714Skris 2055714Skris/* 2155714Skris * Register values. 22280297Sjkim */ 2355714Skris#define DAVINCI_VC_PID 0x00 2455714Skris#define DAVINCI_VC_CTRL 0x04 2555714Skris#define DAVINCI_VC_INTEN 0x08 2655714Skris#define DAVINCI_VC_INTSTATUS 0x0c 2755714Skris#define DAVINCI_VC_INTCLR 0x10 2855714Skris#define DAVINCI_VC_EMUL_CTRL 0x14 2955714Skris#define DAVINCI_VC_RFIFO 0x20 3055714Skris#define DAVINCI_VC_WFIFO 0x24 3155714Skris#define DAVINCI_VC_FIFOSTAT 0x28 3255714Skris#define DAVINCI_VC_TST_CTRL 0x2C 3355714Skris#define DAVINCI_VC_REG05 0x94 3455714Skris#define DAVINCI_VC_REG09 0xA4 3555714Skris#define DAVINCI_VC_REG12 0xB0 3655714Skris 37280297Sjkim/* DAVINCI_VC_CTRL bit fields */ 3855714Skris#define DAVINCI_VC_CTRL_MASK 0x5500 3955714Skris#define DAVINCI_VC_CTRL_RSTADC BIT(0) 40280297Sjkim#define DAVINCI_VC_CTRL_RSTDAC BIT(1) 4155714Skris#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4) 4255714Skris#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5) 4355714Skris#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6) 4455714Skris#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7) 4555714Skris#define DAVINCI_VC_CTRL_RFIFOEN BIT(8) 4655714Skris#define DAVINCI_VC_CTRL_RFIFOCL BIT(9) 4755714Skris#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10) 4855714Skris#define DAVINCI_VC_CTRL_WFIFOEN BIT(12) 4955714Skris#define DAVINCI_VC_CTRL_WFIFOCL BIT(13) 5055714Skris#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14) 5155714Skris 52280297Sjkim/* DAVINCI_VC_INT bit fields */ 5355714Skris#define DAVINCI_VC_INT_MASK 0x3F 5455714Skris#define DAVINCI_VC_INT_RDRDY_MASK BIT(0) 5555714Skris#define DAVINCI_VC_INT_RERROVF_MASK BIT(1) 5655714Skris#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2) 5755714Skris#define DAVINCI_VC_INT_WDREQ_MASK BIT(3) 5855714Skris#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4) 5955714Skris#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5) 6055714Skris 61109998Smarkm/* DAVINCI_VC_REG05 bit fields */ 6255714Skris#define DAVINCI_VC_REG05_PGA_GAIN 0x07 6355714Skris 64280297Sjkim/* DAVINCI_VC_REG09 bit fields */ 65280297Sjkim#define DAVINCI_VC_REG09_MUTE 0x40 66109998Smarkm#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F 67109998Smarkm 68109998Smarkm/* DAVINCI_VC_REG12 bit fields */ 69109998Smarkm#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD 70280297Sjkim#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00 71109998Smarkm 72109998Smarkm#define DAVINCI_VC_CELLS 2 73109998Smarkm 74109998Smarkmenum davinci_vc_cells { 75109998Smarkm DAVINCI_VC_VCIF_CELL, 76109998Smarkm DAVINCI_VC_CQ93VC_CELL, 77109998Smarkm}; 78109998Smarkm 79109998Smarkmstruct davinci_vcif { 80109998Smarkm struct platform_device *pdev; 81109998Smarkm u32 dma_tx_channel; 8255714Skris u32 dma_rx_channel; 83238405Sjkim dma_addr_t dma_tx_addr; 84280297Sjkim dma_addr_t dma_rx_addr; 85109998Smarkm}; 86280297Sjkim 8768651Skrisstruct davinci_vc { 88280297Sjkim /* Device data */ 89280297Sjkim struct device *dev; 90280297Sjkim struct platform_device *pdev; 91280297Sjkim struct clk *clk; 92280297Sjkim 93280297Sjkim /* Memory resources */ 94109998Smarkm void __iomem *base; 9555714Skris struct regmap *regmap; 96109998Smarkm 97280297Sjkim /* MFD cells */ 98280297Sjkim struct mfd_cell cells[DAVINCI_VC_CELLS]; 99280297Sjkim 100280297Sjkim /* Client devices */ 101280297Sjkim struct davinci_vcif davinci_vcif; 102280297Sjkim}; 103280297Sjkim 104109998Smarkm#endif 10555714Skris