1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. 4 */ 5#ifndef LINUX_DMAENGINE_H 6#define LINUX_DMAENGINE_H 7 8#include <linux/device.h> 9#include <linux/err.h> 10#include <linux/uio.h> 11#include <linux/bug.h> 12#include <linux/scatterlist.h> 13#include <linux/bitmap.h> 14#include <linux/types.h> 15#include <asm/page.h> 16 17/** 18 * typedef dma_cookie_t - an opaque DMA cookie 19 * 20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code 21 */ 22typedef s32 dma_cookie_t; 23#define DMA_MIN_COOKIE 1 24 25static inline int dma_submit_error(dma_cookie_t cookie) 26{ 27 return cookie < 0 ? cookie : 0; 28} 29 30/** 31 * enum dma_status - DMA transaction status 32 * @DMA_COMPLETE: transaction completed 33 * @DMA_IN_PROGRESS: transaction not yet processed 34 * @DMA_PAUSED: transaction is paused 35 * @DMA_ERROR: transaction failed 36 */ 37enum dma_status { 38 DMA_COMPLETE, 39 DMA_IN_PROGRESS, 40 DMA_PAUSED, 41 DMA_ERROR, 42 DMA_OUT_OF_ORDER, 43}; 44 45/** 46 * enum dma_transaction_type - DMA transaction types/indexes 47 * 48 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is 49 * automatically set as dma devices are registered. 50 */ 51enum dma_transaction_type { 52 DMA_MEMCPY, 53 DMA_XOR, 54 DMA_PQ, 55 DMA_XOR_VAL, 56 DMA_PQ_VAL, 57 DMA_MEMSET, 58 DMA_MEMSET_SG, 59 DMA_INTERRUPT, 60 DMA_PRIVATE, 61 DMA_ASYNC_TX, 62 DMA_SLAVE, 63 DMA_CYCLIC, 64 DMA_INTERLEAVE, 65 DMA_COMPLETION_NO_ORDER, 66 DMA_REPEAT, 67 DMA_LOAD_EOT, 68/* last transaction type for creation of the capabilities mask */ 69 DMA_TX_TYPE_END, 70}; 71 72/** 73 * enum dma_transfer_direction - dma transfer mode and direction indicator 74 * @DMA_MEM_TO_MEM: Async/Memcpy mode 75 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device 76 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory 77 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device 78 */ 79enum dma_transfer_direction { 80 DMA_MEM_TO_MEM, 81 DMA_MEM_TO_DEV, 82 DMA_DEV_TO_MEM, 83 DMA_DEV_TO_DEV, 84 DMA_TRANS_NONE, 85}; 86 87/** 88 * Interleaved Transfer Request 89 * ---------------------------- 90 * A chunk is collection of contiguous bytes to be transferred. 91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). 92 * ICGs may or may not change between chunks. 93 * A FRAME is the smallest series of contiguous {chunk,icg} pairs, 94 * that when repeated an integral number of times, specifies the transfer. 95 * A transfer template is specification of a Frame, the number of times 96 * it is to be repeated and other per-transfer attributes. 97 * 98 * Practically, a client driver would have ready a template for each 99 * type of transfer it is going to need during its lifetime and 100 * set only 'src_start' and 'dst_start' before submitting the requests. 101 * 102 * 103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' | 104 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| 105 * 106 * == Chunk size 107 * ... ICG 108 */ 109 110/** 111 * struct data_chunk - Element of scatter-gather list that makes a frame. 112 * @size: Number of bytes to read from source. 113 * size_dst := fn(op, size_src), so doesn't mean much for destination. 114 * @icg: Number of bytes to jump after last src/dst address of this 115 * chunk and before first src/dst address for next chunk. 116 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. 117 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. 118 * @dst_icg: Number of bytes to jump after last dst address of this 119 * chunk and before the first dst address for next chunk. 120 * Ignored if dst_inc is true and dst_sgl is false. 121 * @src_icg: Number of bytes to jump after last src address of this 122 * chunk and before the first src address for next chunk. 123 * Ignored if src_inc is true and src_sgl is false. 124 */ 125struct data_chunk { 126 size_t size; 127 size_t icg; 128 size_t dst_icg; 129 size_t src_icg; 130}; 131 132/** 133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern 134 * and attributes. 135 * @src_start: Bus address of source for the first chunk. 136 * @dst_start: Bus address of destination for the first chunk. 137 * @dir: Specifies the type of Source and Destination. 138 * @src_inc: If the source address increments after reading from it. 139 * @dst_inc: If the destination address increments after writing to it. 140 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). 141 * Otherwise, source is read contiguously (icg ignored). 142 * Ignored if src_inc is false. 143 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). 144 * Otherwise, destination is filled contiguously (icg ignored). 145 * Ignored if dst_inc is false. 146 * @numf: Number of frames in this template. 147 * @frame_size: Number of chunks in a frame i.e, size of sgl[]. 148 * @sgl: Array of {chunk,icg} pairs that make up a frame. 149 */ 150struct dma_interleaved_template { 151 dma_addr_t src_start; 152 dma_addr_t dst_start; 153 enum dma_transfer_direction dir; 154 bool src_inc; 155 bool dst_inc; 156 bool src_sgl; 157 bool dst_sgl; 158 size_t numf; 159 size_t frame_size; 160 struct data_chunk sgl[]; 161}; 162 163/** 164 * enum dma_ctrl_flags - DMA flags to augment operation preparation, 165 * control completion, and communicate status. 166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of 167 * this transaction 168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client 169 * acknowledges receipt, i.e. has a chance to establish any dependency 170 * chains 171 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q 172 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P 173 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as 174 * sources that were the result of a previous operation, in the case of a PQ 175 * operation it continues the calculation with new sources 176 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend 177 * on the result of this operation 178 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till 179 * cleared or freed 180 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command 181 * data and the descriptor should be in different format from normal 182 * data descriptors. 183 * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically 184 * repeated when it ends until a transaction is issued on the same channel 185 * with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to 186 * interleaved transactions and is ignored for all other transaction types. 187 * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any 188 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the 189 * repeated transaction ends. Not setting this flag when the previously queued 190 * transaction is marked with DMA_PREP_REPEAT will cause the new transaction 191 * to never be processed and stay in the issued queue forever. The flag is 192 * ignored if the previous transaction is not a repeated transaction. 193 */ 194enum dma_ctrl_flags { 195 DMA_PREP_INTERRUPT = (1 << 0), 196 DMA_CTRL_ACK = (1 << 1), 197 DMA_PREP_PQ_DISABLE_P = (1 << 2), 198 DMA_PREP_PQ_DISABLE_Q = (1 << 3), 199 DMA_PREP_CONTINUE = (1 << 4), 200 DMA_PREP_FENCE = (1 << 5), 201 DMA_CTRL_REUSE = (1 << 6), 202 DMA_PREP_CMD = (1 << 7), 203 DMA_PREP_REPEAT = (1 << 8), 204 DMA_PREP_LOAD_EOT = (1 << 9), 205}; 206 207/** 208 * enum sum_check_bits - bit position of pq_check_flags 209 */ 210enum sum_check_bits { 211 SUM_CHECK_P = 0, 212 SUM_CHECK_Q = 1, 213}; 214 215/** 216 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations 217 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise 218 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise 219 */ 220enum sum_check_flags { 221 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), 222 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), 223}; 224 225 226/** 227 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. 228 * See linux/cpumask.h 229 */ 230typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; 231 232/** 233 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported 234 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the 235 * client driver and it is attached (via the dmaengine_desc_attach_metadata() 236 * helper) to the descriptor. 237 * 238 * Client drivers interested to use this mode can follow: 239 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: 240 * 1. prepare the descriptor (dmaengine_prep_*) 241 * construct the metadata in the client's buffer 242 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the 243 * descriptor 244 * 3. submit the transfer 245 * - DMA_DEV_TO_MEM: 246 * 1. prepare the descriptor (dmaengine_prep_*) 247 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the 248 * descriptor 249 * 3. submit the transfer 250 * 4. when the transfer is completed, the metadata should be available in the 251 * attached buffer 252 * 253 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA 254 * driver. The client driver can ask for the pointer, maximum size and the 255 * currently used size of the metadata and can directly update or read it. 256 * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is 257 * provided as helper functions. 258 * 259 * Note: the metadata area for the descriptor is no longer valid after the 260 * transfer has been completed (valid up to the point when the completion 261 * callback returns if used). 262 * 263 * Client drivers interested to use this mode can follow: 264 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: 265 * 1. prepare the descriptor (dmaengine_prep_*) 266 * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's 267 * metadata area 268 * 3. update the metadata at the pointer 269 * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount 270 * of data the client has placed into the metadata buffer 271 * 5. submit the transfer 272 * - DMA_DEV_TO_MEM: 273 * 1. prepare the descriptor (dmaengine_prep_*) 274 * 2. submit the transfer 275 * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the 276 * pointer to the engine's metadata area 277 * 4. Read out the metadata from the pointer 278 * 279 * Note: the two mode is not compatible and clients must use one mode for a 280 * descriptor. 281 */ 282enum dma_desc_metadata_mode { 283 DESC_METADATA_NONE = 0, 284 DESC_METADATA_CLIENT = BIT(0), 285 DESC_METADATA_ENGINE = BIT(1), 286}; 287 288/** 289 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 290 * @memcpy_count: transaction counter 291 * @bytes_transferred: byte counter 292 */ 293struct dma_chan_percpu { 294 /* stats */ 295 unsigned long memcpy_count; 296 unsigned long bytes_transferred; 297}; 298 299/** 300 * struct dma_router - DMA router structure 301 * @dev: pointer to the DMA router device 302 * @route_free: function to be called when the route can be disconnected 303 */ 304struct dma_router { 305 struct device *dev; 306 void (*route_free)(struct device *dev, void *route_data); 307}; 308 309/** 310 * struct dma_chan - devices supply DMA channels, clients use them 311 * @device: ptr to the dma device who supplies this channel, always !%NULL 312 * @slave: ptr to the device using this channel 313 * @cookie: last cookie value returned to client 314 * @completed_cookie: last completed cookie for this channel 315 * @chan_id: channel ID for sysfs 316 * @dev: class device for sysfs 317 * @name: backlink name for sysfs 318 * @dbg_client_name: slave name for debugfs in format: 319 * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx" 320 * @device_node: used to add this to the device chan list 321 * @local: per-cpu pointer to a struct dma_chan_percpu 322 * @client_count: how many clients are using this channel 323 * @table_count: number of appearances in the mem-to-mem allocation table 324 * @router: pointer to the DMA router structure 325 * @route_data: channel specific data for the router 326 * @private: private data for certain client-channel associations 327 */ 328struct dma_chan { 329 struct dma_device *device; 330 struct device *slave; 331 dma_cookie_t cookie; 332 dma_cookie_t completed_cookie; 333 334 /* sysfs */ 335 int chan_id; 336 struct dma_chan_dev *dev; 337 const char *name; 338#ifdef CONFIG_DEBUG_FS 339 char *dbg_client_name; 340#endif 341 342 struct list_head device_node; 343 struct dma_chan_percpu __percpu *local; 344 int client_count; 345 int table_count; 346 347 /* DMA router */ 348 struct dma_router *router; 349 void *route_data; 350 351 void *private; 352}; 353 354/** 355 * struct dma_chan_dev - relate sysfs device node to backing channel device 356 * @chan: driver channel device 357 * @device: sysfs device 358 * @dev_id: parent dma_device dev_id 359 * @chan_dma_dev: The channel is using custom/different dma-mapping 360 * compared to the parent dma_device 361 */ 362struct dma_chan_dev { 363 struct dma_chan *chan; 364 struct device device; 365 int dev_id; 366 bool chan_dma_dev; 367}; 368 369/** 370 * enum dma_slave_buswidth - defines bus width of the DMA slave 371 * device, source or target buses 372 */ 373enum dma_slave_buswidth { 374 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, 375 DMA_SLAVE_BUSWIDTH_1_BYTE = 1, 376 DMA_SLAVE_BUSWIDTH_2_BYTES = 2, 377 DMA_SLAVE_BUSWIDTH_3_BYTES = 3, 378 DMA_SLAVE_BUSWIDTH_4_BYTES = 4, 379 DMA_SLAVE_BUSWIDTH_8_BYTES = 8, 380 DMA_SLAVE_BUSWIDTH_16_BYTES = 16, 381 DMA_SLAVE_BUSWIDTH_32_BYTES = 32, 382 DMA_SLAVE_BUSWIDTH_64_BYTES = 64, 383 DMA_SLAVE_BUSWIDTH_128_BYTES = 128, 384}; 385 386/** 387 * struct dma_slave_config - dma slave channel runtime config 388 * @direction: whether the data shall go in or out on this slave 389 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are 390 * legal values. DEPRECATED, drivers should use the direction argument 391 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or 392 * the dir field in the dma_interleaved_template structure. 393 * @src_addr: this is the physical address where DMA slave data 394 * should be read (RX), if the source is memory this argument is 395 * ignored. 396 * @dst_addr: this is the physical address where DMA slave data 397 * should be written (TX), if the destination is memory this argument 398 * is ignored. 399 * @src_addr_width: this is the width in bytes of the source (RX) 400 * register where DMA data shall be read. If the source 401 * is memory this may be ignored depending on architecture. 402 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64, 128. 403 * @dst_addr_width: same as src_addr_width but for destination 404 * target (TX) mutatis mutandis. 405 * @src_maxburst: the maximum number of words (note: words, as in 406 * units of the src_addr_width member, not bytes) that can be sent 407 * in one burst to the device. Typically something like half the 408 * FIFO depth on I/O peripherals so you don't overflow it. This 409 * may or may not be applicable on memory sources. 410 * @dst_maxburst: same as src_maxburst but for destination target 411 * mutatis mutandis. 412 * @src_port_window_size: The length of the register area in words the data need 413 * to be accessed on the device side. It is only used for devices which is using 414 * an area instead of a single register to receive the data. Typically the DMA 415 * loops in this area in order to transfer the data. 416 * @dst_port_window_size: same as src_port_window_size but for the destination 417 * port. 418 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill 419 * with 'true' if peripheral should be flow controller. Direction will be 420 * selected at Runtime. 421 * @peripheral_config: peripheral configuration for programming peripheral 422 * for dmaengine transfer 423 * @peripheral_size: peripheral configuration buffer size 424 * 425 * This struct is passed in as configuration data to a DMA engine 426 * in order to set up a certain channel for DMA transport at runtime. 427 * The DMA device/engine has to provide support for an additional 428 * callback in the dma_device structure, device_config and this struct 429 * will then be passed in as an argument to the function. 430 * 431 * The rationale for adding configuration information to this struct is as 432 * follows: if it is likely that more than one DMA slave controllers in 433 * the world will support the configuration option, then make it generic. 434 * If not: if it is fixed so that it be sent in static from the platform 435 * data, then prefer to do that. 436 */ 437struct dma_slave_config { 438 enum dma_transfer_direction direction; 439 phys_addr_t src_addr; 440 phys_addr_t dst_addr; 441 enum dma_slave_buswidth src_addr_width; 442 enum dma_slave_buswidth dst_addr_width; 443 u32 src_maxburst; 444 u32 dst_maxburst; 445 u32 src_port_window_size; 446 u32 dst_port_window_size; 447 bool device_fc; 448 void *peripheral_config; 449 size_t peripheral_size; 450}; 451 452/** 453 * enum dma_residue_granularity - Granularity of the reported transfer residue 454 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The 455 * DMA channel is only able to tell whether a descriptor has been completed or 456 * not, which means residue reporting is not supported by this channel. The 457 * residue field of the dma_tx_state field will always be 0. 458 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully 459 * completed segment of the transfer (For cyclic transfers this is after each 460 * period). This is typically implemented by having the hardware generate an 461 * interrupt after each transferred segment and then the drivers updates the 462 * outstanding residue by the size of the segment. Another possibility is if 463 * the hardware supports scatter-gather and the segment descriptor has a field 464 * which gets set after the segment has been completed. The driver then counts 465 * the number of segments without the flag set to compute the residue. 466 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred 467 * burst. This is typically only supported if the hardware has a progress 468 * register of some sort (E.g. a register with the current read/write address 469 * or a register with the amount of bursts/beats/bytes that have been 470 * transferred or still need to be transferred). 471 */ 472enum dma_residue_granularity { 473 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, 474 DMA_RESIDUE_GRANULARITY_SEGMENT = 1, 475 DMA_RESIDUE_GRANULARITY_BURST = 2, 476}; 477 478/** 479 * struct dma_slave_caps - expose capabilities of a slave channel only 480 * @src_addr_widths: bit mask of src addr widths the channel supports. 481 * Width is specified in bytes, e.g. for a channel supporting 482 * a width of 4 the mask should have BIT(4) set. 483 * @dst_addr_widths: bit mask of dst addr widths the channel supports 484 * @directions: bit mask of slave directions the channel supports. 485 * Since the enum dma_transfer_direction is not defined as bit flag for 486 * each type, the dma controller should set BIT(<TYPE>) and same 487 * should be checked by controller as well 488 * @min_burst: min burst capability per-transfer 489 * @max_burst: max burst capability per-transfer 490 * @max_sg_burst: max number of SG list entries executed in a single burst 491 * DMA tansaction with no software intervention for reinitialization. 492 * Zero value means unlimited number of entries. 493 * @cmd_pause: true, if pause is supported (i.e. for reading residue or 494 * for resume later) 495 * @cmd_resume: true, if resume is supported 496 * @cmd_terminate: true, if terminate cmd is supported 497 * @residue_granularity: granularity of the reported transfer residue 498 * @descriptor_reuse: if a descriptor can be reused by client and 499 * resubmitted multiple times 500 */ 501struct dma_slave_caps { 502 u32 src_addr_widths; 503 u32 dst_addr_widths; 504 u32 directions; 505 u32 min_burst; 506 u32 max_burst; 507 u32 max_sg_burst; 508 bool cmd_pause; 509 bool cmd_resume; 510 bool cmd_terminate; 511 enum dma_residue_granularity residue_granularity; 512 bool descriptor_reuse; 513}; 514 515static inline const char *dma_chan_name(struct dma_chan *chan) 516{ 517 return dev_name(&chan->dev->device); 518} 519 520/** 521 * typedef dma_filter_fn - callback filter for dma_request_channel 522 * @chan: channel to be reviewed 523 * @filter_param: opaque parameter passed through dma_request_channel 524 * 525 * When this optional parameter is specified in a call to dma_request_channel a 526 * suitable channel is passed to this routine for further dispositioning before 527 * being returned. Where 'suitable' indicates a non-busy channel that 528 * satisfies the given capability mask. It returns 'true' to indicate that the 529 * channel is suitable. 530 */ 531typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); 532 533typedef void (*dma_async_tx_callback)(void *dma_async_param); 534 535enum dmaengine_tx_result { 536 DMA_TRANS_NOERROR = 0, /* SUCCESS */ 537 DMA_TRANS_READ_FAILED, /* Source DMA read failed */ 538 DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */ 539 DMA_TRANS_ABORTED, /* Op never submitted / aborted */ 540}; 541 542struct dmaengine_result { 543 enum dmaengine_tx_result result; 544 u32 residue; 545}; 546 547typedef void (*dma_async_tx_callback_result)(void *dma_async_param, 548 const struct dmaengine_result *result); 549 550struct dmaengine_unmap_data { 551#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) 552 u16 map_cnt; 553#else 554 u8 map_cnt; 555#endif 556 u8 to_cnt; 557 u8 from_cnt; 558 u8 bidi_cnt; 559 struct device *dev; 560 struct kref kref; 561 size_t len; 562 dma_addr_t addr[]; 563}; 564 565struct dma_async_tx_descriptor; 566 567struct dma_descriptor_metadata_ops { 568 int (*attach)(struct dma_async_tx_descriptor *desc, void *data, 569 size_t len); 570 571 void *(*get_ptr)(struct dma_async_tx_descriptor *desc, 572 size_t *payload_len, size_t *max_len); 573 int (*set_len)(struct dma_async_tx_descriptor *desc, 574 size_t payload_len); 575}; 576 577/** 578 * struct dma_async_tx_descriptor - async transaction descriptor 579 * ---dma generic offload fields--- 580 * @cookie: tracking cookie for this transaction, set to -EBUSY if 581 * this tx is sitting on a dependency list 582 * @flags: flags to augment operation preparation, control completion, and 583 * communicate status 584 * @phys: physical address of the descriptor 585 * @chan: target channel for this operation 586 * @tx_submit: accept the descriptor, assign ordered cookie and mark the 587 * descriptor pending. To be pushed on .issue_pending() call 588 * @callback: routine to call after this operation is complete 589 * @callback_param: general parameter to pass to the callback routine 590 * @desc_metadata_mode: core managed metadata mode to protect mixed use of 591 * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise 592 * DESC_METADATA_NONE 593 * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the 594 * DMA driver if metadata mode is supported with the descriptor 595 * ---async_tx api specific fields--- 596 * @next: at completion submit this descriptor 597 * @parent: pointer to the next level up in the dependency chain 598 * @lock: protect the parent and next pointers 599 */ 600struct dma_async_tx_descriptor { 601 dma_cookie_t cookie; 602 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ 603 dma_addr_t phys; 604 struct dma_chan *chan; 605 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); 606 int (*desc_free)(struct dma_async_tx_descriptor *tx); 607 dma_async_tx_callback callback; 608 dma_async_tx_callback_result callback_result; 609 void *callback_param; 610 struct dmaengine_unmap_data *unmap; 611 enum dma_desc_metadata_mode desc_metadata_mode; 612 struct dma_descriptor_metadata_ops *metadata_ops; 613#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 614 struct dma_async_tx_descriptor *next; 615 struct dma_async_tx_descriptor *parent; 616 spinlock_t lock; 617#endif 618}; 619 620#ifdef CONFIG_DMA_ENGINE 621static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 622 struct dmaengine_unmap_data *unmap) 623{ 624 kref_get(&unmap->kref); 625 tx->unmap = unmap; 626} 627 628struct dmaengine_unmap_data * 629dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); 630void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); 631#else 632static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 633 struct dmaengine_unmap_data *unmap) 634{ 635} 636static inline struct dmaengine_unmap_data * 637dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) 638{ 639 return NULL; 640} 641static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) 642{ 643} 644#endif 645 646static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) 647{ 648 if (!tx->unmap) 649 return; 650 651 dmaengine_unmap_put(tx->unmap); 652 tx->unmap = NULL; 653} 654 655#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 656static inline void txd_lock(struct dma_async_tx_descriptor *txd) 657{ 658} 659static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 660{ 661} 662static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 663{ 664 BUG(); 665} 666static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 667{ 668} 669static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 670{ 671} 672static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 673{ 674 return NULL; 675} 676static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 677{ 678 return NULL; 679} 680 681#else 682static inline void txd_lock(struct dma_async_tx_descriptor *txd) 683{ 684 spin_lock_bh(&txd->lock); 685} 686static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 687{ 688 spin_unlock_bh(&txd->lock); 689} 690static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 691{ 692 txd->next = next; 693 next->parent = txd; 694} 695static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 696{ 697 txd->parent = NULL; 698} 699static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 700{ 701 txd->next = NULL; 702} 703static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 704{ 705 return txd->parent; 706} 707static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 708{ 709 return txd->next; 710} 711#endif 712 713/** 714 * struct dma_tx_state - filled in to report the status of 715 * a transfer. 716 * @last: last completed DMA cookie 717 * @used: last issued DMA cookie (i.e. the one in progress) 718 * @residue: the remaining number of bytes left to transmit 719 * on the selected transfer for states DMA_IN_PROGRESS and 720 * DMA_PAUSED if this is implemented in the driver, else 0 721 * @in_flight_bytes: amount of data in bytes cached by the DMA. 722 */ 723struct dma_tx_state { 724 dma_cookie_t last; 725 dma_cookie_t used; 726 u32 residue; 727 u32 in_flight_bytes; 728}; 729 730/** 731 * enum dmaengine_alignment - defines alignment of the DMA async tx 732 * buffers 733 */ 734enum dmaengine_alignment { 735 DMAENGINE_ALIGN_1_BYTE = 0, 736 DMAENGINE_ALIGN_2_BYTES = 1, 737 DMAENGINE_ALIGN_4_BYTES = 2, 738 DMAENGINE_ALIGN_8_BYTES = 3, 739 DMAENGINE_ALIGN_16_BYTES = 4, 740 DMAENGINE_ALIGN_32_BYTES = 5, 741 DMAENGINE_ALIGN_64_BYTES = 6, 742 DMAENGINE_ALIGN_128_BYTES = 7, 743 DMAENGINE_ALIGN_256_BYTES = 8, 744}; 745 746/** 747 * struct dma_slave_map - associates slave device and it's slave channel with 748 * parameter to be used by a filter function 749 * @devname: name of the device 750 * @slave: slave channel name 751 * @param: opaque parameter to pass to struct dma_filter.fn 752 */ 753struct dma_slave_map { 754 const char *devname; 755 const char *slave; 756 void *param; 757}; 758 759/** 760 * struct dma_filter - information for slave device/channel to filter_fn/param 761 * mapping 762 * @fn: filter function callback 763 * @mapcnt: number of slave device/channel in the map 764 * @map: array of channel to filter mapping data 765 */ 766struct dma_filter { 767 dma_filter_fn fn; 768 int mapcnt; 769 const struct dma_slave_map *map; 770}; 771 772/** 773 * struct dma_device - info on the entity supplying DMA services 774 * @ref: reference is taken and put every time a channel is allocated or freed 775 * @chancnt: how many DMA channels are supported 776 * @privatecnt: how many DMA channels are requested by dma_request_channel 777 * @channels: the list of struct dma_chan 778 * @global_node: list_head for global dma_device_list 779 * @filter: information for device/slave to filter function/param mapping 780 * @cap_mask: one or more dma_capability flags 781 * @desc_metadata_modes: supported metadata modes by the DMA device 782 * @max_xor: maximum number of xor sources, 0 if no capability 783 * @max_pq: maximum number of PQ sources and PQ-continue capability 784 * @copy_align: alignment shift for memcpy operations 785 * @xor_align: alignment shift for xor operations 786 * @pq_align: alignment shift for pq operations 787 * @fill_align: alignment shift for memset operations 788 * @dev_id: unique device ID 789 * @dev: struct device reference for dma mapping api 790 * @owner: owner module (automatically set based on the provided dev) 791 * @chan_ida: unique channel ID 792 * @src_addr_widths: bit mask of src addr widths the device supports 793 * Width is specified in bytes, e.g. for a device supporting 794 * a width of 4 the mask should have BIT(4) set. 795 * @dst_addr_widths: bit mask of dst addr widths the device supports 796 * @directions: bit mask of slave directions the device supports. 797 * Since the enum dma_transfer_direction is not defined as bit flag for 798 * each type, the dma controller should set BIT(<TYPE>) and same 799 * should be checked by controller as well 800 * @min_burst: min burst capability per-transfer 801 * @max_burst: max burst capability per-transfer 802 * @max_sg_burst: max number of SG list entries executed in a single burst 803 * DMA tansaction with no software intervention for reinitialization. 804 * Zero value means unlimited number of entries. 805 * @descriptor_reuse: a submitted transfer can be resubmitted after completion 806 * @residue_granularity: granularity of the transfer residue reported 807 * by tx_status 808 * @device_alloc_chan_resources: allocate resources and return the 809 * number of allocated descriptors 810 * @device_router_config: optional callback for DMA router configuration 811 * @device_free_chan_resources: release DMA channel's resources 812 * @device_prep_dma_memcpy: prepares a memcpy operation 813 * @device_prep_dma_xor: prepares a xor operation 814 * @device_prep_dma_xor_val: prepares a xor validation operation 815 * @device_prep_dma_pq: prepares a pq operation 816 * @device_prep_dma_pq_val: prepares a pqzero_sum operation 817 * @device_prep_dma_memset: prepares a memset operation 818 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list 819 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 820 * @device_prep_slave_sg: prepares a slave dma operation 821 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. 822 * The function takes a buffer of size buf_len. The callback function will 823 * be called after period_len bytes have been transferred. 824 * @device_prep_interleaved_dma: Transfer expression in a generic way. 825 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address 826 * @device_caps: May be used to override the generic DMA slave capabilities 827 * with per-channel specific ones 828 * @device_config: Pushes a new configuration to a channel, return 0 or an error 829 * code 830 * @device_pause: Pauses any transfer happening on a channel. Returns 831 * 0 or an error code 832 * @device_resume: Resumes any transfer on a channel previously 833 * paused. Returns 0 or an error code 834 * @device_terminate_all: Aborts all transfers on a channel. Returns 0 835 * or an error code 836 * @device_synchronize: Synchronizes the termination of a transfers to the 837 * current context. 838 * @device_tx_status: poll for transaction completion, the optional 839 * txstate parameter can be supplied with a pointer to get a 840 * struct with auxiliary transfer status information, otherwise the call 841 * will just return a simple status code 842 * @device_issue_pending: push pending transactions to hardware 843 * @device_release: called sometime atfer dma_async_device_unregister() is 844 * called and there are no further references to this structure. This 845 * must be implemented to free resources however many existing drivers 846 * do not and are therefore not safe to unbind while in use. 847 * @dbg_summary_show: optional routine to show contents in debugfs; default code 848 * will be used when this is omitted, but custom code can show extra, 849 * controller specific information. 850 * @dbg_dev_root: the root folder in debugfs for this device 851 */ 852struct dma_device { 853 struct kref ref; 854 unsigned int chancnt; 855 unsigned int privatecnt; 856 struct list_head channels; 857 struct list_head global_node; 858 struct dma_filter filter; 859 dma_cap_mask_t cap_mask; 860 enum dma_desc_metadata_mode desc_metadata_modes; 861 unsigned short max_xor; 862 unsigned short max_pq; 863 enum dmaengine_alignment copy_align; 864 enum dmaengine_alignment xor_align; 865 enum dmaengine_alignment pq_align; 866 enum dmaengine_alignment fill_align; 867 #define DMA_HAS_PQ_CONTINUE (1 << 15) 868 869 int dev_id; 870 struct device *dev; 871 struct module *owner; 872 struct ida chan_ida; 873 874 u32 src_addr_widths; 875 u32 dst_addr_widths; 876 u32 directions; 877 u32 min_burst; 878 u32 max_burst; 879 u32 max_sg_burst; 880 bool descriptor_reuse; 881 enum dma_residue_granularity residue_granularity; 882 883 int (*device_alloc_chan_resources)(struct dma_chan *chan); 884 int (*device_router_config)(struct dma_chan *chan); 885 void (*device_free_chan_resources)(struct dma_chan *chan); 886 887 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 888 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 889 size_t len, unsigned long flags); 890 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 891 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 892 unsigned int src_cnt, size_t len, unsigned long flags); 893 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( 894 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 895 size_t len, enum sum_check_flags *result, unsigned long flags); 896 struct dma_async_tx_descriptor *(*device_prep_dma_pq)( 897 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 898 unsigned int src_cnt, const unsigned char *scf, 899 size_t len, unsigned long flags); 900 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( 901 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 902 unsigned int src_cnt, const unsigned char *scf, size_t len, 903 enum sum_check_flags *pqres, unsigned long flags); 904 struct dma_async_tx_descriptor *(*device_prep_dma_memset)( 905 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 906 unsigned long flags); 907 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( 908 struct dma_chan *chan, struct scatterlist *sg, 909 unsigned int nents, int value, unsigned long flags); 910 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( 911 struct dma_chan *chan, unsigned long flags); 912 913 struct dma_async_tx_descriptor *(*device_prep_slave_sg)( 914 struct dma_chan *chan, struct scatterlist *sgl, 915 unsigned int sg_len, enum dma_transfer_direction direction, 916 unsigned long flags, void *context); 917 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( 918 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 919 size_t period_len, enum dma_transfer_direction direction, 920 unsigned long flags); 921 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( 922 struct dma_chan *chan, struct dma_interleaved_template *xt, 923 unsigned long flags); 924 struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)( 925 struct dma_chan *chan, dma_addr_t dst, u64 data, 926 unsigned long flags); 927 928 void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); 929 int (*device_config)(struct dma_chan *chan, struct dma_slave_config *config); 930 int (*device_pause)(struct dma_chan *chan); 931 int (*device_resume)(struct dma_chan *chan); 932 int (*device_terminate_all)(struct dma_chan *chan); 933 void (*device_synchronize)(struct dma_chan *chan); 934 935 enum dma_status (*device_tx_status)(struct dma_chan *chan, 936 dma_cookie_t cookie, 937 struct dma_tx_state *txstate); 938 void (*device_issue_pending)(struct dma_chan *chan); 939 void (*device_release)(struct dma_device *dev); 940 /* debugfs support */ 941 void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev); 942 struct dentry *dbg_dev_root; 943}; 944 945static inline int dmaengine_slave_config(struct dma_chan *chan, 946 struct dma_slave_config *config) 947{ 948 if (chan->device->device_config) 949 return chan->device->device_config(chan, config); 950 951 return -ENOSYS; 952} 953 954static inline bool is_slave_direction(enum dma_transfer_direction direction) 955{ 956 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM) || 957 (direction == DMA_DEV_TO_DEV); 958} 959 960static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( 961 struct dma_chan *chan, dma_addr_t buf, size_t len, 962 enum dma_transfer_direction dir, unsigned long flags) 963{ 964 struct scatterlist sg; 965 sg_init_table(&sg, 1); 966 sg_dma_address(&sg) = buf; 967 sg_dma_len(&sg) = len; 968 969 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 970 return NULL; 971 972 return chan->device->device_prep_slave_sg(chan, &sg, 1, 973 dir, flags, NULL); 974} 975 976static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( 977 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 978 enum dma_transfer_direction dir, unsigned long flags) 979{ 980 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 981 return NULL; 982 983 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 984 dir, flags, NULL); 985} 986 987#ifdef CONFIG_RAPIDIO_DMA_ENGINE 988struct rio_dma_ext; 989static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( 990 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 991 enum dma_transfer_direction dir, unsigned long flags, 992 struct rio_dma_ext *rio_ext) 993{ 994 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 995 return NULL; 996 997 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 998 dir, flags, rio_ext); 999} 1000#endif 1001 1002static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( 1003 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 1004 size_t period_len, enum dma_transfer_direction dir, 1005 unsigned long flags) 1006{ 1007 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) 1008 return NULL; 1009 1010 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, 1011 period_len, dir, flags); 1012} 1013 1014static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( 1015 struct dma_chan *chan, struct dma_interleaved_template *xt, 1016 unsigned long flags) 1017{ 1018 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) 1019 return NULL; 1020 if (flags & DMA_PREP_REPEAT && 1021 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits)) 1022 return NULL; 1023 1024 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 1025} 1026 1027/** 1028 * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor. 1029 * @chan: The channel to be used for this descriptor 1030 * @dest: Address of buffer to be set 1031 * @value: Treated as a single byte value that fills the destination buffer 1032 * @len: The total size of dest 1033 * @flags: DMA engine flags 1034 */ 1035static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( 1036 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 1037 unsigned long flags) 1038{ 1039 if (!chan || !chan->device || !chan->device->device_prep_dma_memset) 1040 return NULL; 1041 1042 return chan->device->device_prep_dma_memset(chan, dest, value, 1043 len, flags); 1044} 1045 1046static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy( 1047 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 1048 size_t len, unsigned long flags) 1049{ 1050 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy) 1051 return NULL; 1052 1053 return chan->device->device_prep_dma_memcpy(chan, dest, src, 1054 len, flags); 1055} 1056 1057static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, 1058 enum dma_desc_metadata_mode mode) 1059{ 1060 if (!chan) 1061 return false; 1062 1063 return !!(chan->device->desc_metadata_modes & mode); 1064} 1065 1066#ifdef CONFIG_DMA_ENGINE 1067int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, 1068 void *data, size_t len); 1069void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, 1070 size_t *payload_len, size_t *max_len); 1071int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, 1072 size_t payload_len); 1073#else /* CONFIG_DMA_ENGINE */ 1074static inline int dmaengine_desc_attach_metadata( 1075 struct dma_async_tx_descriptor *desc, void *data, size_t len) 1076{ 1077 return -EINVAL; 1078} 1079static inline void *dmaengine_desc_get_metadata_ptr( 1080 struct dma_async_tx_descriptor *desc, size_t *payload_len, 1081 size_t *max_len) 1082{ 1083 return NULL; 1084} 1085static inline int dmaengine_desc_set_metadata_len( 1086 struct dma_async_tx_descriptor *desc, size_t payload_len) 1087{ 1088 return -EINVAL; 1089} 1090#endif /* CONFIG_DMA_ENGINE */ 1091 1092/** 1093 * dmaengine_terminate_all() - Terminate all active DMA transfers 1094 * @chan: The channel for which to terminate the transfers 1095 * 1096 * This function is DEPRECATED use either dmaengine_terminate_sync() or 1097 * dmaengine_terminate_async() instead. 1098 */ 1099static inline int dmaengine_terminate_all(struct dma_chan *chan) 1100{ 1101 if (chan->device->device_terminate_all) 1102 return chan->device->device_terminate_all(chan); 1103 1104 return -ENOSYS; 1105} 1106 1107/** 1108 * dmaengine_terminate_async() - Terminate all active DMA transfers 1109 * @chan: The channel for which to terminate the transfers 1110 * 1111 * Calling this function will terminate all active and pending descriptors 1112 * that have previously been submitted to the channel. It is not guaranteed 1113 * though that the transfer for the active descriptor has stopped when the 1114 * function returns. Furthermore it is possible the complete callback of a 1115 * submitted transfer is still running when this function returns. 1116 * 1117 * dmaengine_synchronize() needs to be called before it is safe to free 1118 * any memory that is accessed by previously submitted descriptors or before 1119 * freeing any resources accessed from within the completion callback of any 1120 * previously submitted descriptors. 1121 * 1122 * This function can be called from atomic context as well as from within a 1123 * complete callback of a descriptor submitted on the same channel. 1124 * 1125 * If none of the two conditions above apply consider using 1126 * dmaengine_terminate_sync() instead. 1127 */ 1128static inline int dmaengine_terminate_async(struct dma_chan *chan) 1129{ 1130 if (chan->device->device_terminate_all) 1131 return chan->device->device_terminate_all(chan); 1132 1133 return -EINVAL; 1134} 1135 1136/** 1137 * dmaengine_synchronize() - Synchronize DMA channel termination 1138 * @chan: The channel to synchronize 1139 * 1140 * Synchronizes to the DMA channel termination to the current context. When this 1141 * function returns it is guaranteed that all transfers for previously issued 1142 * descriptors have stopped and it is safe to free the memory associated 1143 * with them. Furthermore it is guaranteed that all complete callback functions 1144 * for a previously submitted descriptor have finished running and it is safe to 1145 * free resources accessed from within the complete callbacks. 1146 * 1147 * The behavior of this function is undefined if dma_async_issue_pending() has 1148 * been called between dmaengine_terminate_async() and this function. 1149 * 1150 * This function must only be called from non-atomic context and must not be 1151 * called from within a complete callback of a descriptor submitted on the same 1152 * channel. 1153 */ 1154static inline void dmaengine_synchronize(struct dma_chan *chan) 1155{ 1156 might_sleep(); 1157 1158 if (chan->device->device_synchronize) 1159 chan->device->device_synchronize(chan); 1160} 1161 1162/** 1163 * dmaengine_terminate_sync() - Terminate all active DMA transfers 1164 * @chan: The channel for which to terminate the transfers 1165 * 1166 * Calling this function will terminate all active and pending transfers 1167 * that have previously been submitted to the channel. It is similar to 1168 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually 1169 * stopped and that all complete callbacks have finished running when the 1170 * function returns. 1171 * 1172 * This function must only be called from non-atomic context and must not be 1173 * called from within a complete callback of a descriptor submitted on the same 1174 * channel. 1175 */ 1176static inline int dmaengine_terminate_sync(struct dma_chan *chan) 1177{ 1178 int ret; 1179 1180 ret = dmaengine_terminate_async(chan); 1181 if (ret) 1182 return ret; 1183 1184 dmaengine_synchronize(chan); 1185 1186 return 0; 1187} 1188 1189static inline int dmaengine_pause(struct dma_chan *chan) 1190{ 1191 if (chan->device->device_pause) 1192 return chan->device->device_pause(chan); 1193 1194 return -ENOSYS; 1195} 1196 1197static inline int dmaengine_resume(struct dma_chan *chan) 1198{ 1199 if (chan->device->device_resume) 1200 return chan->device->device_resume(chan); 1201 1202 return -ENOSYS; 1203} 1204 1205static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, 1206 dma_cookie_t cookie, struct dma_tx_state *state) 1207{ 1208 return chan->device->device_tx_status(chan, cookie, state); 1209} 1210 1211static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) 1212{ 1213 return desc->tx_submit(desc); 1214} 1215 1216static inline bool dmaengine_check_align(enum dmaengine_alignment align, 1217 size_t off1, size_t off2, size_t len) 1218{ 1219 return !(((1 << align) - 1) & (off1 | off2 | len)); 1220} 1221 1222static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, 1223 size_t off2, size_t len) 1224{ 1225 return dmaengine_check_align(dev->copy_align, off1, off2, len); 1226} 1227 1228static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, 1229 size_t off2, size_t len) 1230{ 1231 return dmaengine_check_align(dev->xor_align, off1, off2, len); 1232} 1233 1234static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, 1235 size_t off2, size_t len) 1236{ 1237 return dmaengine_check_align(dev->pq_align, off1, off2, len); 1238} 1239 1240static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, 1241 size_t off2, size_t len) 1242{ 1243 return dmaengine_check_align(dev->fill_align, off1, off2, len); 1244} 1245 1246static inline void 1247dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) 1248{ 1249 dma->max_pq = maxpq; 1250 if (has_pq_continue) 1251 dma->max_pq |= DMA_HAS_PQ_CONTINUE; 1252} 1253 1254static inline bool dmaf_continue(enum dma_ctrl_flags flags) 1255{ 1256 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; 1257} 1258 1259static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) 1260{ 1261 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; 1262 1263 return (flags & mask) == mask; 1264} 1265 1266static inline bool dma_dev_has_pq_continue(struct dma_device *dma) 1267{ 1268 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; 1269} 1270 1271static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) 1272{ 1273 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; 1274} 1275 1276/* dma_maxpq - reduce maxpq in the face of continued operations 1277 * @dma - dma device with PQ capability 1278 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set 1279 * 1280 * When an engine does not support native continuation we need 3 extra 1281 * source slots to reuse P and Q with the following coefficients: 1282 * 1/ {00} * P : remove P from Q', but use it as a source for P' 1283 * 2/ {01} * Q : use Q to continue Q' calculation 1284 * 3/ {00} * Q : subtract Q from P' to cancel (2) 1285 * 1286 * In the case where P is disabled we only need 1 extra source: 1287 * 1/ {01} * Q : use Q to continue Q' calculation 1288 */ 1289static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) 1290{ 1291 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) 1292 return dma_dev_to_maxpq(dma); 1293 if (dmaf_p_disabled_continue(flags)) 1294 return dma_dev_to_maxpq(dma) - 1; 1295 if (dmaf_continue(flags)) 1296 return dma_dev_to_maxpq(dma) - 3; 1297 BUG(); 1298} 1299 1300static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, 1301 size_t dir_icg) 1302{ 1303 if (inc) { 1304 if (dir_icg) 1305 return dir_icg; 1306 if (sgl) 1307 return icg; 1308 } 1309 1310 return 0; 1311} 1312 1313static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, 1314 struct data_chunk *chunk) 1315{ 1316 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, 1317 chunk->icg, chunk->dst_icg); 1318} 1319 1320static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, 1321 struct data_chunk *chunk) 1322{ 1323 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, 1324 chunk->icg, chunk->src_icg); 1325} 1326 1327/* --- public DMA engine API --- */ 1328 1329#ifdef CONFIG_DMA_ENGINE 1330void dmaengine_get(void); 1331void dmaengine_put(void); 1332#else 1333static inline void dmaengine_get(void) 1334{ 1335} 1336static inline void dmaengine_put(void) 1337{ 1338} 1339#endif 1340 1341#ifdef CONFIG_ASYNC_TX_DMA 1342#define async_dmaengine_get() dmaengine_get() 1343#define async_dmaengine_put() dmaengine_put() 1344#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 1345#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) 1346#else 1347#define async_dma_find_channel(type) dma_find_channel(type) 1348#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ 1349#else 1350static inline void async_dmaengine_get(void) 1351{ 1352} 1353static inline void async_dmaengine_put(void) 1354{ 1355} 1356static inline struct dma_chan * 1357async_dma_find_channel(enum dma_transaction_type type) 1358{ 1359 return NULL; 1360} 1361#endif /* CONFIG_ASYNC_TX_DMA */ 1362void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, 1363 struct dma_chan *chan); 1364 1365static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) 1366{ 1367 tx->flags |= DMA_CTRL_ACK; 1368} 1369 1370static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) 1371{ 1372 tx->flags &= ~DMA_CTRL_ACK; 1373} 1374 1375static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) 1376{ 1377 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; 1378} 1379 1380#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) 1381static inline void 1382__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1383{ 1384 set_bit(tx_type, dstp->bits); 1385} 1386 1387#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) 1388static inline void 1389__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1390{ 1391 clear_bit(tx_type, dstp->bits); 1392} 1393 1394#define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 1395static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 1396{ 1397 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); 1398} 1399 1400#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) 1401static inline int 1402__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) 1403{ 1404 return test_bit(tx_type, srcp->bits); 1405} 1406 1407#define for_each_dma_cap_mask(cap, mask) \ 1408 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) 1409 1410/** 1411 * dma_async_issue_pending - flush pending transactions to HW 1412 * @chan: target DMA channel 1413 * 1414 * This allows drivers to push copies to HW in batches, 1415 * reducing MMIO writes where possible. 1416 */ 1417static inline void dma_async_issue_pending(struct dma_chan *chan) 1418{ 1419 chan->device->device_issue_pending(chan); 1420} 1421 1422/** 1423 * dma_async_is_tx_complete - poll for transaction completion 1424 * @chan: DMA channel 1425 * @cookie: transaction identifier to check status of 1426 * @last: returns last completed cookie, can be NULL 1427 * @used: returns last issued cookie, can be NULL 1428 * 1429 * If @last and @used are passed in, upon return they reflect the driver 1430 * internal state and can be used with dma_async_is_complete() to check 1431 * the status of multiple cookies without re-checking hardware state. 1432 */ 1433static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 1434 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 1435{ 1436 struct dma_tx_state state; 1437 enum dma_status status; 1438 1439 status = chan->device->device_tx_status(chan, cookie, &state); 1440 if (last) 1441 *last = state.last; 1442 if (used) 1443 *used = state.used; 1444 return status; 1445} 1446 1447/** 1448 * dma_async_is_complete - test a cookie against chan state 1449 * @cookie: transaction identifier to test status of 1450 * @last_complete: last know completed transaction 1451 * @last_used: last cookie value handed out 1452 * 1453 * dma_async_is_complete() is used in dma_async_is_tx_complete() 1454 * the test logic is separated for lightweight testing of multiple cookies 1455 */ 1456static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, 1457 dma_cookie_t last_complete, dma_cookie_t last_used) 1458{ 1459 if (last_complete <= last_used) { 1460 if ((cookie <= last_complete) || (cookie > last_used)) 1461 return DMA_COMPLETE; 1462 } else { 1463 if ((cookie <= last_complete) && (cookie > last_used)) 1464 return DMA_COMPLETE; 1465 } 1466 return DMA_IN_PROGRESS; 1467} 1468 1469static inline void 1470dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) 1471{ 1472 if (!st) 1473 return; 1474 1475 st->last = last; 1476 st->used = used; 1477 st->residue = residue; 1478} 1479 1480#ifdef CONFIG_DMA_ENGINE 1481struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); 1482enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); 1483enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); 1484void dma_issue_pending_all(void); 1485struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1486 dma_filter_fn fn, void *fn_param, 1487 struct device_node *np); 1488 1489struct dma_chan *dma_request_chan(struct device *dev, const char *name); 1490struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); 1491 1492void dma_release_channel(struct dma_chan *chan); 1493int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); 1494#else 1495static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) 1496{ 1497 return NULL; 1498} 1499static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) 1500{ 1501 return DMA_COMPLETE; 1502} 1503static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) 1504{ 1505 return DMA_COMPLETE; 1506} 1507static inline void dma_issue_pending_all(void) 1508{ 1509} 1510static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1511 dma_filter_fn fn, 1512 void *fn_param, 1513 struct device_node *np) 1514{ 1515 return NULL; 1516} 1517static inline struct dma_chan *dma_request_chan(struct device *dev, 1518 const char *name) 1519{ 1520 return ERR_PTR(-ENODEV); 1521} 1522static inline struct dma_chan *dma_request_chan_by_mask( 1523 const dma_cap_mask_t *mask) 1524{ 1525 return ERR_PTR(-ENODEV); 1526} 1527static inline void dma_release_channel(struct dma_chan *chan) 1528{ 1529} 1530static inline int dma_get_slave_caps(struct dma_chan *chan, 1531 struct dma_slave_caps *caps) 1532{ 1533 return -ENXIO; 1534} 1535#endif 1536 1537static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) 1538{ 1539 struct dma_slave_caps caps; 1540 int ret; 1541 1542 ret = dma_get_slave_caps(tx->chan, &caps); 1543 if (ret) 1544 return ret; 1545 1546 if (!caps.descriptor_reuse) 1547 return -EPERM; 1548 1549 tx->flags |= DMA_CTRL_REUSE; 1550 return 0; 1551} 1552 1553static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) 1554{ 1555 tx->flags &= ~DMA_CTRL_REUSE; 1556} 1557 1558static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) 1559{ 1560 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; 1561} 1562 1563static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) 1564{ 1565 /* this is supported for reusable desc, so check that */ 1566 if (!dmaengine_desc_test_reuse(desc)) 1567 return -EPERM; 1568 1569 return desc->desc_free(desc); 1570} 1571 1572/* --- DMA device --- */ 1573 1574int dma_async_device_register(struct dma_device *device); 1575int dmaenginem_async_device_register(struct dma_device *device); 1576void dma_async_device_unregister(struct dma_device *device); 1577int dma_async_device_channel_register(struct dma_device *device, 1578 struct dma_chan *chan); 1579void dma_async_device_channel_unregister(struct dma_device *device, 1580 struct dma_chan *chan); 1581void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1582#define dma_request_channel(mask, x, y) \ 1583 __dma_request_channel(&(mask), x, y, NULL) 1584 1585/* Deprecated, please use dma_request_chan() directly */ 1586static inline struct dma_chan * __deprecated 1587dma_request_slave_channel(struct device *dev, const char *name) 1588{ 1589 struct dma_chan *ch = dma_request_chan(dev, name); 1590 1591 return IS_ERR(ch) ? NULL : ch; 1592} 1593 1594static inline struct dma_chan 1595*dma_request_slave_channel_compat(const dma_cap_mask_t mask, 1596 dma_filter_fn fn, void *fn_param, 1597 struct device *dev, const char *name) 1598{ 1599 struct dma_chan *chan; 1600 1601 chan = dma_request_slave_channel(dev, name); 1602 if (chan) 1603 return chan; 1604 1605 if (!fn || !fn_param) 1606 return NULL; 1607 1608 return __dma_request_channel(&mask, fn, fn_param, NULL); 1609} 1610 1611static inline char * 1612dmaengine_get_direction_text(enum dma_transfer_direction dir) 1613{ 1614 switch (dir) { 1615 case DMA_DEV_TO_MEM: 1616 return "DEV_TO_MEM"; 1617 case DMA_MEM_TO_DEV: 1618 return "MEM_TO_DEV"; 1619 case DMA_MEM_TO_MEM: 1620 return "MEM_TO_MEM"; 1621 case DMA_DEV_TO_DEV: 1622 return "DEV_TO_DEV"; 1623 default: 1624 return "invalid"; 1625 } 1626} 1627 1628static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan) 1629{ 1630 if (chan->dev->chan_dma_dev) 1631 return &chan->dev->device; 1632 1633 return chan->device->dev; 1634} 1635 1636#endif /* DMAENGINE_H */ 1637