1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * UEFI Common Platform Error Record 4 * 5 * Copyright (C) 2010, Intel Corp. 6 * Author: Huang Ying <ying.huang@intel.com> 7 */ 8 9#ifndef LINUX_CPER_H 10#define LINUX_CPER_H 11 12#include <linux/uuid.h> 13#include <linux/trace_seq.h> 14 15/* CPER record signature and the size */ 16#define CPER_SIG_RECORD "CPER" 17#define CPER_SIG_SIZE 4 18/* Used in signature_end field in struct cper_record_header */ 19#define CPER_SIG_END 0xffffffff 20 21/* 22 * CPER record header revision, used in revision field in struct 23 * cper_record_header 24 */ 25#define CPER_RECORD_REV 0x0100 26 27/* 28 * CPER record length contains the CPER fields which are relevant for further 29 * handling of a memory error in userspace (we don't carry all the fields 30 * defined in the UEFI spec because some of them don't make any sense.) 31 * Currently, a length of 256 should be more than enough. 32 */ 33#define CPER_REC_LEN 256 34/* 35 * Severity definition for error_severity in struct cper_record_header 36 * and section_severity in struct cper_section_descriptor 37 */ 38enum { 39 CPER_SEV_RECOVERABLE, 40 CPER_SEV_FATAL, 41 CPER_SEV_CORRECTED, 42 CPER_SEV_INFORMATIONAL, 43}; 44 45/* 46 * Validation bits definition for validation_bits in struct 47 * cper_record_header. If set, corresponding fields in struct 48 * cper_record_header contain valid information. 49 */ 50#define CPER_VALID_PLATFORM_ID 0x0001 51#define CPER_VALID_TIMESTAMP 0x0002 52#define CPER_VALID_PARTITION_ID 0x0004 53 54/* 55 * Notification type used to generate error record, used in 56 * notification_type in struct cper_record_header. These UUIDs are defined 57 * in the UEFI spec v2.7, sec N.2.1. 58 */ 59 60/* Corrected Machine Check */ 61#define CPER_NOTIFY_CMC \ 62 GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \ 63 0xEB, 0xD4, 0xF8, 0x90) 64/* Corrected Platform Error */ 65#define CPER_NOTIFY_CPE \ 66 GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \ 67 0xF2, 0x7E, 0xBE, 0xEE) 68/* Machine Check Exception */ 69#define CPER_NOTIFY_MCE \ 70 GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \ 71 0xE1, 0x49, 0x13, 0xBB) 72/* PCI Express Error */ 73#define CPER_NOTIFY_PCIE \ 74 GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \ 75 0xAF, 0x67, 0xC1, 0x04) 76/* INIT Record (for IPF) */ 77#define CPER_NOTIFY_INIT \ 78 GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \ 79 0xD3, 0x9B, 0xC9, 0x8E) 80/* Non-Maskable Interrupt */ 81#define CPER_NOTIFY_NMI \ 82 GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \ 83 0x85, 0xD6, 0xE9, 0x8A) 84/* BOOT Error Record */ 85#define CPER_NOTIFY_BOOT \ 86 GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \ 87 0xD4, 0x64, 0xB3, 0x8F) 88/* DMA Remapping Error */ 89#define CPER_NOTIFY_DMAR \ 90 GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \ 91 0x72, 0x2D, 0xEB, 0x41) 92 93/* CXL Event record UUIDs are formatted as GUIDs and reported in section type */ 94/* 95 * General Media Event Record 96 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 97 */ 98#define CPER_SEC_CXL_GEN_MEDIA_GUID \ 99 GUID_INIT(0xfbcd0a77, 0xc260, 0x417f, \ 100 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6) 101/* 102 * DRAM Event Record 103 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 104 */ 105#define CPER_SEC_CXL_DRAM_GUID \ 106 GUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, \ 107 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24) 108/* 109 * Memory Module Event Record 110 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 111 */ 112#define CPER_SEC_CXL_MEM_MODULE_GUID \ 113 GUID_INIT(0xfe927475, 0xdd59, 0x4339, \ 114 0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74) 115 116/* 117 * Flags bits definitions for flags in struct cper_record_header 118 * If set, the error has been recovered 119 */ 120#define CPER_HW_ERROR_FLAGS_RECOVERED 0x1 121/* If set, the error is for previous boot */ 122#define CPER_HW_ERROR_FLAGS_PREVERR 0x2 123/* If set, the error is injected for testing */ 124#define CPER_HW_ERROR_FLAGS_SIMULATED 0x4 125 126/* 127 * CPER section header revision, used in revision field in struct 128 * cper_section_descriptor 129 */ 130#define CPER_SEC_REV 0x0100 131 132/* 133 * Validation bits definition for validation_bits in struct 134 * cper_section_descriptor. If set, corresponding fields in struct 135 * cper_section_descriptor contain valid information. 136 */ 137#define CPER_SEC_VALID_FRU_ID 0x1 138#define CPER_SEC_VALID_FRU_TEXT 0x2 139 140/* 141 * Flags bits definitions for flags in struct cper_section_descriptor 142 * 143 * If set, the section is associated with the error condition 144 * directly, and should be focused on 145 */ 146#define CPER_SEC_PRIMARY 0x0001 147/* 148 * If set, the error was not contained within the processor or memory 149 * hierarchy and the error may have propagated to persistent storage 150 * or network 151 */ 152#define CPER_SEC_CONTAINMENT_WARNING 0x0002 153/* If set, the component must be re-initialized or re-enabled prior to use */ 154#define CPER_SEC_RESET 0x0004 155/* If set, Linux may choose to discontinue use of the resource */ 156#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008 157/* 158 * If set, resource could not be queried for error information due to 159 * conflicts with other system software or resources. Some fields of 160 * the section will be invalid 161 */ 162#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010 163/* 164 * If set, action has been taken to ensure error containment (such as 165 * poisoning data), but the error has not been fully corrected and the 166 * data has not been consumed. Linux may choose to take further 167 * corrective action before the data is consumed 168 */ 169#define CPER_SEC_LATENT_ERROR 0x0020 170 171/* 172 * Section type definitions, used in section_type field in struct 173 * cper_section_descriptor. These UUIDs are defined in the UEFI spec 174 * v2.7, sec N.2.2. 175 */ 176 177/* Processor Generic */ 178#define CPER_SEC_PROC_GENERIC \ 179 GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \ 180 0x93, 0xC4, 0xF3, 0xDB) 181/* Processor Specific: X86/X86_64 */ 182#define CPER_SEC_PROC_IA \ 183 GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \ 184 0x24, 0x2B, 0x6E, 0x1D) 185/* Processor Specific: IA64 */ 186#define CPER_SEC_PROC_IPF \ 187 GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \ 188 0x80, 0xC7, 0x3C, 0x88, 0x81) 189/* Processor Specific: ARM */ 190#define CPER_SEC_PROC_ARM \ 191 GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \ 192 0x1D, 0x5D, 0x46, 0xB0) 193/* Platform Memory */ 194#define CPER_SEC_PLATFORM_MEM \ 195 GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ 196 0xED, 0x7C, 0x83, 0xB1) 197#define CPER_SEC_PCIE \ 198 GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \ 199 0xCB, 0x3C, 0x6F, 0x35) 200/* Firmware Error Record Reference */ 201#define CPER_SEC_FW_ERR_REC_REF \ 202 GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \ 203 0x9C, 0x8E, 0x69, 0xED) 204/* PCI/PCI-X Bus */ 205#define CPER_SEC_PCI_X_BUS \ 206 GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \ 207 0xD3, 0xF9, 0xC9, 0xDD) 208/* PCI Component/Device */ 209#define CPER_SEC_PCI_DEV \ 210 GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \ 211 0x8B, 0x00, 0x13, 0x26) 212#define CPER_SEC_DMAR_GENERIC \ 213 GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \ 214 0xDE, 0x3E, 0x2C, 0x64) 215/* Intel VT for Directed I/O specific DMAr */ 216#define CPER_SEC_DMAR_VT \ 217 GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \ 218 0xDD, 0x93, 0xE8, 0xCF) 219/* IOMMU specific DMAr */ 220#define CPER_SEC_DMAR_IOMMU \ 221 GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \ 222 0xDF, 0xAA, 0x84, 0xEC) 223 224#define CPER_PROC_VALID_TYPE 0x0001 225#define CPER_PROC_VALID_ISA 0x0002 226#define CPER_PROC_VALID_ERROR_TYPE 0x0004 227#define CPER_PROC_VALID_OPERATION 0x0008 228#define CPER_PROC_VALID_FLAGS 0x0010 229#define CPER_PROC_VALID_LEVEL 0x0020 230#define CPER_PROC_VALID_VERSION 0x0040 231#define CPER_PROC_VALID_BRAND_INFO 0x0080 232#define CPER_PROC_VALID_ID 0x0100 233#define CPER_PROC_VALID_TARGET_ADDRESS 0x0200 234#define CPER_PROC_VALID_REQUESTOR_ID 0x0400 235#define CPER_PROC_VALID_RESPONDER_ID 0x0800 236#define CPER_PROC_VALID_IP 0x1000 237 238#define CPER_MEM_VALID_ERROR_STATUS 0x0001 239#define CPER_MEM_VALID_PA 0x0002 240#define CPER_MEM_VALID_PA_MASK 0x0004 241#define CPER_MEM_VALID_NODE 0x0008 242#define CPER_MEM_VALID_CARD 0x0010 243#define CPER_MEM_VALID_MODULE 0x0020 244#define CPER_MEM_VALID_BANK 0x0040 245#define CPER_MEM_VALID_DEVICE 0x0080 246#define CPER_MEM_VALID_ROW 0x0100 247#define CPER_MEM_VALID_COLUMN 0x0200 248#define CPER_MEM_VALID_BIT_POSITION 0x0400 249#define CPER_MEM_VALID_REQUESTOR_ID 0x0800 250#define CPER_MEM_VALID_RESPONDER_ID 0x1000 251#define CPER_MEM_VALID_TARGET_ID 0x2000 252#define CPER_MEM_VALID_ERROR_TYPE 0x4000 253#define CPER_MEM_VALID_RANK_NUMBER 0x8000 254#define CPER_MEM_VALID_CARD_HANDLE 0x10000 255#define CPER_MEM_VALID_MODULE_HANDLE 0x20000 256#define CPER_MEM_VALID_ROW_EXT 0x40000 257#define CPER_MEM_VALID_BANK_GROUP 0x80000 258#define CPER_MEM_VALID_BANK_ADDRESS 0x100000 259#define CPER_MEM_VALID_CHIP_ID 0x200000 260 261#define CPER_MEM_EXT_ROW_MASK 0x3 262#define CPER_MEM_EXT_ROW_SHIFT 16 263 264#define CPER_MEM_BANK_ADDRESS_MASK 0xff 265#define CPER_MEM_BANK_GROUP_SHIFT 8 266 267#define CPER_MEM_CHIP_ID_SHIFT 5 268 269#define CPER_PCIE_VALID_PORT_TYPE 0x0001 270#define CPER_PCIE_VALID_VERSION 0x0002 271#define CPER_PCIE_VALID_COMMAND_STATUS 0x0004 272#define CPER_PCIE_VALID_DEVICE_ID 0x0008 273#define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010 274#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020 275#define CPER_PCIE_VALID_CAPABILITY 0x0040 276#define CPER_PCIE_VALID_AER_INFO 0x0080 277 278#define CPER_PCIE_SLOT_SHIFT 3 279 280#define CPER_ARM_VALID_MPIDR BIT(0) 281#define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1) 282#define CPER_ARM_VALID_RUNNING_STATE BIT(2) 283#define CPER_ARM_VALID_VENDOR_INFO BIT(3) 284 285#define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0) 286#define CPER_ARM_INFO_VALID_FLAGS BIT(1) 287#define CPER_ARM_INFO_VALID_ERR_INFO BIT(2) 288#define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3) 289#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4) 290 291#define CPER_ARM_INFO_FLAGS_FIRST BIT(0) 292#define CPER_ARM_INFO_FLAGS_LAST BIT(1) 293#define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2) 294#define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3) 295 296#define CPER_ARM_CACHE_ERROR 0 297#define CPER_ARM_TLB_ERROR 1 298#define CPER_ARM_BUS_ERROR 2 299#define CPER_ARM_VENDOR_ERROR 3 300#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR 301 302#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0) 303#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1) 304#define CPER_ARM_ERR_VALID_LEVEL BIT(2) 305#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3) 306#define CPER_ARM_ERR_VALID_CORRECTED BIT(4) 307#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5) 308#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6) 309#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7) 310#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8) 311#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9) 312#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10) 313#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11) 314 315#define CPER_ARM_ERR_TRANSACTION_SHIFT 16 316#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0) 317#define CPER_ARM_ERR_OPERATION_SHIFT 18 318#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0) 319#define CPER_ARM_ERR_LEVEL_SHIFT 22 320#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0) 321#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25 322#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0) 323#define CPER_ARM_ERR_CORRECTED_SHIFT 26 324#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0) 325#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27 326#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0) 327#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28 328#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0) 329#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29 330#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0) 331#define CPER_ARM_ERR_TIME_OUT_SHIFT 31 332#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0) 333#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32 334#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0) 335#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34 336#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0) 337#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43 338#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0) 339 340/* 341 * All tables and structs must be byte-packed to match CPER 342 * specification, since the tables are provided by the system BIOS 343 */ 344#pragma pack(1) 345 346/* Record Header, UEFI v2.7 sec N.2.1 */ 347struct cper_record_header { 348 char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */ 349 u16 revision; /* must be CPER_RECORD_REV */ 350 u32 signature_end; /* must be CPER_SIG_END */ 351 u16 section_count; 352 u32 error_severity; 353 u32 validation_bits; 354 u32 record_length; 355 u64 timestamp; 356 guid_t platform_id; 357 guid_t partition_id; 358 guid_t creator_id; 359 guid_t notification_type; 360 u64 record_id; 361 u32 flags; 362 u64 persistence_information; 363 u8 reserved[12]; /* must be zero */ 364}; 365 366/* Section Descriptor, UEFI v2.7 sec N.2.2 */ 367struct cper_section_descriptor { 368 u32 section_offset; /* Offset in bytes of the 369 * section body from the base 370 * of the record header */ 371 u32 section_length; 372 u16 revision; /* must be CPER_RECORD_REV */ 373 u8 validation_bits; 374 u8 reserved; /* must be zero */ 375 u32 flags; 376 guid_t section_type; 377 guid_t fru_id; 378 u32 section_severity; 379 u8 fru_text[20]; 380}; 381 382/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */ 383struct cper_sec_proc_generic { 384 u64 validation_bits; 385 u8 proc_type; 386 u8 proc_isa; 387 u8 proc_error_type; 388 u8 operation; 389 u8 flags; 390 u8 level; 391 u16 reserved; 392 u64 cpu_version; 393 char cpu_brand[128]; 394 u64 proc_id; 395 u64 target_addr; 396 u64 requestor_id; 397 u64 responder_id; 398 u64 ip; 399}; 400 401/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */ 402struct cper_sec_proc_ia { 403 u64 validation_bits; 404 u64 lapic_id; 405 u8 cpuid[48]; 406}; 407 408/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */ 409struct cper_ia_err_info { 410 guid_t err_type; 411 u64 validation_bits; 412 u64 check_info; 413 u64 target_id; 414 u64 requestor_id; 415 u64 responder_id; 416 u64 ip; 417}; 418 419/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */ 420struct cper_ia_proc_ctx { 421 u16 reg_ctx_type; 422 u16 reg_arr_size; 423 u32 msr_addr; 424 u64 mm_reg_addr; 425}; 426 427/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */ 428struct cper_sec_proc_arm { 429 u32 validation_bits; 430 u16 err_info_num; /* Number of Processor Error Info */ 431 u16 context_info_num; /* Number of Processor Context Info Records*/ 432 u32 section_length; 433 u8 affinity_level; 434 u8 reserved[3]; /* must be zero */ 435 u64 mpidr; 436 u64 midr; 437 u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */ 438 u32 psci_state; 439}; 440 441/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */ 442struct cper_arm_err_info { 443 u8 version; 444 u8 length; 445 u16 validation_bits; 446 u8 type; 447 u16 multiple_error; 448 u8 flags; 449 u64 error_info; 450 u64 virt_fault_addr; 451 u64 physical_fault_addr; 452}; 453 454/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */ 455struct cper_arm_ctx_info { 456 u16 version; 457 u16 type; 458 u32 size; 459}; 460 461/* Old Memory Error Section, UEFI v2.1, v2.2 */ 462struct cper_sec_mem_err_old { 463 u64 validation_bits; 464 u64 error_status; 465 u64 physical_addr; 466 u64 physical_addr_mask; 467 u16 node; 468 u16 card; 469 u16 module; 470 u16 bank; 471 u16 device; 472 u16 row; 473 u16 column; 474 u16 bit_pos; 475 u64 requestor_id; 476 u64 responder_id; 477 u64 target_id; 478 u8 error_type; 479}; 480 481/* Memory Error Section (UEFI >= v2.3), UEFI v2.8 sec N.2.5 */ 482struct cper_sec_mem_err { 483 u64 validation_bits; 484 u64 error_status; 485 u64 physical_addr; 486 u64 physical_addr_mask; 487 u16 node; 488 u16 card; 489 u16 module; 490 u16 bank; 491 u16 device; 492 u16 row; 493 u16 column; 494 u16 bit_pos; 495 u64 requestor_id; 496 u64 responder_id; 497 u64 target_id; 498 u8 error_type; 499 u8 extended; 500 u16 rank; 501 u16 mem_array_handle; /* "card handle" in UEFI 2.4 */ 502 u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */ 503}; 504 505struct cper_mem_err_compact { 506 u64 validation_bits; 507 u16 node; 508 u16 card; 509 u16 module; 510 u16 bank; 511 u16 device; 512 u16 row; 513 u16 column; 514 u16 bit_pos; 515 u64 requestor_id; 516 u64 responder_id; 517 u64 target_id; 518 u16 rank; 519 u16 mem_array_handle; 520 u16 mem_dev_handle; 521 u8 extended; 522}; 523 524static inline u32 cper_get_mem_extension(u64 mem_valid, u8 mem_extended) 525{ 526 if (!(mem_valid & CPER_MEM_VALID_ROW_EXT)) 527 return 0; 528 return (mem_extended & CPER_MEM_EXT_ROW_MASK) << CPER_MEM_EXT_ROW_SHIFT; 529} 530 531/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */ 532struct cper_sec_pcie { 533 u64 validation_bits; 534 u32 port_type; 535 struct { 536 u8 minor; 537 u8 major; 538 u8 reserved[2]; 539 } version; 540 u16 command; 541 u16 status; 542 u32 reserved; 543 struct { 544 u16 vendor_id; 545 u16 device_id; 546 u8 class_code[3]; 547 u8 function; 548 u8 device; 549 u16 segment; 550 u8 bus; 551 u8 secondary_bus; 552 u16 slot; 553 u8 reserved; 554 } device_id; 555 struct { 556 u32 lower; 557 u32 upper; 558 } serial_number; 559 struct { 560 u16 secondary_status; 561 u16 control; 562 } bridge; 563 u8 capability[60]; 564 u8 aer_info[96]; 565}; 566 567/* Firmware Error Record Reference, UEFI v2.7 sec N.2.10 */ 568struct cper_sec_fw_err_rec_ref { 569 u8 record_type; 570 u8 revision; 571 u8 reserved[6]; 572 u64 record_identifier; 573 guid_t record_identifier_guid; 574}; 575 576/* Reset to default packing */ 577#pragma pack() 578 579extern const char *const cper_proc_error_type_strs[4]; 580 581u64 cper_next_record_id(void); 582const char *cper_severity_str(unsigned int); 583const char *cper_mem_err_type_str(unsigned int); 584const char *cper_mem_err_status_str(u64 status); 585void cper_print_bits(const char *prefix, unsigned int bits, 586 const char * const strs[], unsigned int strs_size); 587void cper_mem_err_pack(const struct cper_sec_mem_err *, 588 struct cper_mem_err_compact *); 589const char *cper_mem_err_unpack(struct trace_seq *, 590 struct cper_mem_err_compact *); 591void cper_print_proc_arm(const char *pfx, 592 const struct cper_sec_proc_arm *proc); 593void cper_print_proc_ia(const char *pfx, 594 const struct cper_sec_proc_ia *proc); 595int cper_mem_err_location(struct cper_mem_err_compact *mem, char *msg); 596int cper_dimm_err_location(struct cper_mem_err_compact *mem, char *msg); 597 598struct acpi_hest_generic_status; 599void cper_estatus_print(const char *pfx, 600 const struct acpi_hest_generic_status *estatus); 601int cper_estatus_check_header(const struct acpi_hest_generic_status *estatus); 602int cper_estatus_check(const struct acpi_hest_generic_status *estatus); 603 604#endif 605