1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * include/linux/clk/at91_pmc.h 4 * 5 * Copyright (C) 2005 Ivan Kokshaysky 6 * Copyright (C) SAN People 7 * 8 * Power Management Controller (PMC) - System peripherals registers. 9 * Based on AT91RM9200 datasheet revision E. 10 */ 11 12#ifndef AT91_PMC_H 13#define AT91_PMC_H 14 15#include <linux/bits.h> 16 17#define AT91_PMC_V1 (1) /* PMC version 1 */ 18#define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */ 19 20#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ 21#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ 22 23#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ 24#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 25#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 26#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 27#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 28#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 29#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 30#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 31#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 32#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ 33#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ 34#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ 35#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 36#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 37 38#define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */ 39#define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */ 40#define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */ 41#define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */ 42 43#define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */ 44 45#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ 46#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ 47#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ 48 49#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */ 50#define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */ 51#define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */ 52#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */ 53#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */ 54 55#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ 56#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 57#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 58#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 59#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ 60 61#define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */ 62#define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */ 63#define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */ 64#define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */ 65#define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */ 66 67#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ 68#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 69#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ 70#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ 71#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ 72#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 73#define AT91_PMC_KEY_MASK (0xff << 16) 74#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ 75#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ 76#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ 77 78#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ 79#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ 80#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ 81 82#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ 83 84#define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */ 85#define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */ 86 87#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ 88#define AT91_PMC_DIV (0xff << 0) /* Divider */ 89#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 90#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 91#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ 92#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) 93#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ 94#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) 95#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ 96#define AT91_PMC_USBDIV_1 (0 << 28) 97#define AT91_PMC_USBDIV_2 (1 << 28) 98#define AT91_PMC_USBDIV_4 (2 << 28) 99#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 100 101#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */ 102 103#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ 104#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ 105#define AT91_PMC_CSS_SLOW (0 << 0) 106#define AT91_PMC_CSS_MAIN (1 << 0) 107#define AT91_PMC_CSS_PLLA (2 << 0) 108#define AT91_PMC_CSS_PLLB (3 << 0) 109#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ 110#define PMC_PRES_OFFSET 2 111#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ 112#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) 113#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) 114#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) 115#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) 116#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) 117#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) 118#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) 119#define PMC_ALT_PRES_OFFSET 4 120#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ 121#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) 122#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) 123#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) 124#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) 125#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) 126#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) 127#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) 128#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ 129#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ 130#define AT91RM9200_PMC_MDIV_2 (1 << 8) 131#define AT91RM9200_PMC_MDIV_3 (2 << 8) 132#define AT91RM9200_PMC_MDIV_4 (3 << 8) 133#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ 134#define AT91SAM9_PMC_MDIV_2 (1 << 8) 135#define AT91SAM9_PMC_MDIV_4 (2 << 8) 136#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ 137#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ 138#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ 139#define AT91_PMC_PDIV_1 (0 << 12) 140#define AT91_PMC_PDIV_2 (1 << 12) 141#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ 142#define AT91_PMC_PLLADIV2_OFF (0 << 12) 143#define AT91_PMC_PLLADIV2_ON (1 << 12) 144#define AT91_PMC_H32MXDIV BIT(24) 145 146#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */ 147#define AT91_PMC_MCR_V2_ID_MSK (0xF) 148#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK) 149#define AT91_PMC_MCR_V2_CMD (1 << 7) 150#define AT91_PMC_MCR_V2_DIV (7 << 8) 151#define AT91_PMC_MCR_V2_DIV1 (0 << 8) 152#define AT91_PMC_MCR_V2_DIV2 (1 << 8) 153#define AT91_PMC_MCR_V2_DIV4 (2 << 8) 154#define AT91_PMC_MCR_V2_DIV8 (3 << 8) 155#define AT91_PMC_MCR_V2_DIV16 (4 << 8) 156#define AT91_PMC_MCR_V2_DIV32 (5 << 8) 157#define AT91_PMC_MCR_V2_DIV64 (6 << 8) 158#define AT91_PMC_MCR_V2_DIV3 (7 << 8) 159#define AT91_PMC_MCR_V2_CSS (0x1F << 16) 160#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16) 161#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16) 162#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16) 163#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16) 164#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16) 165#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16) 166#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16) 167#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16) 168#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16) 169#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16) 170#define AT91_PMC_MCR_V2_EN (1 << 28) 171 172#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ 173 174#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ 175#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ 176#define AT91_PMC_USBS_PLLA (0 << 0) 177#define AT91_PMC_USBS_UPLL (1 << 0) 178#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ 179#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ 180#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) 181#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) 182 183#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ 184#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ 185#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ 186#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) 187 188#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ 189#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ 190#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ 191#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ 192#define AT91_PMC_CSSMCK_CSS (0 << 8) 193#define AT91_PMC_CSSMCK_MCK (1 << 8) 194 195#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ 196#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ 197#define AT91_PMC_SR 0x68 /* Status Register */ 198#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ 199#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 200#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 201#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 202#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ 203#define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */ 204#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 205#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 206#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 207#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ 208#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ 209#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ 210#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ 211#define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ 212#define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */ 213#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ 214 215#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ 216#define AT91_PMC_FSTT(n) BIT(n) 217#define AT91_PMC_RTTAL BIT(16) 218#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ 219#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ 220#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ 221#define AT91_PMC_LPM BIT(20) /* Low-power Mode */ 222#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ 223#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ 224 225#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */ 226 227#define AT91_PMC_FS_INPUT_MASK 0x7ff 228 229#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ 230 231#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ 232#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ 233#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ 234#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ 235 236#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ 237#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ 238#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ 239 240#define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */ 241 242#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ 243#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ 244#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ 245 246#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ 247#define AT91_PMC_PCR_PID_MASK 0x3f 248#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ 249#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20) 250#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ 251#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ 252 253#define AT91_PMC_AUDIO_PLL0 0x14c 254#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) 255#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) 256#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) 257#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) 258#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 259#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) 260#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) 261#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 262#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) 263#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) 264 265#define AT91_PMC_AUDIO_PLL1 0x150 266#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff 267#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 268#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) 269#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) 270#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 271#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) 272#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) 273#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 274#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f 275#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) 276#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) 277 278#endif 279