1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2015, 2016 ARM Ltd. 4 */ 5#ifndef __KVM_ARM_VGIC_H 6#define __KVM_ARM_VGIC_H 7 8#include <linux/bits.h> 9#include <linux/kvm.h> 10#include <linux/irqreturn.h> 11#include <linux/kref.h> 12#include <linux/mutex.h> 13#include <linux/spinlock.h> 14#include <linux/static_key.h> 15#include <linux/types.h> 16#include <linux/xarray.h> 17#include <kvm/iodev.h> 18#include <linux/list.h> 19#include <linux/jump_label.h> 20 21#include <linux/irqchip/arm-gic-v4.h> 22 23#define VGIC_V3_MAX_CPUS 512 24#define VGIC_V2_MAX_CPUS 8 25#define VGIC_NR_IRQS_LEGACY 256 26#define VGIC_NR_SGIS 16 27#define VGIC_NR_PPIS 16 28#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 29#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) 30#define VGIC_MAX_SPI 1019 31#define VGIC_MAX_RESERVED 1023 32#define VGIC_MIN_LPI 8192 33#define KVM_IRQCHIP_NUM_PINS (1020 - 32) 34 35#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) 36#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ 37 (irq) <= VGIC_MAX_SPI) 38 39enum vgic_type { 40 VGIC_V2, /* Good ol' GICv2 */ 41 VGIC_V3, /* New fancy GICv3 */ 42}; 43 44/* same for all guests, as depending only on the _host's_ GIC model */ 45struct vgic_global { 46 /* type of the host GIC */ 47 enum vgic_type type; 48 49 /* Physical address of vgic virtual cpu interface */ 50 phys_addr_t vcpu_base; 51 52 /* GICV mapping, kernel VA */ 53 void __iomem *vcpu_base_va; 54 /* GICV mapping, HYP VA */ 55 void __iomem *vcpu_hyp_va; 56 57 /* virtual control interface mapping, kernel VA */ 58 void __iomem *vctrl_base; 59 /* virtual control interface mapping, HYP VA */ 60 void __iomem *vctrl_hyp; 61 62 /* Number of implemented list registers */ 63 int nr_lr; 64 65 /* Maintenance IRQ number */ 66 unsigned int maint_irq; 67 68 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 69 int max_gic_vcpus; 70 71 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 72 bool can_emulate_gicv2; 73 74 /* Hardware has GICv4? */ 75 bool has_gicv4; 76 bool has_gicv4_1; 77 78 /* Pseudo GICv3 from outer space */ 79 bool no_hw_deactivation; 80 81 /* GIC system register CPU interface */ 82 struct static_key_false gicv3_cpuif; 83 84 u32 ich_vtr_el2; 85}; 86 87extern struct vgic_global kvm_vgic_global_state; 88 89#define VGIC_V2_MAX_LRS (1 << 6) 90#define VGIC_V3_MAX_LRS 16 91#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 92 93enum vgic_irq_config { 94 VGIC_CONFIG_EDGE = 0, 95 VGIC_CONFIG_LEVEL 96}; 97 98/* 99 * Per-irq ops overriding some common behavious. 100 * 101 * Always called in non-preemptible section and the functions can use 102 * kvm_arm_get_running_vcpu() to get the vcpu pointer for private IRQs. 103 */ 104struct irq_ops { 105 /* Per interrupt flags for special-cased interrupts */ 106 unsigned long flags; 107 108#define VGIC_IRQ_SW_RESAMPLE BIT(0) /* Clear the active state for resampling */ 109 110 /* 111 * Callback function pointer to in-kernel devices that can tell us the 112 * state of the input level of mapped level-triggered IRQ faster than 113 * peaking into the physical GIC. 114 */ 115 bool (*get_input_level)(int vintid); 116}; 117 118struct vgic_irq { 119 raw_spinlock_t irq_lock; /* Protects the content of the struct */ 120 struct rcu_head rcu; 121 struct list_head ap_list; 122 123 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU 124 * SPIs and LPIs: The VCPU whose ap_list 125 * this is queued on. 126 */ 127 128 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should 129 * be sent to, as a result of the 130 * targets reg (v2) or the 131 * affinity reg (v3). 132 */ 133 134 u32 intid; /* Guest visible INTID */ 135 bool line_level; /* Level only */ 136 bool pending_latch; /* The pending latch state used to calculate 137 * the pending state for both level 138 * and edge triggered IRQs. */ 139 bool active; /* not used for LPIs */ 140 bool enabled; 141 bool hw; /* Tied to HW IRQ */ 142 struct kref refcount; /* Used for LPIs */ 143 u32 hwintid; /* HW INTID number */ 144 unsigned int host_irq; /* linux irq corresponding to hwintid */ 145 union { 146 u8 targets; /* GICv2 target VCPUs mask */ 147 u32 mpidr; /* GICv3 target VCPU */ 148 }; 149 u8 source; /* GICv2 SGIs only */ 150 u8 active_source; /* GICv2 SGIs only */ 151 u8 priority; 152 u8 group; /* 0 == group 0, 1 == group 1 */ 153 enum vgic_irq_config config; /* Level or edge */ 154 155 struct irq_ops *ops; 156 157 void *owner; /* Opaque pointer to reserve an interrupt 158 for in-kernel devices. */ 159}; 160 161static inline bool vgic_irq_needs_resampling(struct vgic_irq *irq) 162{ 163 return irq->ops && (irq->ops->flags & VGIC_IRQ_SW_RESAMPLE); 164} 165 166struct vgic_register_region; 167struct vgic_its; 168 169enum iodev_type { 170 IODEV_CPUIF, 171 IODEV_DIST, 172 IODEV_REDIST, 173 IODEV_ITS 174}; 175 176struct vgic_io_device { 177 gpa_t base_addr; 178 union { 179 struct kvm_vcpu *redist_vcpu; 180 struct vgic_its *its; 181 }; 182 const struct vgic_register_region *regions; 183 enum iodev_type iodev_type; 184 int nr_regions; 185 struct kvm_io_device dev; 186}; 187 188struct vgic_its { 189 /* The base address of the ITS control register frame */ 190 gpa_t vgic_its_base; 191 192 bool enabled; 193 struct vgic_io_device iodev; 194 struct kvm_device *dev; 195 196 /* These registers correspond to GITS_BASER{0,1} */ 197 u64 baser_device_table; 198 u64 baser_coll_table; 199 200 /* Protects the command queue */ 201 struct mutex cmd_lock; 202 u64 cbaser; 203 u32 creadr; 204 u32 cwriter; 205 206 /* migration ABI revision in use */ 207 u32 abi_rev; 208 209 /* Protects the device and collection lists */ 210 struct mutex its_lock; 211 struct list_head device_list; 212 struct list_head collection_list; 213}; 214 215struct vgic_state_iter; 216 217struct vgic_redist_region { 218 u32 index; 219 gpa_t base; 220 u32 count; /* number of redistributors or 0 if single region */ 221 u32 free_index; /* index of the next free redistributor */ 222 struct list_head list; 223}; 224 225struct vgic_dist { 226 bool in_kernel; 227 bool ready; 228 bool initialized; 229 230 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 231 u32 vgic_model; 232 233 /* Implementation revision as reported in the GICD_IIDR */ 234 u32 implementation_rev; 235#define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */ 236#define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */ 237#define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3 238 239 /* Userspace can write to GICv2 IGROUPR */ 240 bool v2_groups_user_writable; 241 242 /* Do injected MSIs require an additional device ID? */ 243 bool msis_require_devid; 244 245 int nr_spis; 246 247 /* base addresses in guest physical address space: */ 248 gpa_t vgic_dist_base; /* distributor */ 249 union { 250 /* either a GICv2 CPU interface */ 251 gpa_t vgic_cpu_base; 252 /* or a number of GICv3 redistributor regions */ 253 struct list_head rd_regions; 254 }; 255 256 /* distributor enabled */ 257 bool enabled; 258 259 /* Wants SGIs without active state */ 260 bool nassgireq; 261 262 struct vgic_irq *spis; 263 264 struct vgic_io_device dist_iodev; 265 266 bool has_its; 267 bool table_write_in_progress; 268 269 /* 270 * Contains the attributes and gpa of the LPI configuration table. 271 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share 272 * one address across all redistributors. 273 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables" 274 */ 275 u64 propbaser; 276 277 /* Protects the lpi_list. */ 278 raw_spinlock_t lpi_list_lock; 279 struct xarray lpi_xa; 280 atomic_t lpi_count; 281 282 /* LPI translation cache */ 283 struct list_head lpi_translation_cache; 284 285 /* used by vgic-debug */ 286 struct vgic_state_iter *iter; 287 288 /* 289 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE 290 * array, the property table pointer as well as allocation 291 * data. This essentially ties the Linux IRQ core and ITS 292 * together, and avoids leaking KVM's data structures anywhere 293 * else. 294 */ 295 struct its_vm its_vm; 296}; 297 298struct vgic_v2_cpu_if { 299 u32 vgic_hcr; 300 u32 vgic_vmcr; 301 u32 vgic_apr; 302 u32 vgic_lr[VGIC_V2_MAX_LRS]; 303 304 unsigned int used_lrs; 305}; 306 307struct vgic_v3_cpu_if { 308 u32 vgic_hcr; 309 u32 vgic_vmcr; 310 u32 vgic_sre; /* Restored only, change ignored */ 311 u32 vgic_ap0r[4]; 312 u32 vgic_ap1r[4]; 313 u64 vgic_lr[VGIC_V3_MAX_LRS]; 314 315 /* 316 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the 317 * pending table pointer, the its_vm pointer and a few other 318 * HW specific things. As for the its_vm structure, this is 319 * linking the Linux IRQ subsystem and the ITS together. 320 */ 321 struct its_vpe its_vpe; 322 323 unsigned int used_lrs; 324}; 325 326struct vgic_cpu { 327 /* CPU vif control registers for world switch */ 328 union { 329 struct vgic_v2_cpu_if vgic_v2; 330 struct vgic_v3_cpu_if vgic_v3; 331 }; 332 333 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; 334 335 raw_spinlock_t ap_list_lock; /* Protects the ap_list */ 336 337 /* 338 * List of IRQs that this VCPU should consider because they are either 339 * Active or Pending (hence the name; AP list), or because they recently 340 * were one of the two and need to be migrated off this list to another 341 * VCPU. 342 */ 343 struct list_head ap_list_head; 344 345 /* 346 * Members below are used with GICv3 emulation only and represent 347 * parts of the redistributor. 348 */ 349 struct vgic_io_device rd_iodev; 350 struct vgic_redist_region *rdreg; 351 u32 rdreg_index; 352 atomic_t syncr_busy; 353 354 /* Contains the attributes and gpa of the LPI pending tables. */ 355 u64 pendbaser; 356 /* GICR_CTLR.{ENABLE_LPIS,RWP} */ 357 atomic_t ctlr; 358 359 /* Cache guest priority bits */ 360 u32 num_pri_bits; 361 362 /* Cache guest interrupt ID bits */ 363 u32 num_id_bits; 364}; 365 366extern struct static_key_false vgic_v2_cpuif_trap; 367extern struct static_key_false vgic_v3_cpuif_trap; 368 369int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr); 370void kvm_vgic_early_init(struct kvm *kvm); 371int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); 372int kvm_vgic_create(struct kvm *kvm, u32 type); 373void kvm_vgic_destroy(struct kvm *kvm); 374void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 375int kvm_vgic_map_resources(struct kvm *kvm); 376int kvm_vgic_hyp_init(void); 377void kvm_vgic_init_cpu_hardware(void); 378 379int kvm_vgic_inject_irq(struct kvm *kvm, struct kvm_vcpu *vcpu, 380 unsigned int intid, bool level, void *owner); 381int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, 382 u32 vintid, struct irq_ops *ops); 383int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid); 384int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid); 385bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); 386 387int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 388 389void kvm_vgic_load(struct kvm_vcpu *vcpu); 390void kvm_vgic_put(struct kvm_vcpu *vcpu); 391void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu); 392 393#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 394#define vgic_initialized(k) ((k)->arch.vgic.initialized) 395#define vgic_ready(k) ((k)->arch.vgic.ready) 396#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 397 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) 398 399bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 400void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 401void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 402void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); 403 404void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1); 405 406/** 407 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW 408 * 409 * The host's GIC naturally limits the maximum amount of VCPUs a guest 410 * can use. 411 */ 412static inline int kvm_vgic_get_max_vcpus(void) 413{ 414 return kvm_vgic_global_state.max_gic_vcpus; 415} 416 417/** 418 * kvm_vgic_setup_default_irq_routing: 419 * Setup a default flat gsi routing table mapping all SPIs 420 */ 421int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); 422 423int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner); 424 425struct kvm_kernel_irq_routing_entry; 426 427int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq, 428 struct kvm_kernel_irq_routing_entry *irq_entry); 429 430int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq, 431 struct kvm_kernel_irq_routing_entry *irq_entry); 432 433int vgic_v4_load(struct kvm_vcpu *vcpu); 434void vgic_v4_commit(struct kvm_vcpu *vcpu); 435int vgic_v4_put(struct kvm_vcpu *vcpu); 436 437/* CPU HP callbacks */ 438void kvm_vgic_cpu_up(void); 439void kvm_vgic_cpu_down(void); 440 441#endif /* __KVM_ARM_VGIC_H */ 442