1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ 3 4#ifndef __ABI_MACH_T194_RESET_H 5#define __ABI_MACH_T194_RESET_H 6 7#define TEGRA194_RESET_ACTMON 1 8#define TEGRA194_RESET_ADSP_ALL 2 9#define TEGRA194_RESET_AFI 3 10#define TEGRA194_RESET_CAN1 4 11#define TEGRA194_RESET_CAN2 5 12#define TEGRA194_RESET_DLA0 6 13#define TEGRA194_RESET_DLA1 7 14#define TEGRA194_RESET_DPAUX 8 15#define TEGRA194_RESET_DPAUX1 9 16#define TEGRA194_RESET_DPAUX2 10 17#define TEGRA194_RESET_DPAUX3 11 18#define TEGRA194_RESET_EQOS 17 19#define TEGRA194_RESET_GPCDMA 18 20#define TEGRA194_RESET_GPU 19 21#define TEGRA194_RESET_HDA 20 22#define TEGRA194_RESET_HDA2CODEC_2X 21 23#define TEGRA194_RESET_HDA2HDMICODEC 22 24#define TEGRA194_RESET_HOST1X 23 25#define TEGRA194_RESET_I2C1 24 26#define TEGRA194_RESET_I2C10 25 27#define TEGRA194_RESET_RSVD_26 26 28#define TEGRA194_RESET_RSVD_27 27 29#define TEGRA194_RESET_RSVD_28 28 30#define TEGRA194_RESET_I2C2 29 31#define TEGRA194_RESET_I2C3 30 32#define TEGRA194_RESET_I2C4 31 33#define TEGRA194_RESET_I2C6 32 34#define TEGRA194_RESET_I2C7 33 35#define TEGRA194_RESET_I2C8 34 36#define TEGRA194_RESET_I2C9 35 37#define TEGRA194_RESET_ISP 36 38#define TEGRA194_RESET_MIPI_CAL 37 39#define TEGRA194_RESET_MPHY_CLK_CTL 38 40#define TEGRA194_RESET_MPHY_L0_RX 39 41#define TEGRA194_RESET_MPHY_L0_TX 40 42#define TEGRA194_RESET_MPHY_L1_RX 41 43#define TEGRA194_RESET_MPHY_L1_TX 42 44#define TEGRA194_RESET_NVCSI 43 45#define TEGRA194_RESET_NVDEC 44 46#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45 47#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46 48#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47 49#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48 50#define TEGRA194_RESET_NVDISPLAY0_MISC 49 51#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50 52#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51 53#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52 54#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53 55#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54 56#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55 57#define TEGRA194_RESET_RSVD_56 56 58#define TEGRA194_RESET_RSVD_57 57 59#define TEGRA194_RESET_RSVD_58 58 60#define TEGRA194_RESET_NVENC 59 61#define TEGRA194_RESET_NVENC1 60 62#define TEGRA194_RESET_NVJPG 61 63#define TEGRA194_RESET_PCIE 62 64#define TEGRA194_RESET_PCIEXCLK 63 65#define TEGRA194_RESET_RSVD_64 64 66#define TEGRA194_RESET_RSVD_65 65 67#define TEGRA194_RESET_PVA0_ALL 66 68#define TEGRA194_RESET_PVA1_ALL 67 69#define TEGRA194_RESET_PWM1 68 70#define TEGRA194_RESET_PWM2 69 71#define TEGRA194_RESET_PWM3 70 72#define TEGRA194_RESET_PWM4 71 73#define TEGRA194_RESET_PWM5 72 74#define TEGRA194_RESET_PWM6 73 75#define TEGRA194_RESET_PWM7 74 76#define TEGRA194_RESET_PWM8 75 77#define TEGRA194_RESET_QSPI0 76 78#define TEGRA194_RESET_QSPI1 77 79#define TEGRA194_RESET_SATA 78 80#define TEGRA194_RESET_SATACOLD 79 81#define TEGRA194_RESET_SCE_ALL 80 82#define TEGRA194_RESET_RCE_ALL 81 83#define TEGRA194_RESET_SDMMC1 82 84#define TEGRA194_RESET_RSVD_83 83 85#define TEGRA194_RESET_SDMMC3 84 86#define TEGRA194_RESET_SDMMC4 85 87#define TEGRA194_RESET_SE 86 88#define TEGRA194_RESET_SOR0 87 89#define TEGRA194_RESET_SOR1 88 90#define TEGRA194_RESET_SOR2 89 91#define TEGRA194_RESET_SOR3 90 92#define TEGRA194_RESET_SPI1 91 93#define TEGRA194_RESET_SPI2 92 94#define TEGRA194_RESET_SPI3 93 95#define TEGRA194_RESET_SPI4 94 96#define TEGRA194_RESET_TACH 95 97#define TEGRA194_RESET_RSVD_96 96 98#define TEGRA194_RESET_TSCTNVI 97 99#define TEGRA194_RESET_TSEC 98 100#define TEGRA194_RESET_TSECB 99 101#define TEGRA194_RESET_UARTA 100 102#define TEGRA194_RESET_UARTB 101 103#define TEGRA194_RESET_UARTC 102 104#define TEGRA194_RESET_UARTD 103 105#define TEGRA194_RESET_UARTE 104 106#define TEGRA194_RESET_UARTF 105 107#define TEGRA194_RESET_UARTG 106 108#define TEGRA194_RESET_UARTH 107 109#define TEGRA194_RESET_UFSHC 108 110#define TEGRA194_RESET_UFSHC_AXI_M 109 111#define TEGRA194_RESET_UFSHC_LP_SEQ 110 112#define TEGRA194_RESET_RSVD_111 111 113#define TEGRA194_RESET_VI 112 114#define TEGRA194_RESET_VIC 113 115#define TEGRA194_RESET_XUSB_PADCTL 114 116#define TEGRA194_RESET_NVDEC1 115 117#define TEGRA194_RESET_PEX0_CORE_0 116 118#define TEGRA194_RESET_PEX0_CORE_1 117 119#define TEGRA194_RESET_PEX0_CORE_2 118 120#define TEGRA194_RESET_PEX0_CORE_3 119 121#define TEGRA194_RESET_PEX0_CORE_4 120 122#define TEGRA194_RESET_PEX0_CORE_0_APB 121 123#define TEGRA194_RESET_PEX0_CORE_1_APB 122 124#define TEGRA194_RESET_PEX0_CORE_2_APB 123 125#define TEGRA194_RESET_PEX0_CORE_3_APB 124 126#define TEGRA194_RESET_PEX0_CORE_4_APB 125 127#define TEGRA194_RESET_PEX0_COMMON_APB 126 128#define TEGRA194_RESET_PEX1_CORE_5 129 129#define TEGRA194_RESET_PEX1_CORE_5_APB 130 130#define TEGRA194_RESET_CVNAS 131 131#define TEGRA194_RESET_CVNAS_FCM 132 132#define TEGRA194_RESET_DMIC5 144 133#define TEGRA194_RESET_APE 145 134#define TEGRA194_RESET_PEX_USB_UPHY 146 135#define TEGRA194_RESET_PEX_USB_UPHY_L0 147 136#define TEGRA194_RESET_PEX_USB_UPHY_L1 148 137#define TEGRA194_RESET_PEX_USB_UPHY_L2 149 138#define TEGRA194_RESET_PEX_USB_UPHY_L3 150 139#define TEGRA194_RESET_PEX_USB_UPHY_L4 151 140#define TEGRA194_RESET_PEX_USB_UPHY_L5 152 141#define TEGRA194_RESET_PEX_USB_UPHY_L6 153 142#define TEGRA194_RESET_PEX_USB_UPHY_L7 154 143#define TEGRA194_RESET_PEX_USB_UPHY_L8 155 144#define TEGRA194_RESET_PEX_USB_UPHY_L9 156 145#define TEGRA194_RESET_PEX_USB_UPHY_L10 157 146#define TEGRA194_RESET_PEX_USB_UPHY_L11 158 147#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159 148#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160 149#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161 150#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162 151 152#endif 153