1272343Sngie/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2272343Sngie/* 3272343Sngie * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4272343Sngie * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> 5272343Sngie */ 6272343Sngie 7272343Sngie#ifndef _DT_BINDINGS_STM32MP25_RESET_H_ 8272343Sngie#define _DT_BINDINGS_STM32MP25_RESET_H_ 9272343Sngie 10272343Sngie#define TIM1_R 0 11272343Sngie#define TIM2_R 1 12272343Sngie#define TIM3_R 2 13272343Sngie#define TIM4_R 3 14272343Sngie#define TIM5_R 4 15272343Sngie#define TIM6_R 5 16272343Sngie#define TIM7_R 6 17272343Sngie#define TIM8_R 7 18272343Sngie#define TIM10_R 8 19272343Sngie#define TIM11_R 9 20272343Sngie#define TIM12_R 10 21272343Sngie#define TIM13_R 11 22272343Sngie#define TIM14_R 12 23272343Sngie#define TIM15_R 13 24272343Sngie#define TIM16_R 14 25272343Sngie#define TIM17_R 15 26272343Sngie#define TIM20_R 16 27272343Sngie#define LPTIM1_R 17 28272343Sngie#define LPTIM2_R 18 29272343Sngie#define LPTIM3_R 19 30272343Sngie#define LPTIM4_R 20 31272343Sngie#define LPTIM5_R 21 32272343Sngie#define SPI1_R 22 33272343Sngie#define SPI2_R 23 34272343Sngie#define SPI3_R 24 35272343Sngie#define SPI4_R 25 36272343Sngie#define SPI5_R 26 37272343Sngie#define SPI6_R 27 38272343Sngie#define SPI7_R 28 39272343Sngie#define SPI8_R 29 40272343Sngie#define SPDIFRX_R 30 41272343Sngie#define USART1_R 31 42272343Sngie#define USART2_R 32 43272343Sngie#define USART3_R 33 44272343Sngie#define UART4_R 34 45272343Sngie#define UART5_R 35 46272343Sngie#define USART6_R 36 47272343Sngie#define UART7_R 37 48272343Sngie#define UART8_R 38 49272343Sngie#define UART9_R 39 50272343Sngie#define LPUART1_R 40 51272343Sngie#define IS2M_R 41 52272343Sngie#define I2C1_R 42 53272343Sngie#define I2C2_R 43 54272343Sngie#define I2C3_R 44 55272343Sngie#define I2C4_R 45 56272343Sngie#define I2C5_R 46 57272343Sngie#define I2C6_R 47 58272343Sngie#define I2C7_R 48 59272343Sngie#define I2C8_R 49 60272343Sngie#define SAI1_R 50 61272343Sngie#define SAI2_R 51 62272343Sngie#define SAI3_R 52 63272343Sngie#define SAI4_R 53 64272343Sngie#define MDF1_R 54 65272343Sngie#define MDF2_R 55 66272343Sngie#define FDCAN_R 56 67272343Sngie#define HDP_R 57 68272343Sngie#define ADC12_R 58 69272343Sngie#define ADC3_R 59 70272343Sngie#define ETH1_R 60 71272343Sngie#define ETH2_R 61 72272343Sngie#define USBH_R 62 73#define USB2PHY1_R 63 74#define USB2PHY2_R 64 75#define USB3DR_R 65 76#define USB3PCIEPHY_R 66 77#define USBTC_R 67 78#define ETHSW_R 68 79#define SDMMC1_R 69 80#define SDMMC1DLL_R 70 81#define SDMMC2_R 71 82#define SDMMC2DLL_R 72 83#define SDMMC3_R 73 84#define SDMMC3DLL_R 74 85#define GPU_R 75 86#define LTDC_R 76 87#define DSI_R 77 88#define LVDS_R 78 89#define CSI_R 79 90#define DCMIPP_R 80 91#define CCI_R 81 92#define VDEC_R 82 93#define VENC_R 83 94#define WWDG1_R 84 95#define WWDG2_R 85 96#define VREF_R 86 97#define DTS_R 87 98#define CRC_R 88 99#define SERC_R 89 100#define OSPIIOM_R 90 101#define I3C1_R 91 102#define I3C2_R 92 103#define I3C3_R 93 104#define I3C4_R 94 105#define IWDG2_KER_R 95 106#define IWDG4_KER_R 96 107#define RNG_R 97 108#define PKA_R 98 109#define SAES_R 99 110#define HASH_R 100 111#define CRYP1_R 101 112#define CRYP2_R 102 113#define PCIE_R 103 114#define OSPI1_R 104 115#define OSPI1DLL_R 105 116#define OSPI2_R 106 117#define OSPI2DLL_R 107 118#define FMC_R 108 119#define DBG_R 109 120#define GPIOA_R 110 121#define GPIOB_R 111 122#define GPIOC_R 112 123#define GPIOD_R 113 124#define GPIOE_R 114 125#define GPIOF_R 115 126#define GPIOG_R 116 127#define GPIOH_R 117 128#define GPIOI_R 118 129#define GPIOJ_R 119 130#define GPIOK_R 120 131#define GPIOZ_R 121 132#define HPDMA1_R 122 133#define HPDMA2_R 123 134#define HPDMA3_R 124 135#define LPDMA_R 125 136#define HSEM_R 126 137#define IPCC1_R 127 138#define IPCC2_R 128 139#define C2_HOLDBOOT_R 129 140#define C1_HOLDBOOT_R 130 141#define C1_R 131 142#define C1P1POR_R 132 143#define C1P1_R 133 144#define C2_R 134 145#define C3_R 135 146#define SYS_R 136 147#define VSW_R 137 148#define C1MS_R 138 149#define DDRCP_R 139 150#define DDRCAPB_R 140 151#define DDRPHYCAPB_R 141 152#define DDRCFG_R 142 153#define DDR_R 143 154 155#define STM32MP25_LAST_RESET 144 156 157#define RST_SCMI_C1_R 0 158#define RST_SCMI_C2_R 1 159#define RST_SCMI_C1_HOLDBOOT_R 2 160#define RST_SCMI_C2_HOLDBOOT_R 3 161#define RST_SCMI_FMC 4 162#define RST_SCMI_OSPI1 5 163#define RST_SCMI_OSPI1DLL 6 164#define RST_SCMI_OSPI2 7 165#define RST_SCMI_OSPI2DLL 8 166 167#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */ 168