1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2017 MediaTek Inc.
4 * Author: Sean Wang <sean.wang@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
8#define _DT_BINDINGS_RESET_CONTROLLER_MT7622
9
10/* INFRACFG resets */
11#define MT7622_INFRA_EMI_REG_RST		0
12#define MT7622_INFRA_DRAMC0_A0_RST		1
13#define MT7622_INFRA_APCIRQ_EINT_RST		3
14#define MT7622_INFRA_APXGPT_RST			4
15#define MT7622_INFRA_SCPSYS_RST			5
16#define MT7622_INFRA_PMIC_WRAP_RST		7
17#define MT7622_INFRA_IRRX_RST			9
18#define MT7622_INFRA_EMI_RST			16
19#define MT7622_INFRA_WED0_RST			17
20#define MT7622_INFRA_DRAMC_RST			18
21#define MT7622_INFRA_CCI_INTF_RST		19
22#define MT7622_INFRA_TRNG_RST			21
23#define MT7622_INFRA_SYSIRQ_RST			22
24#define MT7622_INFRA_WED1_RST			25
25
26/* PERICFG Subsystem resets */
27#define MT7622_PERI_UART0_SW_RST		0
28#define MT7622_PERI_UART1_SW_RST		1
29#define MT7622_PERI_UART2_SW_RST		2
30#define MT7622_PERI_UART3_SW_RST		3
31#define MT7622_PERI_UART4_SW_RST		4
32#define MT7622_PERI_BTIF_SW_RST			6
33#define MT7622_PERI_PWM_SW_RST			8
34#define MT7622_PERI_AUXADC_SW_RST		10
35#define MT7622_PERI_DMA_SW_RST			11
36#define MT7622_PERI_IRTX_SW_RST			13
37#define MT7622_PERI_NFI_SW_RST			14
38#define MT7622_PERI_THERM_SW_RST		16
39#define MT7622_PERI_MSDC0_SW_RST		19
40#define MT7622_PERI_MSDC1_SW_RST		20
41#define MT7622_PERI_I2C0_SW_RST			22
42#define MT7622_PERI_I2C1_SW_RST			23
43#define MT7622_PERI_I2C2_SW_RST			24
44#define MT7622_PERI_SPI0_SW_RST			33
45#define MT7622_PERI_SPI1_SW_RST			34
46#define MT7622_PERI_FLASHIF_SW_RST		36
47
48/* TOPRGU resets */
49#define MT7622_TOPRGU_INFRA_RST			0
50#define MT7622_TOPRGU_ETHDMA_RST		1
51#define MT7622_TOPRGU_DDRPHY_RST		6
52#define MT7622_TOPRGU_INFRA_AO_RST		8
53#define MT7622_TOPRGU_CONN_RST			9
54#define MT7622_TOPRGU_APMIXED_RST		10
55#define MT7622_TOPRGU_CONN_MCU_RST		12
56
57/* PCIe/SATA Subsystem resets */
58#define MT7622_SATA_PHY_REG_RST			12
59#define MT7622_SATA_PHY_SW_RST			13
60#define MT7622_SATA_AXI_BUS_RST			15
61#define MT7622_PCIE1_CORE_RST			19
62#define MT7622_PCIE1_MMIO_RST			20
63#define MT7622_PCIE1_HRST			21
64#define MT7622_PCIE1_USER_RST			22
65#define MT7622_PCIE1_PIPE_RST			23
66#define MT7622_PCIE0_CORE_RST			27
67#define MT7622_PCIE0_MMIO_RST			28
68#define MT7622_PCIE0_HRST			29
69#define MT7622_PCIE0_USER_RST			30
70#define MT7622_PCIE0_PIPE_RST			31
71
72/* SSUSB Subsystem resets */
73#define MT7622_SSUSB_PHY_PWR_RST		3
74#define MT7622_SSUSB_MAC_PWR_RST		4
75
76/* ETHSYS Subsystem resets */
77#define MT7622_ETHSYS_SYS_RST			0
78#define MT7622_ETHSYS_MCM_RST			2
79#define MT7622_ETHSYS_HSDMA_RST			5
80#define MT7622_ETHSYS_FE_RST			6
81#define MT7622_ETHSYS_GMAC_RST			23
82#define MT7622_ETHSYS_EPHY_RST			24
83#define MT7622_ETHSYS_CRYPTO_RST		29
84#define MT7622_ETHSYS_PPE_RST			31
85
86#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */
87