1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2/* 3 * Copyright (c) 2023 Amlogic, Inc. All rights reserved. 4 */ 5 6#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H 7#define _DT_BINDINGS_AMLOGIC_C3_RESET_H 8 9/* RESET0 */ 10/* 0-3 */ 11#define RESET_USBCTRL 4 12/* 5-7 */ 13#define RESET_USBPHY20 8 14/* 9 */ 15#define RESET_USB2DRD 10 16#define RESET_MIPI_DSI_HOST 11 17#define RESET_MIPI_DSI_PHY 12 18/* 13-20 */ 19#define RESET_GE2D 21 20#define RESET_DWAP 22 21/* 23-31 */ 22 23/* RESET1 */ 24#define RESET_AUDIO 32 25/* 33-34 */ 26#define RESET_DDRAPB 35 27#define RESET_DDR 36 28#define RESET_DOS_CAPB3 37 29#define RESET_DOS 38 30/* 39-46 */ 31#define RESET_NNA 47 32#define RESET_ETHERNET 48 33#define RESET_ISP 49 34#define RESET_VC9000E_APB 50 35#define RESET_VC9000E_A 51 36/* 52 */ 37#define RESET_VC9000E_CORE 53 38/* 54-63 */ 39 40/* RESET2 */ 41#define RESET_ABUS_ARB 64 42#define RESET_IRCTRL 65 43/* 66 */ 44#define RESET_TEMP_PII 67 45/* 68-72 */ 46#define RESET_SPICC_0 73 47#define RESET_SPICC_1 74 48#define RESET_RSA 75 49 50/* 76-79 */ 51#define RESET_MSR_CLK 80 52#define RESET_SPIFC 81 53#define RESET_SAR_ADC 82 54/* 83-87 */ 55#define RESET_ACODEC 88 56/* 89-90 */ 57#define RESET_WATCHDOG 91 58/* 92-95 */ 59 60/* RESET3 */ 61#define RESET_ISP_NIC_GPV 96 62#define RESET_ISP_NIC_MAIN 97 63#define RESET_ISP_NIC_VCLK 98 64#define RESET_ISP_NIC_VOUT 99 65#define RESET_ISP_NIC_ALL 100 66#define RESET_VOUT 101 67#define RESET_VOUT_VENC 102 68/* 103 */ 69#define RESET_CVE_NIC_GPV 104 70#define RESET_CVE_NIC_MAIN 105 71#define RESET_CVE_NIC_GE2D 106 72#define RESET_CVE_NIC_DW 106 73#define RESET_CVE_NIC_CVE 108 74#define RESET_CVE_NIC_ALL 109 75#define RESET_CVE 110 76/* 112-127 */ 77 78/* RESET4 */ 79#define RESET_RTC 128 80#define RESET_PWM_AB 129 81#define RESET_PWM_CD 130 82#define RESET_PWM_EF 131 83#define RESET_PWM_GH 132 84#define RESET_PWM_IJ 133 85#define RESET_PWM_KL 134 86#define RESET_PWM_MN 135 87/* 136-137 */ 88#define RESET_UART_A 138 89#define RESET_UART_B 139 90#define RESET_UART_C 140 91#define RESET_UART_D 141 92#define RESET_UART_E 142 93#define RESET_UART_F 143 94#define RESET_I2C_S_A 144 95#define RESET_I2C_M_A 145 96#define RESET_I2C_M_B 146 97#define RESET_I2C_M_C 147 98#define RESET_I2C_M_D 148 99/* 149-151 */ 100#define RESET_SD_EMMC_A 152 101#define RESET_SD_EMMC_B 153 102#define RESET_SD_EMMC_C 154 103 104/* RESET5 */ 105/* 160-172 */ 106#define RESET_BRG_NIC_NNA 173 107#define RESET_BRG_MUX_NIC_MAIN 174 108#define RESET_BRG_AO_NIC_ALL 175 109/* 176-183 */ 110#define RESET_BRG_NIC_VAPB 184 111#define RESET_BRG_NIC_SDIO_B 185 112#define RESET_BRG_NIC_SDIO_A 186 113#define RESET_BRG_NIC_EMMC 187 114#define RESET_BRG_NIC_DSU 188 115#define RESET_BRG_NIC_SYSCLK 189 116#define RESET_BRG_NIC_MAIN 190 117#define RESET_BRG_NIC_ALL 191 118 119#endif 120