1#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H 2#define DT_BINDINGS_MEMORY_TEGRA194_MC_H 3 4/* special clients */ 5#define TEGRA194_SID_INVALID 0x00 6#define TEGRA194_SID_PASSTHROUGH 0x7f 7 8/* host1x clients */ 9#define TEGRA194_SID_HOST1X 0x01 10#define TEGRA194_SID_CSI 0x02 11#define TEGRA194_SID_VIC 0x03 12#define TEGRA194_SID_VI 0x04 13#define TEGRA194_SID_ISP 0x05 14#define TEGRA194_SID_NVDEC 0x06 15#define TEGRA194_SID_NVENC 0x07 16#define TEGRA194_SID_NVJPG 0x08 17#define TEGRA194_SID_NVDISPLAY 0x09 18#define TEGRA194_SID_TSEC 0x0a 19#define TEGRA194_SID_TSECB 0x0b 20#define TEGRA194_SID_SE 0x0c 21#define TEGRA194_SID_SE1 0x0d 22#define TEGRA194_SID_SE2 0x0e 23#define TEGRA194_SID_SE3 0x0f 24 25/* GPU clients */ 26#define TEGRA194_SID_GPU 0x10 27 28/* other SoC clients */ 29#define TEGRA194_SID_AFI 0x11 30#define TEGRA194_SID_HDA 0x12 31#define TEGRA194_SID_ETR 0x13 32#define TEGRA194_SID_EQOS 0x14 33#define TEGRA194_SID_UFSHC 0x15 34#define TEGRA194_SID_AON 0x16 35#define TEGRA194_SID_SDMMC4 0x17 36#define TEGRA194_SID_SDMMC3 0x18 37#define TEGRA194_SID_SDMMC2 0x19 38#define TEGRA194_SID_SDMMC1 0x1a 39#define TEGRA194_SID_XUSB_HOST 0x1b 40#define TEGRA194_SID_XUSB_DEV 0x1c 41#define TEGRA194_SID_SATA 0x1d 42#define TEGRA194_SID_APE 0x1e 43#define TEGRA194_SID_SCE 0x1f 44 45/* GPC DMA clients */ 46#define TEGRA194_SID_GPCDMA_0 0x20 47#define TEGRA194_SID_GPCDMA_1 0x21 48#define TEGRA194_SID_GPCDMA_2 0x22 49#define TEGRA194_SID_GPCDMA_3 0x23 50#define TEGRA194_SID_GPCDMA_4 0x24 51#define TEGRA194_SID_GPCDMA_5 0x25 52#define TEGRA194_SID_GPCDMA_6 0x26 53#define TEGRA194_SID_GPCDMA_7 0x27 54 55/* APE DMA clients */ 56#define TEGRA194_SID_APE_1 0x28 57#define TEGRA194_SID_APE_2 0x29 58 59/* camera RTCPU */ 60#define TEGRA194_SID_RCE 0x2a 61 62/* camera RTCPU on host1x address space */ 63#define TEGRA194_SID_RCE_1X 0x2b 64 65/* APE DMA clients */ 66#define TEGRA194_SID_APE_3 0x2c 67 68/* camera RTCPU running on APE */ 69#define TEGRA194_SID_APE_CAM 0x2d 70#define TEGRA194_SID_APE_CAM_1X 0x2e 71 72#define TEGRA194_SID_RCE_RM 0x2f 73#define TEGRA194_SID_VI_FALCON 0x30 74#define TEGRA194_SID_ISP_FALCON 0x31 75 76/* 77 * The BPMP has its SID value hardcoded in the firmware. Changing it requires 78 * considerable effort. 79 */ 80#define TEGRA194_SID_BPMP 0x32 81 82/* for SMMU tests */ 83#define TEGRA194_SID_SMMU_TEST 0x33 84 85/* host1x virtualization channels */ 86#define TEGRA194_SID_HOST1X_CTX0 0x38 87#define TEGRA194_SID_HOST1X_CTX1 0x39 88#define TEGRA194_SID_HOST1X_CTX2 0x3a 89#define TEGRA194_SID_HOST1X_CTX3 0x3b 90#define TEGRA194_SID_HOST1X_CTX4 0x3c 91#define TEGRA194_SID_HOST1X_CTX5 0x3d 92#define TEGRA194_SID_HOST1X_CTX6 0x3e 93#define TEGRA194_SID_HOST1X_CTX7 0x3f 94 95/* host1x command buffers */ 96#define TEGRA194_SID_HOST1X_VM0 0x40 97#define TEGRA194_SID_HOST1X_VM1 0x41 98#define TEGRA194_SID_HOST1X_VM2 0x42 99#define TEGRA194_SID_HOST1X_VM3 0x43 100#define TEGRA194_SID_HOST1X_VM4 0x44 101#define TEGRA194_SID_HOST1X_VM5 0x45 102#define TEGRA194_SID_HOST1X_VM6 0x46 103#define TEGRA194_SID_HOST1X_VM7 0x47 104 105/* SE data buffers */ 106#define TEGRA194_SID_SE_VM0 0x48 107#define TEGRA194_SID_SE_VM1 0x49 108#define TEGRA194_SID_SE_VM2 0x4a 109#define TEGRA194_SID_SE_VM3 0x4b 110#define TEGRA194_SID_SE_VM4 0x4c 111#define TEGRA194_SID_SE_VM5 0x4d 112#define TEGRA194_SID_SE_VM6 0x4e 113#define TEGRA194_SID_SE_VM7 0x4f 114 115#define TEGRA194_SID_MIU 0x50 116 117#define TEGRA194_SID_NVDLA0 0x51 118#define TEGRA194_SID_NVDLA1 0x52 119 120#define TEGRA194_SID_PVA0 0x53 121#define TEGRA194_SID_PVA1 0x54 122#define TEGRA194_SID_NVENC1 0x55 123#define TEGRA194_SID_PCIE0 0x56 124#define TEGRA194_SID_PCIE1 0x57 125#define TEGRA194_SID_PCIE2 0x58 126#define TEGRA194_SID_PCIE3 0x59 127#define TEGRA194_SID_PCIE4 0x5a 128#define TEGRA194_SID_PCIE5 0x5b 129#define TEGRA194_SID_NVDEC1 0x5c 130 131#define TEGRA194_SID_XUSB_VF0 0x5d 132#define TEGRA194_SID_XUSB_VF1 0x5e 133#define TEGRA194_SID_XUSB_VF2 0x5f 134#define TEGRA194_SID_XUSB_VF3 0x60 135 136#define TEGRA194_SID_RCE_VM3 0x61 137#define TEGRA194_SID_VI_VM2 0x62 138#define TEGRA194_SID_VI_VM3 0x63 139#define TEGRA194_SID_RCE_SERVER 0x64 140 141/* 142 * memory client IDs 143 */ 144 145/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 146#define TEGRA194_MEMORY_CLIENT_PTCR 0x00 147/* MSS internal memqual MIU7 read clients */ 148#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 149/* MSS internal memqual MIU7 write clients */ 150#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 151/* High-definition audio (HDA) read clients */ 152#define TEGRA194_MEMORY_CLIENT_HDAR 0x15 153/* Host channel data read clients */ 154#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 155#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c 156/* SATA read clients */ 157#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f 158/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 159#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 160#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b 161/* High-definition audio (HDA) write clients */ 162#define TEGRA194_MEMORY_CLIENT_HDAW 0x35 163/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 164#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 165/* SATA write clients */ 166#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d 167/* ISP read client for Crossbar A */ 168#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 169/* ISP read client 1 for Crossbar A */ 170#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 171/* ISP Write client for Crossbar A */ 172#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 173/* ISP Write client Crossbar B */ 174#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 175/* XUSB_HOST read clients */ 176#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a 177/* XUSB_HOST write clients */ 178#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b 179/* XUSB read clients */ 180#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c 181/* XUSB_DEV write clients */ 182#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d 183/* sdmmca memory read client */ 184#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 185/* sdmmc memory read client */ 186#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 187/* sdmmcd memory read client */ 188#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 189/* sdmmca memory write client */ 190#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 191/* sdmmc memory write client */ 192#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 193/* sdmmcd memory write client */ 194#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 195#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c 196#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d 197/* VI Write client */ 198#define TEGRA194_MEMORY_CLIENT_VIW 0x72 199#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 200#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 201/* Audio Processing (APE) engine read clients */ 202#define TEGRA194_MEMORY_CLIENT_APER 0x7a 203/* Audio Processing (APE) engine write clients */ 204#define TEGRA194_MEMORY_CLIENT_APEW 0x7b 205#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e 206#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f 207/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ 208#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 209/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ 210#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 211/* ETR read clients */ 212#define TEGRA194_MEMORY_CLIENT_ETRR 0x84 213/* ETR write clients */ 214#define TEGRA194_MEMORY_CLIENT_ETRW 0x85 215/* AXI Switch read client */ 216#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c 217/* AXI Switch write client */ 218#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d 219/* EQOS read client */ 220#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e 221/* EQOS write client */ 222#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f 223/* UFSHC read client */ 224#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 225/* UFSHC write client */ 226#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 227/* NVDISPLAY read client */ 228#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 229/* BPMP read client */ 230#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 231/* BPMP write client */ 232#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 233/* BPMPDMA read client */ 234#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 235/* BPMPDMA write client */ 236#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 237/* AON read client */ 238#define TEGRA194_MEMORY_CLIENT_AONR 0x97 239/* AON write client */ 240#define TEGRA194_MEMORY_CLIENT_AONW 0x98 241/* AONDMA read client */ 242#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 243/* AONDMA write client */ 244#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a 245/* SCE read client */ 246#define TEGRA194_MEMORY_CLIENT_SCER 0x9b 247/* SCE write client */ 248#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c 249/* SCEDMA read client */ 250#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d 251/* SCEDMA write client */ 252#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e 253/* APEDMA read client */ 254#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f 255/* APEDMA write client */ 256#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 257/* NVDISPLAY read client instance 2 */ 258#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 259#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 260#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 261/* MSS internal memqual MIU0 read clients */ 262#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 263/* MSS internal memqual MIU0 write clients */ 264#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 265/* MSS internal memqual MIU1 read clients */ 266#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 267/* MSS internal memqual MIU1 write clients */ 268#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 269/* MSS internal memqual MIU2 read clients */ 270#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae 271/* MSS internal memqual MIU2 write clients */ 272#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf 273/* MSS internal memqual MIU3 read clients */ 274#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 275/* MSS internal memqual MIU3 write clients */ 276#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 277/* MSS internal memqual MIU4 read clients */ 278#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 279/* MSS internal memqual MIU4 write clients */ 280#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 281#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 282#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 283#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 284#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 285#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 286#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 287#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba 288#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb 289/* VI FLACON read clients */ 290#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc 291/* VIFAL write clients */ 292#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd 293/* DLA0ARDA read clients */ 294#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe 295/* DLA0 Falcon read clients */ 296#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf 297/* DLA0 write clients */ 298#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 299/* DLA0 write clients */ 300#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 301/* DLA1ARDA read clients */ 302#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 303/* DLA1 Falcon read clients */ 304#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 305/* DLA1 write clients */ 306#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 307/* DLA1 write clients */ 308#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 309/* PVA0RDA read clients */ 310#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 311/* PVA0RDB read clients */ 312#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 313/* PVA0RDC read clients */ 314#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 315/* PVA0WRA write clients */ 316#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 317/* PVA0WRB write clients */ 318#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca 319/* PVA0WRC write clients */ 320#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb 321/* PVA1RDA read clients */ 322#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc 323/* PVA1RDB read clients */ 324#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd 325/* PVA1RDC read clients */ 326#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce 327/* PVA1WRA write clients */ 328#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf 329/* PVA1WRB write clients */ 330#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 331/* PVA1WRC write clients */ 332#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 333/* RCE read client */ 334#define TEGRA194_MEMORY_CLIENT_RCER 0xd2 335/* RCE write client */ 336#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 337/* RCEDMA read client */ 338#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 339/* RCEDMA write client */ 340#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 341#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 342#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 343/* PCIE0 read clients */ 344#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 345/* PCIE0 write clients */ 346#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 347/* PCIE1 read clients */ 348#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda 349/* PCIE1 write clients */ 350#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb 351/* PCIE2 read clients */ 352#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc 353/* PCIE2 write clients */ 354#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd 355/* PCIE3 read clients */ 356#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde 357/* PCIE3 write clients */ 358#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf 359/* PCIE4 read clients */ 360#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 361/* PCIE4 write clients */ 362#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 363/* PCIE5 read clients */ 364#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 365/* PCIE5 write clients */ 366#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 367/* ISP read client 1 for Crossbar A */ 368#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 369#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 370#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 371#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 372#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 373/* DLA0ARDA1 read clients */ 374#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 375/* DLA1ARDA1 read clients */ 376#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea 377/* PVA0RDA1 read clients */ 378#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb 379/* PVA0RDB1 read clients */ 380#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec 381/* PVA1RDA1 read clients */ 382#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed 383/* PVA1RDB1 read clients */ 384#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee 385/* PCIE5r1 read clients */ 386#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef 387#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 388#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 389/* ISP read client for Crossbar A */ 390#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 391/* PCIE0 read clients */ 392#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 393#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 394#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 395#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 396#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 397#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 398#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 399#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa 400#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb 401/* MSS internal memqual MIU5 read clients */ 402#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc 403/* MSS internal memqual MIU5 write clients */ 404#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd 405/* MSS internal memqual MIU6 read clients */ 406#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe 407/* MSS internal memqual MIU6 write clients */ 408#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff 409 410#endif 411