1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2/* 3 * Unisoc UMS512 SoC DTS file 4 * 5 * Copyright (C) 2022, Unisoc Inc. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_UMS512_H_ 9#define _DT_BINDINGS_CLK_UMS512_H_ 10 11#define CLK_26M_AUD 0 12#define CLK_13M 1 13#define CLK_6M5 2 14#define CLK_4M3 3 15#define CLK_2M 4 16#define CLK_1M 5 17#define CLK_250K 6 18#define CLK_RCO_25M 7 19#define CLK_RCO_4M 8 20#define CLK_RCO_2M 9 21#define CLK_ISPPLL_GATE 10 22#define CLK_DPLL0_GATE 11 23#define CLK_DPLL1_GATE 12 24#define CLK_LPLL_GATE 13 25#define CLK_TWPLL_GATE 14 26#define CLK_GPLL_GATE 15 27#define CLK_RPLL_GATE 16 28#define CLK_CPPLL_GATE 17 29#define CLK_MPLL0_GATE 18 30#define CLK_MPLL1_GATE 19 31#define CLK_MPLL2_GATE 20 32#define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1) 33 34#define CLK_DPLL0 0 35#define CLK_DPLL0_58M31 1 36#define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1) 37 38#define CLK_MPLL1 0 39#define CLK_MPLL1_63M38 1 40#define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1) 41 42#define CLK_RPLL 0 43#define CLK_AUDIO_GATE 1 44#define CLK_MPLL0 2 45#define CLK_MPLL0_56M88 3 46#define CLK_MPLL2 4 47#define CLK_MPLL2_47M13 5 48#define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1) 49 50#define CLK_TWPLL 0 51#define CLK_TWPLL_768M 1 52#define CLK_TWPLL_384M 2 53#define CLK_TWPLL_192M 3 54#define CLK_TWPLL_96M 4 55#define CLK_TWPLL_48M 5 56#define CLK_TWPLL_24M 6 57#define CLK_TWPLL_12M 7 58#define CLK_TWPLL_512M 8 59#define CLK_TWPLL_256M 9 60#define CLK_TWPLL_128M 10 61#define CLK_TWPLL_64M 11 62#define CLK_TWPLL_307M2 12 63#define CLK_TWPLL_219M4 13 64#define CLK_TWPLL_170M6 14 65#define CLK_TWPLL_153M6 15 66#define CLK_TWPLL_76M8 16 67#define CLK_TWPLL_51M2 17 68#define CLK_TWPLL_38M4 18 69#define CLK_TWPLL_19M2 19 70#define CLK_TWPLL_12M29 20 71#define CLK_LPLL 21 72#define CLK_LPLL_614M4 22 73#define CLK_LPLL_409M6 23 74#define CLK_LPLL_245M76 24 75#define CLK_LPLL_30M72 25 76#define CLK_ISPPLL 26 77#define CLK_ISPPLL_468M 27 78#define CLK_ISPPLL_78M 28 79#define CLK_GPLL 29 80#define CLK_GPLL_40M 30 81#define CLK_CPPLL 31 82#define CLK_CPPLL_39M32 32 83#define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1) 84 85#define CLK_AP_APB 0 86#define CLK_IPI 1 87#define CLK_AP_UART0 2 88#define CLK_AP_UART1 3 89#define CLK_AP_UART2 4 90#define CLK_AP_I2C0 5 91#define CLK_AP_I2C1 6 92#define CLK_AP_I2C2 7 93#define CLK_AP_I2C3 8 94#define CLK_AP_I2C4 9 95#define CLK_AP_SPI0 10 96#define CLK_AP_SPI1 11 97#define CLK_AP_SPI2 12 98#define CLK_AP_SPI3 13 99#define CLK_AP_IIS0 14 100#define CLK_AP_IIS1 15 101#define CLK_AP_IIS2 16 102#define CLK_AP_SIM 17 103#define CLK_AP_CE 18 104#define CLK_SDIO0_2X 19 105#define CLK_SDIO1_2X 20 106#define CLK_EMMC_2X 21 107#define CLK_VSP 22 108#define CLK_DISPC0 23 109#define CLK_DISPC0_DPI 24 110#define CLK_DSI_APB 25 111#define CLK_DSI_RXESC 26 112#define CLK_DSI_LANEBYTE 27 113#define CLK_VDSP 28 114#define CLK_VDSP_M 29 115#define CLK_AP_CLK_NUM (CLK_VDSP_M + 1) 116 117#define CLK_DSI_EB 0 118#define CLK_DISPC_EB 1 119#define CLK_VSP_EB 2 120#define CLK_VDMA_EB 3 121#define CLK_DMA_PUB_EB 4 122#define CLK_DMA_SEC_EB 5 123#define CLK_IPI_EB 6 124#define CLK_AHB_CKG_EB 7 125#define CLK_BM_CLK_EB 8 126#define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1) 127 128#define CLK_AON_APB 0 129#define CLK_ADI 1 130#define CLK_AUX0 2 131#define CLK_AUX1 3 132#define CLK_AUX2 4 133#define CLK_PROBE 5 134#define CLK_PWM0 6 135#define CLK_PWM1 7 136#define CLK_PWM2 8 137#define CLK_PWM3 9 138#define CLK_EFUSE 10 139#define CLK_UART0 11 140#define CLK_UART1 12 141#define CLK_THM0 13 142#define CLK_THM1 14 143#define CLK_THM2 15 144#define CLK_THM3 16 145#define CLK_AON_I2C 17 146#define CLK_AON_IIS 18 147#define CLK_SCC 19 148#define CLK_APCPU_DAP 20 149#define CLK_APCPU_DAP_MTCK 21 150#define CLK_APCPU_TS 22 151#define CLK_DEBUG_TS 23 152#define CLK_DSI_TEST_S 24 153#define CLK_DJTAG_TCK 25 154#define CLK_DJTAG_TCK_HW 26 155#define CLK_AON_TMR 27 156#define CLK_AON_PMU 28 157#define CLK_DEBOUNCE 29 158#define CLK_APCPU_PMU 30 159#define CLK_TOP_DVFS 31 160#define CLK_OTG_UTMI 32 161#define CLK_OTG_REF 33 162#define CLK_CSSYS 34 163#define CLK_CSSYS_PUB 35 164#define CLK_CSSYS_APB 36 165#define CLK_AP_AXI 37 166#define CLK_AP_MM 38 167#define CLK_SDIO2_2X 39 168#define CLK_ANALOG_IO_APB 40 169#define CLK_DMC_REF_CLK 41 170#define CLK_EMC 42 171#define CLK_USB 43 172#define CLK_26M_PMU 44 173#define CLK_AON_APB_NUM (CLK_26M_PMU + 1) 174 175#define CLK_MM_AHB 0 176#define CLK_MM_MTX 1 177#define CLK_SENSOR0 2 178#define CLK_SENSOR1 3 179#define CLK_SENSOR2 4 180#define CLK_CPP 5 181#define CLK_JPG 6 182#define CLK_FD 7 183#define CLK_DCAM_IF 8 184#define CLK_DCAM_AXI 9 185#define CLK_ISP 10 186#define CLK_MIPI_CSI0 11 187#define CLK_MIPI_CSI1 12 188#define CLK_MIPI_CSI2 13 189#define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1) 190 191#define CLK_RC100M_CAL_EB 0 192#define CLK_DJTAG_TCK_EB 1 193#define CLK_DJTAG_EB 2 194#define CLK_AUX0_EB 3 195#define CLK_AUX1_EB 4 196#define CLK_AUX2_EB 5 197#define CLK_PROBE_EB 6 198#define CLK_MM_EB 7 199#define CLK_GPU_EB 8 200#define CLK_MSPI_EB 9 201#define CLK_APCPU_DAP_EB 10 202#define CLK_AON_CSSYS_EB 11 203#define CLK_CSSYS_APB_EB 12 204#define CLK_CSSYS_PUB_EB 13 205#define CLK_SDPHY_CFG_EB 14 206#define CLK_SDPHY_REF_EB 15 207#define CLK_EFUSE_EB 16 208#define CLK_GPIO_EB 17 209#define CLK_MBOX_EB 18 210#define CLK_KPD_EB 19 211#define CLK_AON_SYST_EB 20 212#define CLK_AP_SYST_EB 21 213#define CLK_AON_TMR_EB 22 214#define CLK_OTG_UTMI_EB 23 215#define CLK_OTG_PHY_EB 24 216#define CLK_SPLK_EB 25 217#define CLK_PIN_EB 26 218#define CLK_ANA_EB 27 219#define CLK_APCPU_TS0_EB 28 220#define CLK_APB_BUSMON_EB 29 221#define CLK_AON_IIS_EB 30 222#define CLK_SCC_EB 31 223#define CLK_THM0_EB 32 224#define CLK_THM1_EB 33 225#define CLK_THM2_EB 34 226#define CLK_ASIM_TOP_EB 35 227#define CLK_I2C_EB 36 228#define CLK_PMU_EB 37 229#define CLK_ADI_EB 38 230#define CLK_EIC_EB 39 231#define CLK_AP_INTC0_EB 40 232#define CLK_AP_INTC1_EB 41 233#define CLK_AP_INTC2_EB 42 234#define CLK_AP_INTC3_EB 43 235#define CLK_AP_INTC4_EB 44 236#define CLK_AP_INTC5_EB 45 237#define CLK_AUDCP_INTC_EB 46 238#define CLK_AP_TMR0_EB 47 239#define CLK_AP_TMR1_EB 48 240#define CLK_AP_TMR2_EB 49 241#define CLK_PWM0_EB 50 242#define CLK_PWM1_EB 51 243#define CLK_PWM2_EB 52 244#define CLK_PWM3_EB 53 245#define CLK_AP_WDG_EB 54 246#define CLK_APCPU_WDG_EB 55 247#define CLK_SERDES_EB 56 248#define CLK_ARCH_RTC_EB 57 249#define CLK_KPD_RTC_EB 58 250#define CLK_AON_SYST_RTC_EB 59 251#define CLK_AP_SYST_RTC_EB 60 252#define CLK_AON_TMR_RTC_EB 61 253#define CLK_EIC_RTC_EB 62 254#define CLK_EIC_RTCDV5_EB 63 255#define CLK_AP_WDG_RTC_EB 64 256#define CLK_AC_WDG_RTC_EB 65 257#define CLK_AP_TMR0_RTC_EB 66 258#define CLK_AP_TMR1_RTC_EB 67 259#define CLK_AP_TMR2_RTC_EB 68 260#define CLK_DCXO_LC_RTC_EB 69 261#define CLK_BB_CAL_RTC_EB 70 262#define CLK_AP_EMMC_RTC_EB 71 263#define CLK_AP_SDIO0_RTC_EB 72 264#define CLK_AP_SDIO1_RTC_EB 73 265#define CLK_AP_SDIO2_RTC_EB 74 266#define CLK_DSI_CSI_TEST_EB 75 267#define CLK_DJTAG_TCK_EN 76 268#define CLK_DPHY_REF_EB 77 269#define CLK_DMC_REF_EB 78 270#define CLK_OTG_REF_EB 79 271#define CLK_TSEN_EB 80 272#define CLK_TMR_EB 81 273#define CLK_RC100M_REF_EB 82 274#define CLK_RC100M_FDK_EB 83 275#define CLK_DEBOUNCE_EB 84 276#define CLK_DET_32K_EB 85 277#define CLK_TOP_CSSYS_EB 86 278#define CLK_AP_AXI_EN 87 279#define CLK_SDIO0_2X_EN 88 280#define CLK_SDIO0_1X_EN 89 281#define CLK_SDIO1_2X_EN 90 282#define CLK_SDIO1_1X_EN 91 283#define CLK_SDIO2_2X_EN 92 284#define CLK_SDIO2_1X_EN 93 285#define CLK_EMMC_2X_EN 94 286#define CLK_EMMC_1X_EN 95 287#define CLK_PLL_TEST_EN 96 288#define CLK_CPHY_CFG_EN 97 289#define CLK_DEBUG_TS_EN 98 290#define CLK_ACCESS_AUD_EN 99 291#define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1) 292 293#define CLK_MM_CPP_EB 0 294#define CLK_MM_JPG_EB 1 295#define CLK_MM_DCAM_EB 2 296#define CLK_MM_ISP_EB 3 297#define CLK_MM_CSI2_EB 4 298#define CLK_MM_CSI1_EB 5 299#define CLK_MM_CSI0_EB 6 300#define CLK_MM_CKG_EB 7 301#define CLK_ISP_AHB_EB 8 302#define CLK_MM_DVFS_EB 9 303#define CLK_MM_FD_EB 10 304#define CLK_MM_SENSOR2_EB 11 305#define CLK_MM_SENSOR1_EB 12 306#define CLK_MM_SENSOR0_EB 13 307#define CLK_MM_MIPI_CSI2_EB 14 308#define CLK_MM_MIPI_CSI1_EB 15 309#define CLK_MM_MIPI_CSI0_EB 16 310#define CLK_DCAM_AXI_EB 17 311#define CLK_ISP_AXI_EB 18 312#define CLK_MM_CPHY_EB 19 313#define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1) 314 315#define CLK_SIM0_EB 0 316#define CLK_IIS0_EB 1 317#define CLK_IIS1_EB 2 318#define CLK_IIS2_EB 3 319#define CLK_APB_REG_EB 4 320#define CLK_SPI0_EB 5 321#define CLK_SPI1_EB 6 322#define CLK_SPI2_EB 7 323#define CLK_SPI3_EB 8 324#define CLK_I2C0_EB 9 325#define CLK_I2C1_EB 10 326#define CLK_I2C2_EB 11 327#define CLK_I2C3_EB 12 328#define CLK_I2C4_EB 13 329#define CLK_UART0_EB 14 330#define CLK_UART1_EB 15 331#define CLK_UART2_EB 16 332#define CLK_SIM0_32K_EB 17 333#define CLK_SPI0_LFIN_EB 18 334#define CLK_SPI1_LFIN_EB 19 335#define CLK_SPI2_LFIN_EB 20 336#define CLK_SPI3_LFIN_EB 21 337#define CLK_SDIO0_EB 22 338#define CLK_SDIO1_EB 23 339#define CLK_SDIO2_EB 24 340#define CLK_EMMC_EB 25 341#define CLK_SDIO0_32K_EB 26 342#define CLK_SDIO1_32K_EB 27 343#define CLK_SDIO2_32K_EB 28 344#define CLK_EMMC_32K_EB 29 345#define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1) 346 347#define CLK_GPU_CORE_EB 0 348#define CLK_GPU_CORE 1 349#define CLK_GPU_MEM_EB 2 350#define CLK_GPU_MEM 3 351#define CLK_GPU_SYS_EB 4 352#define CLK_GPU_SYS 5 353#define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1) 354 355#define CLK_AUDCP_IIS0_EB 0 356#define CLK_AUDCP_IIS1_EB 1 357#define CLK_AUDCP_IIS2_EB 2 358#define CLK_AUDCP_UART_EB 3 359#define CLK_AUDCP_DMA_CP_EB 4 360#define CLK_AUDCP_DMA_AP_EB 5 361#define CLK_AUDCP_SRC48K_EB 6 362#define CLK_AUDCP_MCDT_EB 7 363#define CLK_AUDCP_VBCIFD_EB 8 364#define CLK_AUDCP_VBC_EB 9 365#define CLK_AUDCP_SPLK_EB 10 366#define CLK_AUDCP_ICU_EB 11 367#define CLK_AUDCP_DMA_AP_ASHB_EB 12 368#define CLK_AUDCP_DMA_CP_ASHB_EB 13 369#define CLK_AUDCP_AUD_EB 14 370#define CLK_AUDCP_VBC_24M_EB 15 371#define CLK_AUDCP_TMR_26M_EB 16 372#define CLK_AUDCP_DVFS_ASHB_EB 17 373#define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1) 374 375#define CLK_AUDCP_WDG_EB 0 376#define CLK_AUDCP_RTC_WDG_EB 1 377#define CLK_AUDCP_TMR0_EB 2 378#define CLK_AUDCP_TMR1_EB 3 379#define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1) 380 381#define CLK_ACORE0 0 382#define CLK_ACORE1 1 383#define CLK_ACORE2 2 384#define CLK_ACORE3 3 385#define CLK_ACORE4 4 386#define CLK_ACORE5 5 387#define CLK_PCORE0 6 388#define CLK_PCORE1 7 389#define CLK_SCU 8 390#define CLK_ACE 9 391#define CLK_PERIPH 10 392#define CLK_GIC 11 393#define CLK_ATB 12 394#define CLK_DEBUG_APB 13 395#define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1) 396 397#endif /* _DT_BINDINGS_CLK_UMS512_H_ */ 398