1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 * 3 * Copyright (C) 2022 Renesas Electronics Corp. 4 */ 5#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ 6#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ 7 8#include <dt-bindings/clock/renesas-cpg-mssr.h> 9 10/* R9A07G043 CPG Core Clocks */ 11#define R9A07G043_CLK_I 0 12#define R9A07G043_CLK_I2 1 13#define R9A07G043_CLK_S0 2 14#define R9A07G043_CLK_SPI0 3 15#define R9A07G043_CLK_SPI1 4 16#define R9A07G043_CLK_SD0 5 17#define R9A07G043_CLK_SD1 6 18#define R9A07G043_CLK_M0 7 19#define R9A07G043_CLK_M2 8 /* RZ/G2UL Only */ 20#define R9A07G043_CLK_M3 9 /* RZ/G2UL Only */ 21#define R9A07G043_CLK_HP 10 22#define R9A07G043_CLK_TSU 11 23#define R9A07G043_CLK_ZT 12 24#define R9A07G043_CLK_P0 13 25#define R9A07G043_CLK_P1 14 26#define R9A07G043_CLK_P2 15 27#define R9A07G043_CLK_AT 16 /* RZ/G2UL Only */ 28#define R9A07G043_OSCCLK 17 29#define R9A07G043_CLK_P0_DIV2 18 30 31/* R9A07G043 Module Clocks */ 32#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */ 33#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */ 34#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */ 35#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */ 36#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */ 37#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */ 38#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */ 39#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */ 40#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */ 41#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */ 42#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */ 43#define R9A07G043_SYC_CNT_CLK 11 44#define R9A07G043_DMAC_ACLK 12 45#define R9A07G043_DMAC_PCLK 13 46#define R9A07G043_OSTM0_PCLK 14 47#define R9A07G043_OSTM1_PCLK 15 48#define R9A07G043_OSTM2_PCLK 16 49#define R9A07G043_MTU_X_MCK_MTU3 17 50#define R9A07G043_POE3_CLKM_POE 18 51#define R9A07G043_WDT0_PCLK 19 52#define R9A07G043_WDT0_CLK 20 53#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */ 54#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */ 55#define R9A07G043_SPI_CLK2 23 56#define R9A07G043_SPI_CLK 24 57#define R9A07G043_SDHI0_IMCLK 25 58#define R9A07G043_SDHI0_IMCLK2 26 59#define R9A07G043_SDHI0_CLK_HS 27 60#define R9A07G043_SDHI0_ACLK 28 61#define R9A07G043_SDHI1_IMCLK 29 62#define R9A07G043_SDHI1_IMCLK2 30 63#define R9A07G043_SDHI1_CLK_HS 31 64#define R9A07G043_SDHI1_ACLK 32 65#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */ 66#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */ 67#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */ 68#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */ 69#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */ 70#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */ 71#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */ 72#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */ 73#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */ 74#define R9A07G043_SSI0_PCLK2 42 75#define R9A07G043_SSI0_PCLK_SFR 43 76#define R9A07G043_SSI1_PCLK2 44 77#define R9A07G043_SSI1_PCLK_SFR 45 78#define R9A07G043_SSI2_PCLK2 46 79#define R9A07G043_SSI2_PCLK_SFR 47 80#define R9A07G043_SSI3_PCLK2 48 81#define R9A07G043_SSI3_PCLK_SFR 49 82#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */ 83#define R9A07G043_USB_U2H0_HCLK 51 84#define R9A07G043_USB_U2H1_HCLK 52 85#define R9A07G043_USB_U2P_EXR_CPUCLK 53 86#define R9A07G043_USB_PCLK 54 87#define R9A07G043_ETH0_CLK_AXI 55 88#define R9A07G043_ETH0_CLK_CHI 56 89#define R9A07G043_ETH1_CLK_AXI 57 90#define R9A07G043_ETH1_CLK_CHI 58 91#define R9A07G043_I2C0_PCLK 59 92#define R9A07G043_I2C1_PCLK 60 93#define R9A07G043_I2C2_PCLK 61 94#define R9A07G043_I2C3_PCLK 62 95#define R9A07G043_SCIF0_CLK_PCK 63 96#define R9A07G043_SCIF1_CLK_PCK 64 97#define R9A07G043_SCIF2_CLK_PCK 65 98#define R9A07G043_SCIF3_CLK_PCK 66 99#define R9A07G043_SCIF4_CLK_PCK 67 100#define R9A07G043_SCI0_CLKP 68 101#define R9A07G043_SCI1_CLKP 69 102#define R9A07G043_IRDA_CLKP 70 103#define R9A07G043_RSPI0_CLKB 71 104#define R9A07G043_RSPI1_CLKB 72 105#define R9A07G043_RSPI2_CLKB 73 106#define R9A07G043_CANFD_PCLK 74 107#define R9A07G043_GPIO_HCLK 75 108#define R9A07G043_ADC_ADCLK 76 109#define R9A07G043_ADC_PCLK 77 110#define R9A07G043_TSU_PCLK 78 111#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ 112#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ 113#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ 114#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */ 115#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */ 116#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */ 117#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */ 118#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */ 119#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */ 120 121/* R9A07G043 Resets */ 122#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ 123#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */ 124#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */ 125#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */ 126#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */ 127#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */ 128#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */ 129#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */ 130#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */ 131#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */ 132#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */ 133#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */ 134#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */ 135#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */ 136#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */ 137#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */ 138#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */ 139#define R9A07G043_DMAC_ARESETN 17 140#define R9A07G043_DMAC_RST_ASYNC 18 141#define R9A07G043_SYC_RESETN 19 142#define R9A07G043_OSTM0_PRESETZ 20 143#define R9A07G043_OSTM1_PRESETZ 21 144#define R9A07G043_OSTM2_PRESETZ 22 145#define R9A07G043_MTU_X_PRESET_MTU3 23 146#define R9A07G043_POE3_RST_M_REG 24 147#define R9A07G043_WDT0_PRESETN 25 148#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */ 149#define R9A07G043_SPI_RST 27 150#define R9A07G043_SDHI0_IXRST 28 151#define R9A07G043_SDHI1_IXRST 29 152#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */ 153#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */ 154#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */ 155#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */ 156#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */ 157#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */ 158#define R9A07G043_SSI0_RST_M2_REG 36 159#define R9A07G043_SSI1_RST_M2_REG 37 160#define R9A07G043_SSI2_RST_M2_REG 38 161#define R9A07G043_SSI3_RST_M2_REG 39 162#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */ 163#define R9A07G043_USB_U2H0_HRESETN 41 164#define R9A07G043_USB_U2H1_HRESETN 42 165#define R9A07G043_USB_U2P_EXL_SYSRST 43 166#define R9A07G043_USB_PRESETN 44 167#define R9A07G043_ETH0_RST_HW_N 45 168#define R9A07G043_ETH1_RST_HW_N 46 169#define R9A07G043_I2C0_MRST 47 170#define R9A07G043_I2C1_MRST 48 171#define R9A07G043_I2C2_MRST 49 172#define R9A07G043_I2C3_MRST 50 173#define R9A07G043_SCIF0_RST_SYSTEM_N 51 174#define R9A07G043_SCIF1_RST_SYSTEM_N 52 175#define R9A07G043_SCIF2_RST_SYSTEM_N 53 176#define R9A07G043_SCIF3_RST_SYSTEM_N 54 177#define R9A07G043_SCIF4_RST_SYSTEM_N 55 178#define R9A07G043_SCI0_RST 56 179#define R9A07G043_SCI1_RST 57 180#define R9A07G043_IRDA_RST 58 181#define R9A07G043_RSPI0_RST 59 182#define R9A07G043_RSPI1_RST 60 183#define R9A07G043_RSPI2_RST 61 184#define R9A07G043_CANFD_RSTP_N 62 185#define R9A07G043_CANFD_RSTC_N 63 186#define R9A07G043_GPIO_RSTN 64 187#define R9A07G043_GPIO_PORT_RESETN 65 188#define R9A07G043_GPIO_SPARE_RESETN 66 189#define R9A07G043_ADC_PRESETN 67 190#define R9A07G043_ADC_ADRST_N 68 191#define R9A07G043_TSU_PRESETN 69 192#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */ 193#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */ 194#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */ 195#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */ 196#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */ 197#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */ 198#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */ 199#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */ 200#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ 201#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ 202 203/* Power domain IDs. */ 204#define R9A07G043_PD_ALWAYS_ON 0 205#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */ 206#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */ 207#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */ 208#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */ 209#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */ 210#define R9A07G043_PD_DMAC 6 211#define R9A07G043_PD_GTM0 7 212#define R9A07G043_PD_GTM1 8 213#define R9A07G043_PD_GTM2 9 214#define R9A07G043_PD_MTU 10 215#define R9A07G043_PD_POE3 11 216#define R9A07G043_PD_WDT0 12 217#define R9A07G043_PD_SPI 13 218#define R9A07G043_PD_SDHI0 14 219#define R9A07G043_PD_SDHI1 15 220#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */ 221#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */ 222#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */ 223#define R9A07G043_PD_SSI0 19 224#define R9A07G043_PD_SSI1 20 225#define R9A07G043_PD_SSI2 21 226#define R9A07G043_PD_SSI3 22 227#define R9A07G043_PD_SRC 23 228#define R9A07G043_PD_USB0 24 229#define R9A07G043_PD_USB1 25 230#define R9A07G043_PD_USB_PHY 26 231#define R9A07G043_PD_ETHER0 27 232#define R9A07G043_PD_ETHER1 28 233#define R9A07G043_PD_I2C0 29 234#define R9A07G043_PD_I2C1 30 235#define R9A07G043_PD_I2C2 31 236#define R9A07G043_PD_I2C3 32 237#define R9A07G043_PD_SCIF0 33 238#define R9A07G043_PD_SCIF1 34 239#define R9A07G043_PD_SCIF2 35 240#define R9A07G043_PD_SCIF3 36 241#define R9A07G043_PD_SCIF4 37 242#define R9A07G043_PD_SCI0 38 243#define R9A07G043_PD_SCI1 39 244#define R9A07G043_PD_IRDA 40 245#define R9A07G043_PD_RSPI0 41 246#define R9A07G043_PD_RSPI1 42 247#define R9A07G043_PD_RSPI2 43 248#define R9A07G043_PD_CANFD 44 249#define R9A07G043_PD_ADC 45 250#define R9A07G043_PD_TSU 46 251#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */ 252#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */ 253#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */ 254#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */ 255 256#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ 257