111894Speter/* SPDX-License-Identifier: GPL-2.0 */ 211894Speter/* 39Sjkh * Copyright (c) 2018, The Linux Foundation. All rights reserved. 49Sjkh */ 59Sjkh 69Sjkh#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H 79Sjkh#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H 89Sjkh 911894Speter/* GCC clock registers */ 1011894Speter#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 119Sjkh#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 129Sjkh#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 139Sjkh#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 149Sjkh#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 159Sjkh#define GCC_BOOT_ROM_AHB_CLK 5 169Sjkh#define GCC_CAMERA_AHB_CLK 6 179Sjkh#define GCC_CAMERA_AXI_CLK 7 189Sjkh#define GCC_CAMERA_XO_CLK 8 199Sjkh#define GCC_CE1_AHB_CLK 9 209Sjkh#define GCC_CE1_AXI_CLK 10 219Sjkh#define GCC_CE1_CLK 11 229Sjkh#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 239Sjkh#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 249Sjkh#define GCC_CPUSS_AHB_CLK 14 259Sjkh#define GCC_CPUSS_AHB_CLK_SRC 15 2611894Speter#define GCC_CPUSS_RBCPR_CLK 16 2711894Speter#define GCC_CPUSS_RBCPR_CLK_SRC 17 2811894Speter#define GCC_DDRSS_GPU_AXI_CLK 18 299Sjkh#define GCC_DISP_AHB_CLK 19 309Sjkh#define GCC_DISP_AXI_CLK 20 319Sjkh#define GCC_DISP_GPLL0_CLK_SRC 21 329Sjkh#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 339Sjkh#define GCC_DISP_XO_CLK 23 349Sjkh#define GCC_GP1_CLK 24 359Sjkh#define GCC_GP1_CLK_SRC 25 369Sjkh#define GCC_GP2_CLK 26 379Sjkh#define GCC_GP2_CLK_SRC 27 389Sjkh#define GCC_GP3_CLK 28 399Sjkh#define GCC_GP3_CLK_SRC 29 4011894Speter#define GCC_GPU_CFG_AHB_CLK 30 4111894Speter#define GCC_GPU_GPLL0_CLK_SRC 31 4211894Speter#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 4311894Speter#define GCC_GPU_MEMNOC_GFX_CLK 33 448858Srgrimes#define GCC_GPU_SNOC_DVM_GFX_CLK 34 4511894Speter#define GCC_MSS_AXIS2_CLK 35 4611894Speter#define GCC_MSS_CFG_AHB_CLK 36 4711894Speter#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 4811894Speter#define GCC_MSS_MFAB_AXIS_CLK 38 4911894Speter#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 5011894Speter#define GCC_MSS_SNOC_AXI_CLK 40 5111894Speter#define GCC_PCIE_0_AUX_CLK 41 5211894Speter#define GCC_PCIE_0_AUX_CLK_SRC 42 5311894Speter#define GCC_PCIE_0_CFG_AHB_CLK 43 5411894Speter#define GCC_PCIE_0_CLKREF_CLK 44 5511894Speter#define GCC_PCIE_0_MSTR_AXI_CLK 45 5611894Speter#define GCC_PCIE_0_PIPE_CLK 46 5711894Speter#define GCC_PCIE_0_SLV_AXI_CLK 47 5811894Speter#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 599Sjkh#define GCC_PCIE_1_AUX_CLK 49 609Sjkh#define GCC_PCIE_1_AUX_CLK_SRC 50 619Sjkh#define GCC_PCIE_1_CFG_AHB_CLK 51 629Sjkh#define GCC_PCIE_1_CLKREF_CLK 52 639Sjkh#define GCC_PCIE_1_MSTR_AXI_CLK 53 649Sjkh#define GCC_PCIE_1_PIPE_CLK 54 659Sjkh#define GCC_PCIE_1_SLV_AXI_CLK 55 669Sjkh#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 679Sjkh#define GCC_PCIE_PHY_AUX_CLK 57 689Sjkh#define GCC_PCIE_PHY_REFGEN_CLK 58 699Sjkh#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 709Sjkh#define GCC_PDM2_CLK 60 719Sjkh#define GCC_PDM2_CLK_SRC 61 729Sjkh#define GCC_PDM_AHB_CLK 62 739Sjkh#define GCC_PDM_XO4_CLK 63 749Sjkh#define GCC_PRNG_AHB_CLK 64 759Sjkh#define GCC_QMIP_CAMERA_AHB_CLK 65 769Sjkh#define GCC_QMIP_DISP_AHB_CLK 66 779Sjkh#define GCC_QMIP_VIDEO_AHB_CLK 67 789Sjkh#define GCC_QUPV3_WRAP0_S0_CLK 68 799Sjkh#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 809Sjkh#define GCC_QUPV3_WRAP0_S1_CLK 70 819Sjkh#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 829Sjkh#define GCC_QUPV3_WRAP0_S2_CLK 72 839Sjkh#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 849Sjkh#define GCC_QUPV3_WRAP0_S3_CLK 74 859Sjkh#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 869Sjkh#define GCC_QUPV3_WRAP0_S4_CLK 76 879Sjkh#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 889Sjkh#define GCC_QUPV3_WRAP0_S5_CLK 78 899Sjkh#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 908858Srgrimes#define GCC_QUPV3_WRAP0_S6_CLK 80 919Sjkh#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 929Sjkh#define GCC_QUPV3_WRAP0_S7_CLK 82 938858Srgrimes#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 949Sjkh#define GCC_QUPV3_WRAP1_S0_CLK 84 959Sjkh#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 968858Srgrimes#define GCC_QUPV3_WRAP1_S1_CLK 86 979Sjkh#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 988858Srgrimes#define GCC_QUPV3_WRAP1_S2_CLK 88 999Sjkh#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 1008858Srgrimes#define GCC_QUPV3_WRAP1_S3_CLK 90 1019Sjkh#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 1029Sjkh#define GCC_QUPV3_WRAP1_S4_CLK 92 1038858Srgrimes#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 1049Sjkh#define GCC_QUPV3_WRAP1_S5_CLK 94 1059Sjkh#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 1069Sjkh#define GCC_QUPV3_WRAP1_S6_CLK 96 1078858Srgrimes#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 1089Sjkh#define GCC_QUPV3_WRAP1_S7_CLK 98 1099Sjkh#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 1109Sjkh#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 1119Sjkh#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 1129Sjkh#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 1139Sjkh#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 1149Sjkh#define GCC_SDCC2_AHB_CLK 104 1159Sjkh#define GCC_SDCC2_APPS_CLK 105 1169Sjkh#define GCC_SDCC2_APPS_CLK_SRC 106 1179Sjkh#define GCC_SDCC4_AHB_CLK 107 1189Sjkh#define GCC_SDCC4_APPS_CLK 108 1199Sjkh#define GCC_SDCC4_APPS_CLK_SRC 109 1209Sjkh#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 1219Sjkh#define GCC_TSIF_AHB_CLK 111 12211894Speter#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 1239Sjkh#define GCC_TSIF_REF_CLK 113 12411894Speter#define GCC_TSIF_REF_CLK_SRC 114 1259Sjkh#define GCC_UFS_CARD_AHB_CLK 115 1269Sjkh#define GCC_UFS_CARD_AXI_CLK 116 1279Sjkh#define GCC_UFS_CARD_AXI_CLK_SRC 117 1289Sjkh#define GCC_UFS_CARD_CLKREF_CLK 118 1299Sjkh#define GCC_UFS_CARD_ICE_CORE_CLK 119 1309Sjkh#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 1319Sjkh#define GCC_UFS_CARD_PHY_AUX_CLK 121 1329Sjkh#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 1339Sjkh#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 1349Sjkh#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 1359Sjkh#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 13611894Speter#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 1379Sjkh#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 1389Sjkh#define GCC_UFS_MEM_CLKREF_CLK 128 1399Sjkh#define GCC_UFS_PHY_AHB_CLK 129 1409Sjkh#define GCC_UFS_PHY_AXI_CLK 130 1419Sjkh#define GCC_UFS_PHY_AXI_CLK_SRC 131 14211894Speter#define GCC_UFS_PHY_ICE_CORE_CLK 132 1439Sjkh#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 1449Sjkh#define GCC_UFS_PHY_PHY_AUX_CLK 134 14511894Speter#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 1469Sjkh#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 14711894Speter#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 14811894Speter#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 1499Sjkh#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 1509Sjkh#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 1519Sjkh#define GCC_USB30_PRIM_MASTER_CLK 141 1529Sjkh#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 15311894Speter#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 1549Sjkh#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 1559Sjkh#define GCC_USB30_PRIM_SLEEP_CLK 145 1569Sjkh#define GCC_USB30_SEC_MASTER_CLK 146 1579Sjkh#define GCC_USB30_SEC_MASTER_CLK_SRC 147 1589Sjkh#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 1599Sjkh#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 1609Sjkh#define GCC_USB30_SEC_SLEEP_CLK 150 1619Sjkh#define GCC_USB3_PRIM_CLKREF_CLK 151 1629Sjkh#define GCC_USB3_PRIM_PHY_AUX_CLK 152 1639Sjkh#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 1649Sjkh#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 1659Sjkh#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 1669Sjkh#define GCC_USB3_SEC_CLKREF_CLK 156 16711894Speter#define GCC_USB3_SEC_PHY_AUX_CLK 157 1689Sjkh#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 1699Sjkh#define GCC_USB3_SEC_PHY_PIPE_CLK 159 1709Sjkh#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 1719Sjkh#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 17211894Speter#define GCC_VIDEO_AHB_CLK 162 17311894Speter#define GCC_VIDEO_AXI_CLK 163 1749Sjkh#define GCC_VIDEO_XO_CLK 164 1759Sjkh#define GPLL0 165 17611894Speter#define GPLL0_OUT_EVEN 166 1779Sjkh#define GPLL0_OUT_MAIN 167 17811894Speter#define GCC_GPU_IREF_CLK 168 1799Sjkh#define GCC_SDCC1_AHB_CLK 169 1809Sjkh#define GCC_SDCC1_APPS_CLK 170 1819Sjkh#define GCC_SDCC1_ICE_CORE_CLK 171 1829Sjkh#define GCC_SDCC1_APPS_CLK_SRC 172 18311894Speter#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 18411894Speter#define GCC_APC_VS_CLK 174 1859Sjkh#define GCC_GPU_VS_CLK 175 1869Sjkh#define GCC_MSS_VS_CLK 176 1879Sjkh#define GCC_VDDA_VS_CLK 177 1889Sjkh#define GCC_VDDCX_VS_CLK 178 1899Sjkh#define GCC_VDDMX_VS_CLK 179 1909Sjkh#define GCC_VS_CTRL_AHB_CLK 180 1919Sjkh#define GCC_VS_CTRL_CLK 181 1929Sjkh#define GCC_VS_CTRL_CLK_SRC 182 1939Sjkh#define GCC_VSENSOR_CLK_SRC 183 1949Sjkh#define GPLL4 184 19511894Speter#define GCC_CPUSS_DVM_BUS_CLK 185 1969Sjkh#define GCC_CPUSS_GNOC_CLK 186 1979Sjkh#define GCC_QSPI_CORE_CLK_SRC 187 1989Sjkh#define GCC_QSPI_CORE_CLK 188 1999Sjkh#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 2009Sjkh#define GCC_LPASS_Q6_AXI_CLK 190 20111894Speter#define GCC_LPASS_SWAY_CLK 191 20211894Speter#define GPLL6 192 2039Sjkh 2049Sjkh/* GCC Resets */ 2059Sjkh#define GCC_MMSS_BCR 0 2069Sjkh#define GCC_PCIE_0_BCR 1 2079Sjkh#define GCC_PCIE_1_BCR 2 2089Sjkh#define GCC_PCIE_PHY_BCR 3 20911894Speter#define GCC_PDM_BCR 4 21011894Speter#define GCC_PRNG_BCR 5 2119Sjkh#define GCC_QUPV3_WRAPPER_0_BCR 6 2129Sjkh#define GCC_QUPV3_WRAPPER_1_BCR 7 2139Sjkh#define GCC_QUSB2PHY_PRIM_BCR 8 2149Sjkh#define GCC_QUSB2PHY_SEC_BCR 9 2159Sjkh#define GCC_SDCC2_BCR 10 2169Sjkh#define GCC_SDCC4_BCR 11 2179Sjkh#define GCC_TSIF_BCR 12 2189Sjkh#define GCC_UFS_CARD_BCR 13 2199Sjkh#define GCC_UFS_PHY_BCR 14 2209Sjkh#define GCC_USB30_PRIM_BCR 15 2219Sjkh#define GCC_USB30_SEC_BCR 16 2229Sjkh#define GCC_USB3_PHY_PRIM_BCR 17 2239Sjkh#define GCC_USB3PHY_PHY_PRIM_BCR 18 2249Sjkh#define GCC_USB3_DP_PHY_PRIM_BCR 19 2259Sjkh#define GCC_USB3_PHY_SEC_BCR 20 2269Sjkh#define GCC_USB3PHY_PHY_SEC_BCR 21 2279Sjkh#define GCC_USB3_DP_PHY_SEC_BCR 22 2289Sjkh#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 2299Sjkh#define GCC_PCIE_0_PHY_BCR 24 2309Sjkh#define GCC_PCIE_1_PHY_BCR 25 2319Sjkh 2329Sjkh/* GCC GDSCRs */ 2339Sjkh#define PCIE_0_GDSC 0 2349Sjkh#define PCIE_1_GDSC 1 2359Sjkh#define UFS_CARD_GDSC 2 2369Sjkh#define UFS_PHY_GDSC 3 2379Sjkh#define USB30_PRIM_GDSC 4 2389Sjkh#define USB30_SEC_GDSC 5 2399Sjkh#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 2409Sjkh#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 2419Sjkh#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 2429Sjkh#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 2439Sjkh#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 2449Sjkh#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 24511894Speter#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 24611894Speter 2479Sjkh#endif 2489Sjkh