1254219Scy/* SPDX-License-Identifier: GPL-2.0 */ 2254219Scy/* 3254219Scy * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4254219Scy */ 5254219Scy 6254219Scy#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H 7254219Scy#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H 8254219Scy 9254219Scy#define GPLL0 0 10254219Scy#define UBI32_PLL 1 11254219Scy#define GPLL6 2 12254219Scy#define GPLL4 3 13254219Scy#define PCNOC_BFDCD_CLK_SRC 4 14254219Scy#define GPLL2 5 15254219Scy#define NSS_CRYPTO_PLL 6 16254219Scy#define NSS_PPE_CLK_SRC 7 17254219Scy#define GCC_XO_CLK_SRC 8 18254219Scy#define NSS_CE_CLK_SRC 9 19254219Scy#define GCC_SLEEP_CLK_SRC 10 20254219Scy#define APSS_AHB_CLK_SRC 11 21254219Scy#define NSS_PORT5_RX_CLK_SRC 12 22254219Scy#define NSS_PORT5_TX_CLK_SRC 13 23254219Scy#define PCIE0_AXI_CLK_SRC 14 24254219Scy#define USB0_MASTER_CLK_SRC 15 25254219Scy#define APSS_AHB_POSTDIV_CLK_SRC 16 26254219Scy#define NSS_PORT1_RX_CLK_SRC 17 27254219Scy#define NSS_PORT1_TX_CLK_SRC 18 28254219Scy#define NSS_PORT2_RX_CLK_SRC 19 29254219Scy#define NSS_PORT2_TX_CLK_SRC 20 30254219Scy#define NSS_PORT3_RX_CLK_SRC 21 31254219Scy#define NSS_PORT3_TX_CLK_SRC 22 32254219Scy#define NSS_PORT4_RX_CLK_SRC 23 33254219Scy#define NSS_PORT4_TX_CLK_SRC 24 34254219Scy#define NSS_PORT5_RX_DIV_CLK_SRC 25 35254219Scy#define NSS_PORT5_TX_DIV_CLK_SRC 26 36254219Scy#define APSS_AXI_CLK_SRC 27 37254219Scy#define NSS_CRYPTO_CLK_SRC 28 38254219Scy#define NSS_PORT1_RX_DIV_CLK_SRC 29 39254219Scy#define NSS_PORT1_TX_DIV_CLK_SRC 30 40254219Scy#define NSS_PORT2_RX_DIV_CLK_SRC 31 41254219Scy#define NSS_PORT2_TX_DIV_CLK_SRC 32 42254219Scy#define NSS_PORT3_RX_DIV_CLK_SRC 33 43254219Scy#define NSS_PORT3_TX_DIV_CLK_SRC 34 44254219Scy#define NSS_PORT4_RX_DIV_CLK_SRC 35 45254219Scy#define NSS_PORT4_TX_DIV_CLK_SRC 36 46254219Scy#define NSS_UBI0_CLK_SRC 37 47254219Scy#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38 48254219Scy#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39 49254219Scy#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40 50254219Scy#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41 51254219Scy#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42 52254219Scy#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43 53254219Scy#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44 54254219Scy#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45 55254219Scy#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46 56254219Scy#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47 57254219Scy#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48 58254219Scy#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49 59254219Scy#define BLSP1_UART1_APPS_CLK_SRC 50 60254219Scy#define BLSP1_UART2_APPS_CLK_SRC 51 61254219Scy#define BLSP1_UART3_APPS_CLK_SRC 52 62254219Scy#define BLSP1_UART4_APPS_CLK_SRC 53 63254219Scy#define BLSP1_UART5_APPS_CLK_SRC 54 64254219Scy#define BLSP1_UART6_APPS_CLK_SRC 55 65254219Scy#define CRYPTO_CLK_SRC 56 66254219Scy#define NSS_UBI0_DIV_CLK_SRC 57 67254219Scy#define PCIE0_AUX_CLK_SRC 58 68254219Scy#define PCIE0_PIPE_CLK_SRC 59 69254219Scy#define SDCC1_APPS_CLK_SRC 60 70254219Scy#define USB0_AUX_CLK_SRC 61 71254219Scy#define USB0_MOCK_UTMI_CLK_SRC 62 72254219Scy#define USB0_PIPE_CLK_SRC 63 73254219Scy#define USB1_MOCK_UTMI_CLK_SRC 64 74254219Scy#define GCC_APSS_AHB_CLK 65 75254219Scy#define GCC_APSS_AXI_CLK 66 76254219Scy#define GCC_BLSP1_AHB_CLK 67 77254219Scy#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68 78254219Scy#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69 79254219Scy#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70 80254219Scy#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71 81254219Scy#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72 82254219Scy#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73 83254219Scy#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74 84254219Scy#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75 85254219Scy#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76 86254219Scy#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77 87254219Scy#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78 88254219Scy#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79 89254219Scy#define GCC_BLSP1_UART1_APPS_CLK 80 90254219Scy#define GCC_BLSP1_UART2_APPS_CLK 81 91254219Scy#define GCC_BLSP1_UART3_APPS_CLK 82 92254219Scy#define GCC_BLSP1_UART4_APPS_CLK 83 93254219Scy#define GCC_BLSP1_UART5_APPS_CLK 84 94254219Scy#define GCC_BLSP1_UART6_APPS_CLK 85 95254219Scy#define GCC_CRYPTO_AHB_CLK 86 96254219Scy#define GCC_CRYPTO_AXI_CLK 87 97254219Scy#define GCC_CRYPTO_CLK 88 98254219Scy#define GCC_XO_CLK 89 99254219Scy#define GCC_XO_DIV4_CLK 90 100254219Scy#define GCC_MDIO_AHB_CLK 91 101254219Scy#define GCC_CRYPTO_PPE_CLK 92 102254219Scy#define GCC_NSS_CE_APB_CLK 93 103254219Scy#define GCC_NSS_CE_AXI_CLK 94 104254219Scy#define GCC_NSS_CFG_CLK 95 105254219Scy#define GCC_NSS_CRYPTO_CLK 96 106254219Scy#define GCC_NSS_CSR_CLK 97 107254219Scy#define GCC_NSS_EDMA_CFG_CLK 98 108254219Scy#define GCC_NSS_EDMA_CLK 99 109254219Scy#define GCC_NSS_NOC_CLK 100 110254219Scy#define GCC_NSS_PORT1_RX_CLK 101 111254219Scy#define GCC_NSS_PORT1_TX_CLK 102 112254219Scy#define GCC_NSS_PORT2_RX_CLK 103 113254219Scy#define GCC_NSS_PORT2_TX_CLK 104 114254219Scy#define GCC_NSS_PORT3_RX_CLK 105 115254219Scy#define GCC_NSS_PORT3_TX_CLK 106 116254219Scy#define GCC_NSS_PORT4_RX_CLK 107 117254219Scy#define GCC_NSS_PORT4_TX_CLK 108 118254219Scy#define GCC_NSS_PORT5_RX_CLK 109 119254219Scy#define GCC_NSS_PORT5_TX_CLK 110 120254219Scy#define GCC_NSS_PPE_CFG_CLK 111 121254219Scy#define GCC_NSS_PPE_CLK 112 122254219Scy#define GCC_NSS_PPE_IPE_CLK 113 123254219Scy#define GCC_NSS_PTP_REF_CLK 114 124254219Scy#define GCC_NSSNOC_CE_APB_CLK 115 125254219Scy#define GCC_NSSNOC_CE_AXI_CLK 116 126254219Scy#define GCC_NSSNOC_CRYPTO_CLK 117 127254219Scy#define GCC_NSSNOC_PPE_CFG_CLK 118 128254219Scy#define GCC_NSSNOC_PPE_CLK 119 129254219Scy#define GCC_NSSNOC_QOSGEN_REF_CLK 120 130254219Scy#define GCC_NSSNOC_TIMEOUT_REF_CLK 121 131254219Scy#define GCC_NSSNOC_UBI0_AHB_CLK 122 132254219Scy#define GCC_PORT1_MAC_CLK 123 133254219Scy#define GCC_PORT2_MAC_CLK 124 134254219Scy#define GCC_PORT3_MAC_CLK 125 135254219Scy#define GCC_PORT4_MAC_CLK 126 136254219Scy#define GCC_PORT5_MAC_CLK 127 137254219Scy#define GCC_UBI0_AHB_CLK 128 138254219Scy#define GCC_UBI0_AXI_CLK 129 139254219Scy#define GCC_UBI0_CORE_CLK 130 140254219Scy#define GCC_PCIE0_AHB_CLK 131 141254219Scy#define GCC_PCIE0_AUX_CLK 132 142254219Scy#define GCC_PCIE0_AXI_M_CLK 133 143254219Scy#define GCC_PCIE0_AXI_S_CLK 134 144254219Scy#define GCC_PCIE0_PIPE_CLK 135 145254219Scy#define GCC_PRNG_AHB_CLK 136 146254219Scy#define GCC_QPIC_AHB_CLK 137 147254219Scy#define GCC_QPIC_CLK 138 148254219Scy#define GCC_SDCC1_AHB_CLK 139 149254219Scy#define GCC_SDCC1_APPS_CLK 140 150254219Scy#define GCC_UNIPHY0_AHB_CLK 141 151254219Scy#define GCC_UNIPHY0_PORT1_RX_CLK 142 152254219Scy#define GCC_UNIPHY0_PORT1_TX_CLK 143 153254219Scy#define GCC_UNIPHY0_PORT2_RX_CLK 144 154254219Scy#define GCC_UNIPHY0_PORT2_TX_CLK 145 155254219Scy#define GCC_UNIPHY0_PORT3_RX_CLK 146 156254219Scy#define GCC_UNIPHY0_PORT3_TX_CLK 147 157254219Scy#define GCC_UNIPHY0_PORT4_RX_CLK 148 158254219Scy#define GCC_UNIPHY0_PORT4_TX_CLK 149 159254219Scy#define GCC_UNIPHY0_PORT5_RX_CLK 150 160254219Scy#define GCC_UNIPHY0_PORT5_TX_CLK 151 161254219Scy#define GCC_UNIPHY0_SYS_CLK 152 162254219Scy#define GCC_UNIPHY1_AHB_CLK 153 163254219Scy#define GCC_UNIPHY1_PORT5_RX_CLK 154 164254219Scy#define GCC_UNIPHY1_PORT5_TX_CLK 155 165254219Scy#define GCC_UNIPHY1_SYS_CLK 156 166254219Scy#define GCC_USB0_AUX_CLK 157 167254219Scy#define GCC_USB0_MASTER_CLK 158 168254219Scy#define GCC_USB0_MOCK_UTMI_CLK 159 169254219Scy#define GCC_USB0_PHY_CFG_AHB_CLK 160 170254219Scy#define GCC_USB0_PIPE_CLK 161 171254219Scy#define GCC_USB0_SLEEP_CLK 162 172254219Scy#define GCC_USB1_MASTER_CLK 163 173254219Scy#define GCC_USB1_MOCK_UTMI_CLK 164 174254219Scy#define GCC_USB1_PHY_CFG_AHB_CLK 165 175254219Scy#define GCC_USB1_SLEEP_CLK 166 176254219Scy#define GP1_CLK_SRC 167 177254219Scy#define GP2_CLK_SRC 168 178254219Scy#define GP3_CLK_SRC 169 179254219Scy#define GCC_GP1_CLK 170 180254219Scy#define GCC_GP2_CLK 171 181254219Scy#define GCC_GP3_CLK 172 182254219Scy#define SYSTEM_NOC_BFDCD_CLK_SRC 173 183254219Scy#define GCC_NSSNOC_SNOC_CLK 174 184254219Scy#define GCC_UBI0_NC_AXI_CLK 175 185254219Scy#define GCC_UBI1_NC_AXI_CLK 176 186254219Scy#define GPLL0_MAIN 177 187254219Scy#define UBI32_PLL_MAIN 178 188254219Scy#define GPLL6_MAIN 179 189254219Scy#define GPLL4_MAIN 180 190254219Scy#define GPLL2_MAIN 181 191254219Scy#define NSS_CRYPTO_PLL_MAIN 182 192254219Scy#define GCC_CMN_12GPLL_AHB_CLK 183 193254219Scy#define GCC_CMN_12GPLL_SYS_CLK 184 194254219Scy#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185 195254219Scy#define GCC_SYS_NOC_USB0_AXI_CLK 186 196254219Scy#define GCC_SYS_NOC_PCIE0_AXI_CLK 187 197254219Scy#define QDSS_TSCTR_CLK_SRC 188 198254219Scy#define QDSS_AT_CLK_SRC 189 199254219Scy#define GCC_QDSS_AT_CLK 190 200254219Scy#define GCC_QDSS_DAP_CLK 191 201254219Scy#define ADSS_PWM_CLK_SRC 192 202254219Scy#define GCC_ADSS_PWM_CLK 193 203254219Scy#define SDCC1_ICE_CORE_CLK_SRC 194 204254219Scy#define GCC_SDCC1_ICE_CORE_CLK 195 205254219Scy#define GCC_DCC_CLK 196 206254219Scy#define PCIE0_RCHNG_CLK_SRC 197 207254219Scy#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198 208254219Scy#define PCIE0_RCHNG_CLK 199 209254219Scy#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200 210254219Scy#define WCSS_AHB_CLK_SRC 201 211254219Scy#define Q6_AXI_CLK_SRC 202 212254219Scy#define GCC_Q6SS_PCLKDBG_CLK 203 213254219Scy#define GCC_Q6_TSCTR_1TO2_CLK 204 214254219Scy#define GCC_WCSS_CORE_TBU_CLK 205 215254219Scy#define GCC_WCSS_AXI_M_CLK 206 216254219Scy#define GCC_SYS_NOC_WCSS_AHB_CLK 207 217254219Scy#define GCC_Q6_AXIM_CLK 208 218254219Scy#define GCC_Q6SS_ATBM_CLK 209 219254219Scy#define GCC_WCSS_Q6_TBU_CLK 210 220254219Scy#define GCC_Q6_AXIM2_CLK 211 221254219Scy#define GCC_Q6_AHB_CLK 212 222254219Scy#define GCC_Q6_AHB_S_CLK 213 223254219Scy#define GCC_WCSS_DBG_IFC_APB_CLK 214 224254219Scy#define GCC_WCSS_DBG_IFC_ATB_CLK 215 225254219Scy#define GCC_WCSS_DBG_IFC_NTS_CLK 216 226254219Scy#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217 227254219Scy#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218 228254219Scy#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219 229254219Scy#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220 230254219Scy#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221 231254219Scy#define GCC_WCSS_ECAHB_CLK 222 232254219Scy#define GCC_WCSS_ACMT_CLK 223 233254219Scy#define GCC_WCSS_AHB_S_CLK 224 234254219Scy#define GCC_RBCPR_WCSS_CLK 225 235254219Scy#define RBCPR_WCSS_CLK_SRC 226 236254219Scy#define GCC_RBCPR_WCSS_AHB_CLK 227 237254219Scy#define GCC_LPASS_CORE_AXIM_CLK 228 238254219Scy#define GCC_LPASS_SNOC_CFG_CLK 229 239254219Scy#define GCC_LPASS_Q6_AXIM_CLK 230 240254219Scy#define GCC_LPASS_Q6_ATBM_AT_CLK 231 241254219Scy#define GCC_LPASS_Q6_PCLKDBG_CLK 232 242254219Scy#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233 243254219Scy#define GCC_LPASS_Q6SS_TRIG_CLK 234 244254219Scy#define GCC_LPASS_TBU_CLK 235 245254219Scy#define LPASS_CORE_AXIM_CLK_SRC 236 246254219Scy#define LPASS_SNOC_CFG_CLK_SRC 237 247254219Scy#define LPASS_Q6_AXIM_CLK_SRC 238 248254219Scy#define GCC_PCNOC_LPASS_CLK 239 249254219Scy#define GCC_UBI0_UTCM_CLK 240 250254219Scy#define SNOC_NSSNOC_BFDCD_CLK_SRC 241 251254219Scy#define GCC_SNOC_NSSNOC_CLK 242 252254219Scy#define GCC_MEM_NOC_Q6_AXI_CLK 243 253254219Scy#define GCC_MEM_NOC_UBI32_CLK 244 254254219Scy#define GCC_MEM_NOC_LPASS_CLK 245 255254219Scy#define GCC_SNOC_LPASS_CFG_CLK 246 256254219Scy#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247 257254219Scy#define GCC_QDSS_STM_CLK 248 258254219Scy#define GCC_QDSS_TRACECLKIN_CLK 249 259254219Scy#define QDSS_STM_CLK_SRC 250 260254219Scy#define QDSS_TRACECLKIN_CLK_SRC 251 261254219Scy#define GCC_NSSNOC_ATB_CLK 252 262254219Scy#endif 263254219Scy