1117395Skan/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2117395Skan/* 390075Sobrien * Copyright (C) 2020 Intel Corporation. 450397Sobrien * Lei Chuanhua <Chuanhua.lei@intel.com> 550397Sobrien * Zhu Yixin <Yixin.zhu@intel.com> 6132718Skan */ 750397Sobrien#ifndef __INTEL_LGM_CLK_H 8132718Skan#define __INTEL_LGM_CLK_H 950397Sobrien 1050397Sobrien/* PLL clocks */ 1150397Sobrien#define LGM_CLK_OSC 1 1250397Sobrien#define LGM_CLK_PLLPP 2 13132718Skan#define LGM_CLK_PLL2 3 1450397Sobrien#define LGM_CLK_PLL0CZ 4 1550397Sobrien#define LGM_CLK_PLL0B 5 1650397Sobrien#define LGM_CLK_PLL1 6 1750397Sobrien#define LGM_CLK_LJPLL3 7 1850397Sobrien#define LGM_CLK_LJPLL4 8 19132718Skan#define LGM_CLK_PLL0CM0 9 20169689Skan#define LGM_CLK_PLL0CM1 10 21169689Skan 2250397Sobrien/* clocks from PLLs */ 2390075Sobrien 2490075Sobrien/* ROPLL clocks */ 2590075Sobrien#define LGM_CLK_PP_HW 15 2650397Sobrien#define LGM_CLK_PP_UC 16 2750397Sobrien#define LGM_CLK_PP_FXD 17 2850397Sobrien#define LGM_CLK_PP_TBM 18 2950397Sobrien 3050397Sobrien/* PLL2 clocks */ 3150397Sobrien#define LGM_CLK_DDR 20 3250397Sobrien 3350397Sobrien/* PLL0CZ */ 3450397Sobrien#define LGM_CLK_CM 25 3550397Sobrien#define LGM_CLK_IC 26 3650397Sobrien#define LGM_CLK_SDXC3 27 3750397Sobrien 3850397Sobrien/* PLL0B */ 39117395Skan#define LGM_CLK_NGI 30 4050397Sobrien#define LGM_CLK_NOC4 31 4150397Sobrien#define LGM_CLK_SW 32 4250397Sobrien#define LGM_CLK_QSPI 33 43117395Skan#define LGM_CLK_CQEM LGM_CLK_SW 4450397Sobrien#define LGM_CLK_EMMC5 LGM_CLK_NOC4 4550397Sobrien 4650397Sobrien/* PLL1 */ 4750397Sobrien#define LGM_CLK_CT 35 4850397Sobrien#define LGM_CLK_DSP 36 4950397Sobrien#define LGM_CLK_VIF 37 5050397Sobrien 5150397Sobrien/* LJPLL3 */ 5250397Sobrien#define LGM_CLK_CML 40 5350397Sobrien#define LGM_CLK_SERDES 41 5452284Sobrien#define LGM_CLK_POOL 42 5552284Sobrien#define LGM_CLK_PTP 43 5652284Sobrien 5750397Sobrien/* LJPLL4 */ 5850397Sobrien#define LGM_CLK_PCIE 45 5950397Sobrien#define LGM_CLK_SATA LGM_CLK_PCIE 6050397Sobrien 6150397Sobrien/* PLL0CM0 */ 62132718Skan#define LGM_CLK_CPU0 50 6350397Sobrien 64117395Skan/* PLL0CM1 */ 6550397Sobrien#define LGM_CLK_CPU1 55 6650397Sobrien 67117395Skan/* Miscellaneous clocks */ 6850397Sobrien#define LGM_CLK_EMMC4 60 6950397Sobrien#define LGM_CLK_SDXC2 61 7090075Sobrien#define LGM_CLK_EMMC 62 7190075Sobrien#define LGM_CLK_SDXC 63 7290075Sobrien#define LGM_CLK_SLIC 64 7390075Sobrien#define LGM_CLK_DCL 65 7490075Sobrien#define LGM_CLK_DOCSIS 66 7550397Sobrien#define LGM_CLK_PCM 67 7650397Sobrien#define LGM_CLK_DDR_PHY 68 77117395Skan#define LGM_CLK_PONDEF 69 7850397Sobrien#define LGM_CLK_PL25M 70 7950397Sobrien#define LGM_CLK_PL10M 71 8050397Sobrien#define LGM_CLK_PL1544K 72 8150397Sobrien#define LGM_CLK_PL2048K 73 82117395Skan#define LGM_CLK_PL8K 74 8350397Sobrien#define LGM_CLK_PON_NTR 75 8490075Sobrien#define LGM_CLK_SYNC0 76 8550397Sobrien#define LGM_CLK_SYNC1 77 8650397Sobrien#define LGM_CLK_PROGDIV 78 8750397Sobrien#define LGM_CLK_OD0 79 8850397Sobrien#define LGM_CLK_OD1 80 89132718Skan#define LGM_CLK_CBPHY0 81 9050397Sobrien#define LGM_CLK_CBPHY1 82 9150397Sobrien#define LGM_CLK_CBPHY2 83 9250397Sobrien#define LGM_CLK_CBPHY3 84 9350397Sobrien 9450397Sobrien/* Gate clocks */ 9550397Sobrien/* Gate CLK0 */ 9650397Sobrien#define LGM_GCLK_C55 100 9750397Sobrien#define LGM_GCLK_QSPI 101 9850397Sobrien#define LGM_GCLK_EIP197 102 9950397Sobrien#define LGM_GCLK_VAULT 103 10050397Sobrien#define LGM_GCLK_TOE 104 10150397Sobrien#define LGM_GCLK_SDXC 105 10250397Sobrien#define LGM_GCLK_EMMC 106 10350397Sobrien#define LGM_GCLK_SPI_DBG 107 104117395Skan#define LGM_GCLK_DMA3 108 10550397Sobrien 106117395Skan/* Gate CLK1 */ 10750397Sobrien#define LGM_GCLK_DMA0 120 10850397Sobrien#define LGM_GCLK_LEDC0 121 10950397Sobrien#define LGM_GCLK_LEDC1 122 11050397Sobrien#define LGM_GCLK_I2S0 123 11150397Sobrien#define LGM_GCLK_I2S1 124 11250397Sobrien#define LGM_GCLK_EBU 125 11350397Sobrien#define LGM_GCLK_PWM 126 11450397Sobrien#define LGM_GCLK_I2C0 127 11550397Sobrien#define LGM_GCLK_I2C1 128 11650397Sobrien#define LGM_GCLK_I2C2 129 11750397Sobrien#define LGM_GCLK_I2C3 130 11850397Sobrien#define LGM_GCLK_SSC0 131 11950397Sobrien#define LGM_GCLK_SSC1 132 12050397Sobrien#define LGM_GCLK_SSC2 133 12150397Sobrien#define LGM_GCLK_SSC3 134 12250397Sobrien#define LGM_GCLK_GPTC0 135 12350397Sobrien#define LGM_GCLK_GPTC1 136 12450397Sobrien#define LGM_GCLK_GPTC2 137 12550397Sobrien#define LGM_GCLK_GPTC3 138 12690075Sobrien#define LGM_GCLK_ASC0 139 12790075Sobrien#define LGM_GCLK_ASC1 140 12890075Sobrien#define LGM_GCLK_ASC2 141 129117395Skan#define LGM_GCLK_ASC3 142 13090075Sobrien#define LGM_GCLK_PCM0 143 13190075Sobrien#define LGM_GCLK_PCM1 144 13250397Sobrien#define LGM_GCLK_PCM2 145 13350397Sobrien 13450397Sobrien/* Gate CLK2 */ 13550397Sobrien#define LGM_GCLK_PCIE10 150 13650397Sobrien#define LGM_GCLK_PCIE11 151 13750397Sobrien#define LGM_GCLK_PCIE30 152 13850397Sobrien#define LGM_GCLK_PCIE31 153 13950397Sobrien#define LGM_GCLK_PCIE20 154 14050397Sobrien#define LGM_GCLK_PCIE21 155 14150397Sobrien#define LGM_GCLK_PCIE40 156 14250397Sobrien#define LGM_GCLK_PCIE41 157 14350397Sobrien#define LGM_GCLK_XPCS0 158 14450397Sobrien#define LGM_GCLK_XPCS1 159 14550397Sobrien#define LGM_GCLK_XPCS2 160 14650397Sobrien#define LGM_GCLK_XPCS3 161 14750397Sobrien#define LGM_GCLK_SATA0 162 14850397Sobrien#define LGM_GCLK_SATA1 163 14990075Sobrien#define LGM_GCLK_SATA2 164 15050397Sobrien#define LGM_GCLK_SATA3 165 15190075Sobrien 15250397Sobrien/* Gate CLK3 */ 15390075Sobrien#define LGM_GCLK_ARCEM4 170 15490075Sobrien#define LGM_GCLK_IDMAR1 171 15590075Sobrien#define LGM_GCLK_IDMAT0 172 15650397Sobrien#define LGM_GCLK_IDMAT1 173 15750397Sobrien#define LGM_GCLK_IDMAT2 174 15850397Sobrien#define LGM_GCLK_PPV4 175 15950397Sobrien#define LGM_GCLK_GSWIPO 176 16052284Sobrien#define LGM_GCLK_CQEM 177 16152284Sobrien#define LGM_GCLK_XPCS5 178 16252284Sobrien#define LGM_GCLK_USB1 179 16352284Sobrien#define LGM_GCLK_USB2 180 16452284Sobrien 165#endif /* __INTEL_LGM_CLK_H */ 166