1242723Sjhibbits/* SPDX-License-Identifier: GPL-2.0 */ 2242723Sjhibbits/* 3242723Sjhibbits * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. 4242723Sjhibbits * 5242723Sjhibbits * They are roughly ordered as: 6242723Sjhibbits * - external clocks 7242723Sjhibbits * - PLLs 8242723Sjhibbits * - muxes/dividers in the order they appear in the jz4780 programmers manual 9242723Sjhibbits * - gates in order of their bit in the CLKGR* registers 10242723Sjhibbits */ 11242723Sjhibbits 12242723Sjhibbits#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ 13242723Sjhibbits#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ 14242723Sjhibbits 15242723Sjhibbits#define JZ4780_CLK_EXCLK 0 16242723Sjhibbits#define JZ4780_CLK_RTCLK 1 17242723Sjhibbits#define JZ4780_CLK_APLL 2 18242723Sjhibbits#define JZ4780_CLK_MPLL 3 19242723Sjhibbits#define JZ4780_CLK_EPLL 4 20242723Sjhibbits#define JZ4780_CLK_VPLL 5 21242723Sjhibbits#define JZ4780_CLK_OTGPHY 6 22242723Sjhibbits#define JZ4780_CLK_SCLKA 7 23242723Sjhibbits#define JZ4780_CLK_CPUMUX 8 24242723Sjhibbits#define JZ4780_CLK_CPU 9 25242723Sjhibbits#define JZ4780_CLK_L2CACHE 10 26242723Sjhibbits#define JZ4780_CLK_AHB0 11 27242723Sjhibbits#define JZ4780_CLK_AHB2PMUX 12 28242723Sjhibbits#define JZ4780_CLK_AHB2 13 29242723Sjhibbits#define JZ4780_CLK_PCLK 14 30242723Sjhibbits#define JZ4780_CLK_DDR 15 31242723Sjhibbits#define JZ4780_CLK_VPU 16 32242723Sjhibbits#define JZ4780_CLK_I2SPLL 17 33242723Sjhibbits#define JZ4780_CLK_I2S 18 34242723Sjhibbits#define JZ4780_CLK_LCD0PIXCLK 19 35242723Sjhibbits#define JZ4780_CLK_LCD1PIXCLK 20 36242723Sjhibbits#define JZ4780_CLK_MSCMUX 21 37242723Sjhibbits#define JZ4780_CLK_MSC0 22 38260670Sjhibbits#define JZ4780_CLK_MSC1 23 39260670Sjhibbits#define JZ4780_CLK_MSC2 24 40242723Sjhibbits#define JZ4780_CLK_UHC 25 41242723Sjhibbits#define JZ4780_CLK_SSIPLL 26 42242723Sjhibbits#define JZ4780_CLK_SSI 27 43242723Sjhibbits#define JZ4780_CLK_CIMMCLK 28 44242723Sjhibbits#define JZ4780_CLK_PCMPLL 29 45260670Sjhibbits#define JZ4780_CLK_PCM 30 46260670Sjhibbits#define JZ4780_CLK_GPU 31 47260670Sjhibbits#define JZ4780_CLK_HDMI 32 48260670Sjhibbits#define JZ4780_CLK_BCH 33 49260670Sjhibbits#define JZ4780_CLK_NEMC 34 50242723Sjhibbits#define JZ4780_CLK_OTG0 35 51260670Sjhibbits#define JZ4780_CLK_SSI0 36 52260670Sjhibbits#define JZ4780_CLK_SMB0 37 53260670Sjhibbits#define JZ4780_CLK_SMB1 38 54260670Sjhibbits#define JZ4780_CLK_SCC 39 55260670Sjhibbits#define JZ4780_CLK_AIC 40 56260670Sjhibbits#define JZ4780_CLK_TSSI0 41 57260670Sjhibbits#define JZ4780_CLK_OWI 42 58242723Sjhibbits#define JZ4780_CLK_KBC 43 59242723Sjhibbits#define JZ4780_CLK_SADC 44 60242723Sjhibbits#define JZ4780_CLK_UART0 45 61242723Sjhibbits#define JZ4780_CLK_UART1 46 62242723Sjhibbits#define JZ4780_CLK_UART2 47 63242723Sjhibbits#define JZ4780_CLK_UART3 48 64242723Sjhibbits#define JZ4780_CLK_SSI1 49 65260670Sjhibbits#define JZ4780_CLK_SSI2 50 66260670Sjhibbits#define JZ4780_CLK_PDMA 51 67260670Sjhibbits#define JZ4780_CLK_GPS 52 68260670Sjhibbits#define JZ4780_CLK_MAC 53 69260670Sjhibbits#define JZ4780_CLK_SMB2 54 70260670Sjhibbits#define JZ4780_CLK_CIM 55 71260670Sjhibbits#define JZ4780_CLK_LCD 56 72260670Sjhibbits#define JZ4780_CLK_TVE 57 73260670Sjhibbits#define JZ4780_CLK_IPU 58 74260670Sjhibbits#define JZ4780_CLK_DDR0 59 75260670Sjhibbits#define JZ4780_CLK_DDR1 60 76260670Sjhibbits#define JZ4780_CLK_SMB3 61 77260670Sjhibbits#define JZ4780_CLK_TSSI1 62 78260670Sjhibbits#define JZ4780_CLK_COMPRESS 63 79260670Sjhibbits#define JZ4780_CLK_AIC1 64 80260670Sjhibbits#define JZ4780_CLK_GPVLC 65 81260670Sjhibbits#define JZ4780_CLK_OTG1 66 82260670Sjhibbits#define JZ4780_CLK_UART4 67 83260670Sjhibbits#define JZ4780_CLK_AHBMON 68 84260670Sjhibbits#define JZ4780_CLK_SMB4 69 85260670Sjhibbits#define JZ4780_CLK_DES 70 86260670Sjhibbits#define JZ4780_CLK_X2D 71 87260670Sjhibbits#define JZ4780_CLK_CORE1 72 88260670Sjhibbits#define JZ4780_CLK_EXCLK_DIV512 73 89260670Sjhibbits#define JZ4780_CLK_RTC 74 90260670Sjhibbits 91260670Sjhibbits#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ 92260670Sjhibbits