1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Device Tree binding constants for Bitmain BM1880 SoC
4 *
5 * Copyright (c) 2019 Linaro Ltd.
6 */
7
8#ifndef __DT_BINDINGS_CLOCK_BM1880_H
9#define __DT_BINDINGS_CLOCK_BM1880_H
10
11#define BM1880_CLK_OSC			0
12#define BM1880_CLK_MPLL			1
13#define BM1880_CLK_SPLL			2
14#define BM1880_CLK_FPLL			3
15#define BM1880_CLK_DDRPLL		4
16#define BM1880_CLK_A53			5
17#define BM1880_CLK_50M_A53		6
18#define BM1880_CLK_AHB_ROM		7
19#define BM1880_CLK_AXI_SRAM		8
20#define BM1880_CLK_DDR_AXI		9
21#define BM1880_CLK_EFUSE		10
22#define BM1880_CLK_APB_EFUSE		11
23#define BM1880_CLK_AXI5_EMMC		12
24#define BM1880_CLK_EMMC			13
25#define BM1880_CLK_100K_EMMC		14
26#define BM1880_CLK_AXI5_SD		15
27#define BM1880_CLK_SD			16
28#define BM1880_CLK_100K_SD		17
29#define BM1880_CLK_500M_ETH0		18
30#define BM1880_CLK_AXI4_ETH0		19
31#define BM1880_CLK_500M_ETH1		20
32#define BM1880_CLK_AXI4_ETH1		21
33#define BM1880_CLK_AXI1_GDMA		22
34#define BM1880_CLK_APB_GPIO		23
35#define BM1880_CLK_APB_GPIO_INTR	24
36#define BM1880_CLK_GPIO_DB		25
37#define BM1880_CLK_AXI1_MINER		26
38#define BM1880_CLK_AHB_SF		27
39#define BM1880_CLK_SDMA_AXI		28
40#define BM1880_CLK_SDMA_AUD		29
41#define BM1880_CLK_APB_I2C		30
42#define BM1880_CLK_APB_WDT		31
43#define BM1880_CLK_APB_JPEG		32
44#define BM1880_CLK_JPEG_AXI		33
45#define BM1880_CLK_AXI5_NF		34
46#define BM1880_CLK_APB_NF		35
47#define BM1880_CLK_NF			36
48#define BM1880_CLK_APB_PWM		37
49#define BM1880_CLK_DIV_0_RV		38
50#define BM1880_CLK_DIV_1_RV		39
51#define BM1880_CLK_MUX_RV		40
52#define BM1880_CLK_RV			41
53#define BM1880_CLK_APB_SPI		42
54#define BM1880_CLK_TPU_AXI		43
55#define BM1880_CLK_DIV_UART_500M	44
56#define BM1880_CLK_UART_500M		45
57#define BM1880_CLK_APB_UART		46
58#define BM1880_CLK_APB_I2S		47
59#define BM1880_CLK_AXI4_USB		48
60#define BM1880_CLK_APB_USB		49
61#define BM1880_CLK_125M_USB		50
62#define BM1880_CLK_33K_USB		51
63#define BM1880_CLK_DIV_12M_USB		52
64#define BM1880_CLK_12M_USB		53
65#define BM1880_CLK_APB_VIDEO		54
66#define BM1880_CLK_VIDEO_AXI		55
67#define BM1880_CLK_VPP_AXI		56
68#define BM1880_CLK_APB_VPP		57
69#define BM1880_CLK_DIV_0_AXI1		58
70#define BM1880_CLK_DIV_1_AXI1		59
71#define BM1880_CLK_AXI1			60
72#define BM1880_CLK_AXI2			61
73#define BM1880_CLK_AXI3			62
74#define BM1880_CLK_AXI4			63
75#define BM1880_CLK_AXI5			64
76#define BM1880_CLK_DIV_0_AXI6		65
77#define BM1880_CLK_DIV_1_AXI6		66
78#define BM1880_CLK_MUX_AXI6		67
79#define BM1880_CLK_AXI6			68
80#define BM1880_NR_CLKS			69
81
82#endif /* __DT_BINDINGS_CLOCK_BM1880_H */
83