1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * smscufx.c -- Framebuffer driver for SMSC UFX USB controller 4 * 5 * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net> 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 * 10 * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen, 11 * and others. 12 * 13 * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev 14 * available from http://git.plugable.com 15 * 16 * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven, 17 * usb-skeleton by GregKH. 18 */ 19 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22#include <linux/module.h> 23#include <linux/kernel.h> 24#include <linux/init.h> 25#include <linux/usb.h> 26#include <linux/uaccess.h> 27#include <linux/mm.h> 28#include <linux/fb.h> 29#include <linux/vmalloc.h> 30#include <linux/slab.h> 31#include <linux/delay.h> 32#include "edid.h" 33 34#define check_warn(status, fmt, args...) \ 35 ({ if (status < 0) pr_warn(fmt, ##args); }) 36 37#define check_warn_return(status, fmt, args...) \ 38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } }) 39 40#define check_warn_goto_error(status, fmt, args...) \ 41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } }) 42 43#define all_bits_set(x, bits) (((x) & (bits)) == (bits)) 44 45#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 46#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 47 48/* 49 * TODO: Propose standard fb.h ioctl for reporting damage, 50 * using _IOWR() and one of the existing area structs from fb.h 51 * Consider these ioctls deprecated, but they're still used by the 52 * DisplayLink X server as yet - need both to be modified in tandem 53 * when new ioctl(s) are ready. 54 */ 55#define UFX_IOCTL_RETURN_EDID (0xAD) 56#define UFX_IOCTL_REPORT_DAMAGE (0xAA) 57 58/* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */ 59#define BULK_SIZE (512) 60#define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE) 61#define WRITES_IN_FLIGHT (4) 62 63#define GET_URB_TIMEOUT (HZ) 64#define FREE_URB_TIMEOUT (HZ*2) 65 66#define BPP 2 67 68#define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */ 69#define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */ 70 71struct dloarea { 72 int x, y; 73 int w, h; 74}; 75 76struct urb_node { 77 struct list_head entry; 78 struct ufx_data *dev; 79 struct delayed_work release_urb_work; 80 struct urb *urb; 81}; 82 83struct urb_list { 84 struct list_head list; 85 spinlock_t lock; 86 struct semaphore limit_sem; 87 int available; 88 int count; 89 size_t size; 90}; 91 92struct ufx_data { 93 struct usb_device *udev; 94 struct device *gdev; /* &udev->dev */ 95 struct fb_info *info; 96 struct urb_list urbs; 97 struct kref kref; 98 int fb_count; 99 bool virtualized; /* true when physical usb device not present */ 100 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ 101 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ 102 u8 *edid; /* null until we read edid from hw or get from sysfs */ 103 size_t edid_size; 104 u32 pseudo_palette[256]; 105}; 106 107static struct fb_fix_screeninfo ufx_fix = { 108 .id = "smscufx", 109 .type = FB_TYPE_PACKED_PIXELS, 110 .visual = FB_VISUAL_TRUECOLOR, 111 .xpanstep = 0, 112 .ypanstep = 0, 113 .ywrapstep = 0, 114 .accel = FB_ACCEL_NONE, 115}; 116 117static const u32 smscufx_info_flags = FBINFO_READS_FAST | 118 FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT | 119 FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR; 120 121static const struct usb_device_id id_table[] = { 122 {USB_DEVICE(0x0424, 0x9d00),}, 123 {USB_DEVICE(0x0424, 0x9d01),}, 124 {}, 125}; 126MODULE_DEVICE_TABLE(usb, id_table); 127 128/* module options */ 129static bool console; /* Optionally allow fbcon to consume first framebuffer */ 130static bool fb_defio = true; /* Optionally enable fb_defio mmap support */ 131 132/* ufx keeps a list of urbs for efficient bulk transfers */ 133static void ufx_urb_completion(struct urb *urb); 134static struct urb *ufx_get_urb(struct ufx_data *dev); 135static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len); 136static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size); 137static void ufx_free_urb_list(struct ufx_data *dev); 138 139static DEFINE_MUTEX(disconnect_mutex); 140 141/* reads a control register */ 142static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data) 143{ 144 u32 *buf = kmalloc(4, GFP_KERNEL); 145 int ret; 146 147 BUG_ON(!dev); 148 149 if (!buf) 150 return -ENOMEM; 151 152 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), 153 USB_VENDOR_REQUEST_READ_REGISTER, 154 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 155 00, index, buf, 4, USB_CTRL_GET_TIMEOUT); 156 157 le32_to_cpus(buf); 158 *data = *buf; 159 kfree(buf); 160 161 if (unlikely(ret < 0)) 162 pr_warn("Failed to read register index 0x%08x\n", index); 163 164 return ret; 165} 166 167/* writes a control register */ 168static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data) 169{ 170 u32 *buf = kmalloc(4, GFP_KERNEL); 171 int ret; 172 173 BUG_ON(!dev); 174 175 if (!buf) 176 return -ENOMEM; 177 178 *buf = data; 179 cpu_to_le32s(buf); 180 181 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), 182 USB_VENDOR_REQUEST_WRITE_REGISTER, 183 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 184 00, index, buf, 4, USB_CTRL_SET_TIMEOUT); 185 186 kfree(buf); 187 188 if (unlikely(ret < 0)) 189 pr_warn("Failed to write register index 0x%08x with value " 190 "0x%08x\n", index, data); 191 192 return ret; 193} 194 195static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index, 196 u32 bits_to_clear, u32 bits_to_set) 197{ 198 u32 data; 199 int status = ufx_reg_read(dev, index, &data); 200 check_warn_return(status, "ufx_reg_clear_and_set_bits error reading " 201 "0x%x", index); 202 203 data &= (~bits_to_clear); 204 data |= bits_to_set; 205 206 status = ufx_reg_write(dev, index, data); 207 check_warn_return(status, "ufx_reg_clear_and_set_bits error writing " 208 "0x%x", index); 209 210 return 0; 211} 212 213static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits) 214{ 215 return ufx_reg_clear_and_set_bits(dev, index, 0, bits); 216} 217 218static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits) 219{ 220 return ufx_reg_clear_and_set_bits(dev, index, bits, 0); 221} 222 223static int ufx_lite_reset(struct ufx_data *dev) 224{ 225 int status; 226 u32 value; 227 228 status = ufx_reg_write(dev, 0x3008, 0x00000001); 229 check_warn_return(status, "ufx_lite_reset error writing 0x3008"); 230 231 status = ufx_reg_read(dev, 0x3008, &value); 232 check_warn_return(status, "ufx_lite_reset error reading 0x3008"); 233 234 return (value == 0) ? 0 : -EIO; 235} 236 237/* If display is unblanked, then blank it */ 238static int ufx_blank(struct ufx_data *dev, bool wait) 239{ 240 u32 dc_ctrl, dc_sts; 241 int i; 242 243 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 244 check_warn_return(status, "ufx_blank error reading 0x2004"); 245 246 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 247 check_warn_return(status, "ufx_blank error reading 0x2000"); 248 249 /* return success if display is already blanked */ 250 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100)) 251 return 0; 252 253 /* request the DC to blank the display */ 254 dc_ctrl |= 0x00000100; 255 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 256 check_warn_return(status, "ufx_blank error writing 0x2000"); 257 258 /* return success immediately if we don't have to wait */ 259 if (!wait) 260 return 0; 261 262 for (i = 0; i < 250; i++) { 263 status = ufx_reg_read(dev, 0x2004, &dc_sts); 264 check_warn_return(status, "ufx_blank error reading 0x2004"); 265 266 if (dc_sts & 0x00000100) 267 return 0; 268 } 269 270 /* timed out waiting for display to blank */ 271 return -EIO; 272} 273 274/* If display is blanked, then unblank it */ 275static int ufx_unblank(struct ufx_data *dev, bool wait) 276{ 277 u32 dc_ctrl, dc_sts; 278 int i; 279 280 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 281 check_warn_return(status, "ufx_unblank error reading 0x2004"); 282 283 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 284 check_warn_return(status, "ufx_unblank error reading 0x2000"); 285 286 /* return success if display is already unblanked */ 287 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0)) 288 return 0; 289 290 /* request the DC to unblank the display */ 291 dc_ctrl &= ~0x00000100; 292 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 293 check_warn_return(status, "ufx_unblank error writing 0x2000"); 294 295 /* return success immediately if we don't have to wait */ 296 if (!wait) 297 return 0; 298 299 for (i = 0; i < 250; i++) { 300 status = ufx_reg_read(dev, 0x2004, &dc_sts); 301 check_warn_return(status, "ufx_unblank error reading 0x2004"); 302 303 if ((dc_sts & 0x00000100) == 0) 304 return 0; 305 } 306 307 /* timed out waiting for display to unblank */ 308 return -EIO; 309} 310 311/* If display is enabled, then disable it */ 312static int ufx_disable(struct ufx_data *dev, bool wait) 313{ 314 u32 dc_ctrl, dc_sts; 315 int i; 316 317 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 318 check_warn_return(status, "ufx_disable error reading 0x2004"); 319 320 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 321 check_warn_return(status, "ufx_disable error reading 0x2000"); 322 323 /* return success if display is already disabled */ 324 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0)) 325 return 0; 326 327 /* request the DC to disable the display */ 328 dc_ctrl &= ~(0x00000001); 329 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 330 check_warn_return(status, "ufx_disable error writing 0x2000"); 331 332 /* return success immediately if we don't have to wait */ 333 if (!wait) 334 return 0; 335 336 for (i = 0; i < 250; i++) { 337 status = ufx_reg_read(dev, 0x2004, &dc_sts); 338 check_warn_return(status, "ufx_disable error reading 0x2004"); 339 340 if ((dc_sts & 0x00000001) == 0) 341 return 0; 342 } 343 344 /* timed out waiting for display to disable */ 345 return -EIO; 346} 347 348/* If display is disabled, then enable it */ 349static int ufx_enable(struct ufx_data *dev, bool wait) 350{ 351 u32 dc_ctrl, dc_sts; 352 int i; 353 354 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 355 check_warn_return(status, "ufx_enable error reading 0x2004"); 356 357 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 358 check_warn_return(status, "ufx_enable error reading 0x2000"); 359 360 /* return success if display is already enabled */ 361 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001)) 362 return 0; 363 364 /* request the DC to enable the display */ 365 dc_ctrl |= 0x00000001; 366 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 367 check_warn_return(status, "ufx_enable error writing 0x2000"); 368 369 /* return success immediately if we don't have to wait */ 370 if (!wait) 371 return 0; 372 373 for (i = 0; i < 250; i++) { 374 status = ufx_reg_read(dev, 0x2004, &dc_sts); 375 check_warn_return(status, "ufx_enable error reading 0x2004"); 376 377 if (dc_sts & 0x00000001) 378 return 0; 379 } 380 381 /* timed out waiting for display to enable */ 382 return -EIO; 383} 384 385static int ufx_config_sys_clk(struct ufx_data *dev) 386{ 387 int status = ufx_reg_write(dev, 0x700C, 0x8000000F); 388 check_warn_return(status, "error writing 0x700C"); 389 390 status = ufx_reg_write(dev, 0x7014, 0x0010024F); 391 check_warn_return(status, "error writing 0x7014"); 392 393 status = ufx_reg_write(dev, 0x7010, 0x00000000); 394 check_warn_return(status, "error writing 0x7010"); 395 396 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A); 397 check_warn_return(status, "error clearing PLL1 bypass in 0x700C"); 398 msleep(1); 399 400 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000); 401 check_warn_return(status, "error clearing output gate in 0x700C"); 402 403 return 0; 404} 405 406static int ufx_config_ddr2(struct ufx_data *dev) 407{ 408 int status, i = 0; 409 u32 tmp; 410 411 status = ufx_reg_write(dev, 0x0004, 0x001F0F77); 412 check_warn_return(status, "error writing 0x0004"); 413 414 status = ufx_reg_write(dev, 0x0008, 0xFFF00000); 415 check_warn_return(status, "error writing 0x0008"); 416 417 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222); 418 check_warn_return(status, "error writing 0x000C"); 419 420 status = ufx_reg_write(dev, 0x0010, 0x00030814); 421 check_warn_return(status, "error writing 0x0010"); 422 423 status = ufx_reg_write(dev, 0x0014, 0x00500019); 424 check_warn_return(status, "error writing 0x0014"); 425 426 status = ufx_reg_write(dev, 0x0018, 0x020D0F15); 427 check_warn_return(status, "error writing 0x0018"); 428 429 status = ufx_reg_write(dev, 0x001C, 0x02532305); 430 check_warn_return(status, "error writing 0x001C"); 431 432 status = ufx_reg_write(dev, 0x0020, 0x0B030905); 433 check_warn_return(status, "error writing 0x0020"); 434 435 status = ufx_reg_write(dev, 0x0024, 0x00000827); 436 check_warn_return(status, "error writing 0x0024"); 437 438 status = ufx_reg_write(dev, 0x0028, 0x00000000); 439 check_warn_return(status, "error writing 0x0028"); 440 441 status = ufx_reg_write(dev, 0x002C, 0x00000042); 442 check_warn_return(status, "error writing 0x002C"); 443 444 status = ufx_reg_write(dev, 0x0030, 0x09520000); 445 check_warn_return(status, "error writing 0x0030"); 446 447 status = ufx_reg_write(dev, 0x0034, 0x02223314); 448 check_warn_return(status, "error writing 0x0034"); 449 450 status = ufx_reg_write(dev, 0x0038, 0x00430043); 451 check_warn_return(status, "error writing 0x0038"); 452 453 status = ufx_reg_write(dev, 0x003C, 0xF00F000F); 454 check_warn_return(status, "error writing 0x003C"); 455 456 status = ufx_reg_write(dev, 0x0040, 0xF380F00F); 457 check_warn_return(status, "error writing 0x0040"); 458 459 status = ufx_reg_write(dev, 0x0044, 0xF00F0496); 460 check_warn_return(status, "error writing 0x0044"); 461 462 status = ufx_reg_write(dev, 0x0048, 0x03080406); 463 check_warn_return(status, "error writing 0x0048"); 464 465 status = ufx_reg_write(dev, 0x004C, 0x00001000); 466 check_warn_return(status, "error writing 0x004C"); 467 468 status = ufx_reg_write(dev, 0x005C, 0x00000007); 469 check_warn_return(status, "error writing 0x005C"); 470 471 status = ufx_reg_write(dev, 0x0100, 0x54F00012); 472 check_warn_return(status, "error writing 0x0100"); 473 474 status = ufx_reg_write(dev, 0x0104, 0x00004012); 475 check_warn_return(status, "error writing 0x0104"); 476 477 status = ufx_reg_write(dev, 0x0118, 0x40404040); 478 check_warn_return(status, "error writing 0x0118"); 479 480 status = ufx_reg_write(dev, 0x0000, 0x00000001); 481 check_warn_return(status, "error writing 0x0000"); 482 483 while (i++ < 500) { 484 status = ufx_reg_read(dev, 0x0000, &tmp); 485 check_warn_return(status, "error reading 0x0000"); 486 487 if (all_bits_set(tmp, 0xC0000000)) 488 return 0; 489 } 490 491 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp); 492 return -ETIMEDOUT; 493} 494 495struct pll_values { 496 u32 div_r0; 497 u32 div_f0; 498 u32 div_q0; 499 u32 range0; 500 u32 div_r1; 501 u32 div_f1; 502 u32 div_q1; 503 u32 range1; 504}; 505 506static u32 ufx_calc_range(u32 ref_freq) 507{ 508 if (ref_freq >= 88000000) 509 return 7; 510 511 if (ref_freq >= 54000000) 512 return 6; 513 514 if (ref_freq >= 34000000) 515 return 5; 516 517 if (ref_freq >= 21000000) 518 return 4; 519 520 if (ref_freq >= 13000000) 521 return 3; 522 523 if (ref_freq >= 8000000) 524 return 2; 525 526 return 1; 527} 528 529/* calculates PLL divider settings for a desired target frequency */ 530static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll) 531{ 532 const u32 ref_clk = 25000000; 533 u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1; 534 u32 min_error = clk_pixel_pll; 535 536 for (div_r0 = 1; div_r0 <= 32; div_r0++) { 537 u32 ref_freq0 = ref_clk / div_r0; 538 if (ref_freq0 < 5000000) 539 break; 540 541 if (ref_freq0 > 200000000) 542 continue; 543 544 for (div_f0 = 1; div_f0 <= 256; div_f0++) { 545 u32 vco_freq0 = ref_freq0 * div_f0; 546 547 if (vco_freq0 < 350000000) 548 continue; 549 550 if (vco_freq0 > 700000000) 551 break; 552 553 for (div_q0 = 0; div_q0 < 7; div_q0++) { 554 u32 pllout_freq0 = vco_freq0 / (1 << div_q0); 555 556 if (pllout_freq0 < 5000000) 557 break; 558 559 if (pllout_freq0 > 200000000) 560 continue; 561 562 for (div_r1 = 1; div_r1 <= 32; div_r1++) { 563 u32 ref_freq1 = pllout_freq0 / div_r1; 564 565 if (ref_freq1 < 5000000) 566 break; 567 568 for (div_f1 = 1; div_f1 <= 256; div_f1++) { 569 u32 vco_freq1 = ref_freq1 * div_f1; 570 571 if (vco_freq1 < 350000000) 572 continue; 573 574 if (vco_freq1 > 700000000) 575 break; 576 577 for (div_q1 = 0; div_q1 < 7; div_q1++) { 578 u32 pllout_freq1 = vco_freq1 / (1 << div_q1); 579 int error = abs(pllout_freq1 - clk_pixel_pll); 580 581 if (pllout_freq1 < 5000000) 582 break; 583 584 if (pllout_freq1 > 700000000) 585 continue; 586 587 if (error < min_error) { 588 min_error = error; 589 590 /* final returned value is equal to calculated value - 1 591 * because a value of 0 = divide by 1 */ 592 asic_pll->div_r0 = div_r0 - 1; 593 asic_pll->div_f0 = div_f0 - 1; 594 asic_pll->div_q0 = div_q0; 595 asic_pll->div_r1 = div_r1 - 1; 596 asic_pll->div_f1 = div_f1 - 1; 597 asic_pll->div_q1 = div_q1; 598 599 asic_pll->range0 = ufx_calc_range(ref_freq0); 600 asic_pll->range1 = ufx_calc_range(ref_freq1); 601 602 if (min_error == 0) 603 return; 604 } 605 } 606 } 607 } 608 } 609 } 610 } 611} 612 613/* sets analog bit PLL configuration values */ 614static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock) 615{ 616 struct pll_values asic_pll = {0}; 617 u32 value, clk_pixel, clk_pixel_pll; 618 int status; 619 620 /* convert pixclock (in ps) to frequency (in Hz) */ 621 clk_pixel = PICOS2KHZ(pixclock) * 1000; 622 pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel); 623 624 /* clk_pixel = 1/2 clk_pixel_pll */ 625 clk_pixel_pll = clk_pixel * 2; 626 627 ufx_calc_pll_values(clk_pixel_pll, &asic_pll); 628 629 /* Keep BYPASS and RESET signals asserted until configured */ 630 status = ufx_reg_write(dev, 0x7000, 0x8000000F); 631 check_warn_return(status, "error writing 0x7000"); 632 633 value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) | 634 (asic_pll.div_q1 << 16) | (asic_pll.range1 << 20)); 635 status = ufx_reg_write(dev, 0x7008, value); 636 check_warn_return(status, "error writing 0x7008"); 637 638 value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) | 639 (asic_pll.div_q0 << 16) | (asic_pll.range0 << 20)); 640 status = ufx_reg_write(dev, 0x7004, value); 641 check_warn_return(status, "error writing 0x7004"); 642 643 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005); 644 check_warn_return(status, 645 "error clearing PLL0 bypass bits in 0x7000"); 646 msleep(1); 647 648 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A); 649 check_warn_return(status, 650 "error clearing PLL1 bypass bits in 0x7000"); 651 msleep(1); 652 653 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000); 654 check_warn_return(status, "error clearing gate bits in 0x7000"); 655 656 return 0; 657} 658 659static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var) 660{ 661 u32 temp; 662 u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end; 663 u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end; 664 665 int status = ufx_reg_write(dev, 0x8028, 0); 666 check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad"); 667 668 status = ufx_reg_write(dev, 0x8024, 0); 669 check_warn_return(status, "ufx_set_vid_mode error disabling VDAC"); 670 671 /* shut everything down before changing timing */ 672 status = ufx_blank(dev, true); 673 check_warn_return(status, "ufx_set_vid_mode error blanking display"); 674 675 status = ufx_disable(dev, true); 676 check_warn_return(status, "ufx_set_vid_mode error disabling display"); 677 678 status = ufx_config_pix_clk(dev, var->pixclock); 679 check_warn_return(status, "ufx_set_vid_mode error configuring pixclock"); 680 681 status = ufx_reg_write(dev, 0x2000, 0x00000104); 682 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000"); 683 684 /* set horizontal timings */ 685 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin; 686 h_active = var->xres; 687 h_blank_start = var->xres + var->right_margin; 688 h_blank_end = var->xres + var->right_margin + var->hsync_len; 689 h_sync_start = var->xres + var->right_margin; 690 h_sync_end = var->xres + var->right_margin + var->hsync_len; 691 692 temp = ((h_total - 1) << 16) | (h_active - 1); 693 status = ufx_reg_write(dev, 0x2008, temp); 694 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008"); 695 696 temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1); 697 status = ufx_reg_write(dev, 0x200C, temp); 698 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C"); 699 700 temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1); 701 status = ufx_reg_write(dev, 0x2010, temp); 702 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010"); 703 704 /* set vertical timings */ 705 v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; 706 v_active = var->yres; 707 v_blank_start = var->yres + var->lower_margin; 708 v_blank_end = var->yres + var->lower_margin + var->vsync_len; 709 v_sync_start = var->yres + var->lower_margin; 710 v_sync_end = var->yres + var->lower_margin + var->vsync_len; 711 712 temp = ((v_total - 1) << 16) | (v_active - 1); 713 status = ufx_reg_write(dev, 0x2014, temp); 714 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014"); 715 716 temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1); 717 status = ufx_reg_write(dev, 0x2018, temp); 718 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018"); 719 720 temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1); 721 status = ufx_reg_write(dev, 0x201C, temp); 722 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C"); 723 724 status = ufx_reg_write(dev, 0x2020, 0x00000000); 725 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020"); 726 727 status = ufx_reg_write(dev, 0x2024, 0x00000000); 728 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024"); 729 730 /* Set the frame length register (#pix * 2 bytes/pixel) */ 731 temp = var->xres * var->yres * 2; 732 temp = (temp + 7) & (~0x7); 733 status = ufx_reg_write(dev, 0x2028, temp); 734 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028"); 735 736 /* enable desired output interface & disable others */ 737 status = ufx_reg_write(dev, 0x2040, 0); 738 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 739 740 status = ufx_reg_write(dev, 0x2044, 0); 741 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044"); 742 743 status = ufx_reg_write(dev, 0x2048, 0); 744 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048"); 745 746 /* set the sync polarities & enable bit */ 747 temp = 0x00000001; 748 if (var->sync & FB_SYNC_HOR_HIGH_ACT) 749 temp |= 0x00000010; 750 751 if (var->sync & FB_SYNC_VERT_HIGH_ACT) 752 temp |= 0x00000008; 753 754 status = ufx_reg_write(dev, 0x2040, temp); 755 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 756 757 /* start everything back up */ 758 status = ufx_enable(dev, true); 759 check_warn_return(status, "ufx_set_vid_mode error enabling display"); 760 761 /* Unblank the display */ 762 status = ufx_unblank(dev, true); 763 check_warn_return(status, "ufx_set_vid_mode error unblanking display"); 764 765 /* enable RGB pad */ 766 status = ufx_reg_write(dev, 0x8028, 0x00000003); 767 check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad"); 768 769 /* enable VDAC */ 770 status = ufx_reg_write(dev, 0x8024, 0x00000007); 771 check_warn_return(status, "ufx_set_vid_mode error enabling VDAC"); 772 773 return 0; 774} 775 776static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) 777{ 778 unsigned long start = vma->vm_start; 779 unsigned long size = vma->vm_end - vma->vm_start; 780 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 781 unsigned long page, pos; 782 783 if (info->fbdefio) 784 return fb_deferred_io_mmap(info, vma); 785 786 vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); 787 788 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) 789 return -EINVAL; 790 if (size > info->fix.smem_len) 791 return -EINVAL; 792 if (offset > info->fix.smem_len - size) 793 return -EINVAL; 794 795 pos = (unsigned long)info->fix.smem_start + offset; 796 797 pr_debug("mmap() framebuffer addr:%lu size:%lu\n", 798 pos, size); 799 800 while (size > 0) { 801 page = vmalloc_to_pfn((void *)pos); 802 if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED)) 803 return -EAGAIN; 804 805 start += PAGE_SIZE; 806 pos += PAGE_SIZE; 807 if (size > PAGE_SIZE) 808 size -= PAGE_SIZE; 809 else 810 size = 0; 811 } 812 813 return 0; 814} 815 816static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y, 817 int width, int height) 818{ 819 size_t packed_line_len = ALIGN((width * 2), 4); 820 size_t packed_rect_len = packed_line_len * height; 821 int line; 822 823 BUG_ON(!dev); 824 BUG_ON(!dev->info); 825 826 /* command word */ 827 *((u32 *)&cmd[0]) = cpu_to_le32(0x01); 828 829 /* length word */ 830 *((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16); 831 832 cmd[4] = cpu_to_le16(x); 833 cmd[5] = cpu_to_le16(y); 834 cmd[6] = cpu_to_le16(width); 835 cmd[7] = cpu_to_le16(height); 836 837 /* frame base address */ 838 *((u32 *)&cmd[8]) = cpu_to_le32(0); 839 840 /* color mode and horizontal resolution */ 841 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres); 842 843 /* vertical resolution */ 844 cmd[11] = cpu_to_le16(dev->info->var.yres); 845 846 /* packed data */ 847 for (line = 0; line < height; line++) { 848 const int line_offset = dev->info->fix.line_length * (y + line); 849 const int byte_offset = line_offset + (x * BPP); 850 memcpy(&cmd[(24 + (packed_line_len * line)) / 2], 851 (char *)dev->info->fix.smem_start + byte_offset, width * BPP); 852 } 853} 854 855static int ufx_handle_damage(struct ufx_data *dev, int x, int y, 856 int width, int height) 857{ 858 size_t packed_line_len = ALIGN((width * 2), 4); 859 int len, status, urb_lines, start_line = 0; 860 861 if ((width <= 0) || (height <= 0) || 862 (x + width > dev->info->var.xres) || 863 (y + height > dev->info->var.yres)) 864 return -EINVAL; 865 866 if (!atomic_read(&dev->usb_active)) 867 return 0; 868 869 while (start_line < height) { 870 struct urb *urb = ufx_get_urb(dev); 871 if (!urb) { 872 pr_warn("ufx_handle_damage unable to get urb"); 873 return 0; 874 } 875 876 /* assume we have enough space to transfer at least one line */ 877 BUG_ON(urb->transfer_buffer_length < (24 + (width * 2))); 878 879 /* calculate the maximum number of lines we could fit in */ 880 urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len; 881 882 /* but we might not need this many */ 883 urb_lines = min(urb_lines, (height - start_line)); 884 885 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length); 886 887 ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines); 888 len = 24 + (packed_line_len * urb_lines); 889 890 status = ufx_submit_urb(dev, urb, len); 891 check_warn_return(status, "Error submitting URB"); 892 893 start_line += urb_lines; 894 } 895 896 return 0; 897} 898 899/* NOTE: fb_defio.c is holding info->fbdefio.mutex 900 * Touching ANY framebuffer memory that triggers a page fault 901 * in fb_defio will cause a deadlock, when it also tries to 902 * grab the same mutex. */ 903static void ufx_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist) 904{ 905 struct ufx_data *dev = info->par; 906 struct fb_deferred_io_pageref *pageref; 907 908 if (!fb_defio) 909 return; 910 911 if (!atomic_read(&dev->usb_active)) 912 return; 913 914 /* walk the written page list and render each to device */ 915 list_for_each_entry(pageref, pagereflist, list) { 916 /* create a rectangle of full screen width that encloses the 917 * entire dirty framebuffer page */ 918 const int x = 0; 919 const int width = dev->info->var.xres; 920 const int y = pageref->offset / (width * 2); 921 int height = (PAGE_SIZE / (width * 2)) + 1; 922 height = min(height, (int)(dev->info->var.yres - y)); 923 924 BUG_ON(y >= dev->info->var.yres); 925 BUG_ON((y + height) > dev->info->var.yres); 926 927 ufx_handle_damage(dev, x, y, width, height); 928 } 929} 930 931static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd, 932 unsigned long arg) 933{ 934 struct ufx_data *dev = info->par; 935 struct dloarea *area = NULL; 936 937 if (!atomic_read(&dev->usb_active)) 938 return 0; 939 940 /* TODO: Update X server to get this from sysfs instead */ 941 if (cmd == UFX_IOCTL_RETURN_EDID) { 942 u8 __user *edid = (u8 __user *)arg; 943 if (copy_to_user(edid, dev->edid, dev->edid_size)) 944 return -EFAULT; 945 return 0; 946 } 947 948 /* TODO: Help propose a standard fb.h ioctl to report mmap damage */ 949 if (cmd == UFX_IOCTL_REPORT_DAMAGE) { 950 /* If we have a damage-aware client, turn fb_defio "off" 951 * To avoid perf imact of unnecessary page fault handling. 952 * Done by resetting the delay for this fb_info to a very 953 * long period. Pages will become writable and stay that way. 954 * Reset to normal value when all clients have closed this fb. 955 */ 956 if (info->fbdefio) 957 info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE; 958 959 area = (struct dloarea *)arg; 960 961 if (area->x < 0) 962 area->x = 0; 963 964 if (area->x > info->var.xres) 965 area->x = info->var.xres; 966 967 if (area->y < 0) 968 area->y = 0; 969 970 if (area->y > info->var.yres) 971 area->y = info->var.yres; 972 973 ufx_handle_damage(dev, area->x, area->y, area->w, area->h); 974 } 975 976 return 0; 977} 978 979/* taken from vesafb */ 980static int 981ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green, 982 unsigned blue, unsigned transp, struct fb_info *info) 983{ 984 int err = 0; 985 986 if (regno >= info->cmap.len) 987 return 1; 988 989 if (regno < 16) { 990 if (info->var.red.offset == 10) { 991 /* 1:5:5:5 */ 992 ((u32 *) (info->pseudo_palette))[regno] = 993 ((red & 0xf800) >> 1) | 994 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); 995 } else { 996 /* 0:5:6:5 */ 997 ((u32 *) (info->pseudo_palette))[regno] = 998 ((red & 0xf800)) | 999 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); 1000 } 1001 } 1002 1003 return err; 1004} 1005 1006/* It's common for several clients to have framebuffer open simultaneously. 1007 * e.g. both fbcon and X. Makes things interesting. 1008 * Assumes caller is holding info->lock (for open and release at least) */ 1009static int ufx_ops_open(struct fb_info *info, int user) 1010{ 1011 struct ufx_data *dev = info->par; 1012 1013 /* fbcon aggressively connects to first framebuffer it finds, 1014 * preventing other clients (X) from working properly. Usually 1015 * not what the user wants. Fail by default with option to enable. */ 1016 if (user == 0 && !console) 1017 return -EBUSY; 1018 1019 mutex_lock(&disconnect_mutex); 1020 1021 /* If the USB device is gone, we don't accept new opens */ 1022 if (dev->virtualized) { 1023 mutex_unlock(&disconnect_mutex); 1024 return -ENODEV; 1025 } 1026 1027 dev->fb_count++; 1028 1029 kref_get(&dev->kref); 1030 1031 if (fb_defio && (info->fbdefio == NULL)) { 1032 /* enable defio at last moment if not disabled by client */ 1033 1034 struct fb_deferred_io *fbdefio; 1035 1036 fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL); 1037 if (fbdefio) { 1038 fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1039 fbdefio->deferred_io = ufx_dpy_deferred_io; 1040 } 1041 1042 info->fbdefio = fbdefio; 1043 fb_deferred_io_init(info); 1044 } 1045 1046 pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d", 1047 info->node, user, info, dev->fb_count); 1048 1049 mutex_unlock(&disconnect_mutex); 1050 1051 return 0; 1052} 1053 1054/* 1055 * Called when all client interfaces to start transactions have been disabled, 1056 * and all references to our device instance (ufx_data) are released. 1057 * Every transaction must have a reference, so we know are fully spun down 1058 */ 1059static void ufx_free(struct kref *kref) 1060{ 1061 struct ufx_data *dev = container_of(kref, struct ufx_data, kref); 1062 1063 kfree(dev); 1064} 1065 1066static void ufx_ops_destory(struct fb_info *info) 1067{ 1068 struct ufx_data *dev = info->par; 1069 int node = info->node; 1070 1071 /* Assume info structure is freed after this point */ 1072 framebuffer_release(info); 1073 1074 pr_debug("fb_info for /dev/fb%d has been freed", node); 1075 1076 /* release reference taken by kref_init in probe() */ 1077 kref_put(&dev->kref, ufx_free); 1078} 1079 1080 1081static void ufx_release_urb_work(struct work_struct *work) 1082{ 1083 struct urb_node *unode = container_of(work, struct urb_node, 1084 release_urb_work.work); 1085 1086 up(&unode->dev->urbs.limit_sem); 1087} 1088 1089static void ufx_free_framebuffer(struct ufx_data *dev) 1090{ 1091 struct fb_info *info = dev->info; 1092 1093 if (info->cmap.len != 0) 1094 fb_dealloc_cmap(&info->cmap); 1095 if (info->monspecs.modedb) 1096 fb_destroy_modedb(info->monspecs.modedb); 1097 vfree(info->screen_buffer); 1098 1099 fb_destroy_modelist(&info->modelist); 1100 1101 dev->info = NULL; 1102 1103 /* ref taken in probe() as part of registering framebfufer */ 1104 kref_put(&dev->kref, ufx_free); 1105} 1106 1107/* 1108 * Assumes caller is holding info->lock mutex (for open and release at least) 1109 */ 1110static int ufx_ops_release(struct fb_info *info, int user) 1111{ 1112 struct ufx_data *dev = info->par; 1113 1114 mutex_lock(&disconnect_mutex); 1115 1116 dev->fb_count--; 1117 1118 /* We can't free fb_info here - fbmem will touch it when we return */ 1119 if (dev->virtualized && (dev->fb_count == 0)) 1120 ufx_free_framebuffer(dev); 1121 1122 if ((dev->fb_count == 0) && (info->fbdefio)) { 1123 fb_deferred_io_cleanup(info); 1124 kfree(info->fbdefio); 1125 info->fbdefio = NULL; 1126 } 1127 1128 pr_debug("released /dev/fb%d user=%d count=%d", 1129 info->node, user, dev->fb_count); 1130 1131 kref_put(&dev->kref, ufx_free); 1132 1133 mutex_unlock(&disconnect_mutex); 1134 1135 return 0; 1136} 1137 1138/* Check whether a video mode is supported by the chip 1139 * We start from monitor's modes, so don't need to filter that here */ 1140static int ufx_is_valid_mode(struct fb_videomode *mode, 1141 struct fb_info *info) 1142{ 1143 if ((mode->xres * mode->yres) > (2048 * 1152)) { 1144 pr_debug("%dx%d too many pixels", 1145 mode->xres, mode->yres); 1146 return 0; 1147 } 1148 1149 if (mode->pixclock < 5000) { 1150 pr_debug("%dx%d %dps pixel clock too fast", 1151 mode->xres, mode->yres, mode->pixclock); 1152 return 0; 1153 } 1154 1155 pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres, 1156 mode->pixclock, (1000000 / mode->pixclock)); 1157 return 1; 1158} 1159 1160static void ufx_var_color_format(struct fb_var_screeninfo *var) 1161{ 1162 const struct fb_bitfield red = { 11, 5, 0 }; 1163 const struct fb_bitfield green = { 5, 6, 0 }; 1164 const struct fb_bitfield blue = { 0, 5, 0 }; 1165 1166 var->bits_per_pixel = 16; 1167 var->red = red; 1168 var->green = green; 1169 var->blue = blue; 1170} 1171 1172static int ufx_ops_check_var(struct fb_var_screeninfo *var, 1173 struct fb_info *info) 1174{ 1175 struct fb_videomode mode; 1176 1177 /* TODO: support dynamically changing framebuffer size */ 1178 if ((var->xres * var->yres * 2) > info->fix.smem_len) 1179 return -EINVAL; 1180 1181 /* set device-specific elements of var unrelated to mode */ 1182 ufx_var_color_format(var); 1183 1184 fb_var_to_videomode(&mode, var); 1185 1186 if (!ufx_is_valid_mode(&mode, info)) 1187 return -EINVAL; 1188 1189 return 0; 1190} 1191 1192static int ufx_ops_set_par(struct fb_info *info) 1193{ 1194 struct ufx_data *dev = info->par; 1195 int result; 1196 u16 *pix_framebuffer; 1197 int i; 1198 1199 pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres); 1200 result = ufx_set_vid_mode(dev, &info->var); 1201 1202 if ((result == 0) && (dev->fb_count == 0)) { 1203 /* paint greenscreen */ 1204 pix_framebuffer = (u16 *)info->screen_buffer; 1205 for (i = 0; i < info->fix.smem_len / 2; i++) 1206 pix_framebuffer[i] = 0x37e6; 1207 1208 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres); 1209 } 1210 1211 /* re-enable defio if previously disabled by damage tracking */ 1212 if (info->fbdefio) 1213 info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1214 1215 return result; 1216} 1217 1218/* In order to come back from full DPMS off, we need to set the mode again */ 1219static int ufx_ops_blank(int blank_mode, struct fb_info *info) 1220{ 1221 struct ufx_data *dev = info->par; 1222 ufx_set_vid_mode(dev, &info->var); 1223 return 0; 1224} 1225 1226static void ufx_ops_damage_range(struct fb_info *info, off_t off, size_t len) 1227{ 1228 struct ufx_data *dev = info->par; 1229 int start = max((int)(off / info->fix.line_length), 0); 1230 int lines = min((u32)((len / info->fix.line_length) + 1), (u32)info->var.yres); 1231 1232 ufx_handle_damage(dev, 0, start, info->var.xres, lines); 1233} 1234 1235static void ufx_ops_damage_area(struct fb_info *info, u32 x, u32 y, u32 width, u32 height) 1236{ 1237 struct ufx_data *dev = info->par; 1238 1239 ufx_handle_damage(dev, x, y, width, height); 1240} 1241 1242FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(ufx_ops, 1243 ufx_ops_damage_range, 1244 ufx_ops_damage_area) 1245 1246static const struct fb_ops ufx_ops = { 1247 .owner = THIS_MODULE, 1248 __FB_DEFAULT_DEFERRED_OPS_RDWR(ufx_ops), 1249 .fb_setcolreg = ufx_ops_setcolreg, 1250 __FB_DEFAULT_DEFERRED_OPS_DRAW(ufx_ops), 1251 .fb_mmap = ufx_ops_mmap, 1252 .fb_ioctl = ufx_ops_ioctl, 1253 .fb_open = ufx_ops_open, 1254 .fb_release = ufx_ops_release, 1255 .fb_blank = ufx_ops_blank, 1256 .fb_check_var = ufx_ops_check_var, 1257 .fb_set_par = ufx_ops_set_par, 1258 .fb_destroy = ufx_ops_destory, 1259}; 1260 1261/* Assumes &info->lock held by caller 1262 * Assumes no active clients have framebuffer open */ 1263static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info) 1264{ 1265 int old_len = info->fix.smem_len; 1266 int new_len; 1267 unsigned char *old_fb = info->screen_buffer; 1268 unsigned char *new_fb; 1269 1270 pr_debug("Reallocating framebuffer. Addresses will change!"); 1271 1272 new_len = info->fix.line_length * info->var.yres; 1273 1274 if (PAGE_ALIGN(new_len) > old_len) { 1275 /* 1276 * Alloc system memory for virtual framebuffer 1277 */ 1278 new_fb = vmalloc(new_len); 1279 if (!new_fb) 1280 return -ENOMEM; 1281 1282 if (info->screen_buffer) { 1283 memcpy(new_fb, old_fb, old_len); 1284 vfree(info->screen_buffer); 1285 } 1286 1287 info->screen_buffer = new_fb; 1288 info->fix.smem_len = PAGE_ALIGN(new_len); 1289 info->fix.smem_start = (unsigned long) new_fb; 1290 info->flags = smscufx_info_flags; 1291 } 1292 return 0; 1293} 1294 1295/* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master, 1296 * restart enabled, but no start byte, enable controller */ 1297static int ufx_i2c_init(struct ufx_data *dev) 1298{ 1299 u32 tmp; 1300 1301 /* disable the controller before it can be reprogrammed */ 1302 int status = ufx_reg_write(dev, 0x106C, 0x00); 1303 check_warn_return(status, "failed to disable I2C"); 1304 1305 /* Setup the clock count registers 1306 * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */ 1307 status = ufx_reg_write(dev, 0x1018, 12); 1308 check_warn_return(status, "error writing 0x1018"); 1309 1310 /* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */ 1311 status = ufx_reg_write(dev, 0x1014, 6); 1312 check_warn_return(status, "error writing 0x1014"); 1313 1314 status = ufx_reg_read(dev, 0x1000, &tmp); 1315 check_warn_return(status, "error reading 0x1000"); 1316 1317 /* set speed to std mode */ 1318 tmp &= ~(0x06); 1319 tmp |= 0x02; 1320 1321 /* 7-bit (not 10-bit) addressing */ 1322 tmp &= ~(0x10); 1323 1324 /* enable restart conditions and master mode */ 1325 tmp |= 0x21; 1326 1327 status = ufx_reg_write(dev, 0x1000, tmp); 1328 check_warn_return(status, "error writing 0x1000"); 1329 1330 /* Set normal tx using target address 0 */ 1331 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000); 1332 check_warn_return(status, "error setting TX mode bits in 0x1004"); 1333 1334 /* Enable the controller */ 1335 status = ufx_reg_write(dev, 0x106C, 0x01); 1336 check_warn_return(status, "failed to enable I2C"); 1337 1338 return 0; 1339} 1340 1341/* sets the I2C port mux and target address */ 1342static int ufx_i2c_configure(struct ufx_data *dev) 1343{ 1344 int status = ufx_reg_write(dev, 0x106C, 0x00); 1345 check_warn_return(status, "failed to disable I2C"); 1346 1347 status = ufx_reg_write(dev, 0x3010, 0x00000000); 1348 check_warn_return(status, "failed to write 0x3010"); 1349 1350 /* A0h is std for any EDID, right shifted by one */ 1351 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1)); 1352 check_warn_return(status, "failed to set TAR bits in 0x1004"); 1353 1354 status = ufx_reg_write(dev, 0x106C, 0x01); 1355 check_warn_return(status, "failed to enable I2C"); 1356 1357 return 0; 1358} 1359 1360/* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no 1361 * monitor is connected, there is no error except for timeout */ 1362static int ufx_i2c_wait_busy(struct ufx_data *dev) 1363{ 1364 u32 tmp; 1365 int i, status; 1366 1367 for (i = 0; i < 15; i++) { 1368 status = ufx_reg_read(dev, 0x1100, &tmp); 1369 check_warn_return(status, "0x1100 read failed"); 1370 1371 /* if BUSY is clear, check for error */ 1372 if ((tmp & 0x80000000) == 0) { 1373 if (tmp & 0x20000000) { 1374 pr_warn("I2C read failed, 0x1100=0x%08x", tmp); 1375 return -EIO; 1376 } 1377 1378 return 0; 1379 } 1380 1381 /* perform the first 10 retries without delay */ 1382 if (i >= 10) 1383 msleep(10); 1384 } 1385 1386 pr_warn("I2C access timed out, resetting I2C hardware"); 1387 status = ufx_reg_write(dev, 0x1100, 0x40000000); 1388 check_warn_return(status, "0x1100 write failed"); 1389 1390 return -ETIMEDOUT; 1391} 1392 1393/* reads a 128-byte EDID block from the currently selected port and TAR */ 1394static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len) 1395{ 1396 int i, j, status; 1397 u32 *edid_u32 = (u32 *)edid; 1398 1399 BUG_ON(edid_len != EDID_LENGTH); 1400 1401 status = ufx_i2c_configure(dev); 1402 if (status < 0) { 1403 pr_err("ufx_i2c_configure failed"); 1404 return status; 1405 } 1406 1407 memset(edid, 0xff, EDID_LENGTH); 1408 1409 /* Read the 128-byte EDID as 2 bursts of 64 bytes */ 1410 for (i = 0; i < 2; i++) { 1411 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8); 1412 status = ufx_reg_write(dev, 0x1100, temp); 1413 check_warn_return(status, "Failed to write 0x1100"); 1414 1415 temp |= 0x80000000; 1416 status = ufx_reg_write(dev, 0x1100, temp); 1417 check_warn_return(status, "Failed to write 0x1100"); 1418 1419 status = ufx_i2c_wait_busy(dev); 1420 check_warn_return(status, "Timeout waiting for I2C BUSY to clear"); 1421 1422 for (j = 0; j < 16; j++) { 1423 u32 data_reg_addr = 0x1110 + (j * 4); 1424 status = ufx_reg_read(dev, data_reg_addr, edid_u32++); 1425 check_warn_return(status, "Error reading i2c data"); 1426 } 1427 } 1428 1429 /* all FF's in the first 16 bytes indicates nothing is connected */ 1430 for (i = 0; i < 16; i++) { 1431 if (edid[i] != 0xFF) { 1432 pr_debug("edid data read successfully"); 1433 return EDID_LENGTH; 1434 } 1435 } 1436 1437 pr_warn("edid data contains all 0xff"); 1438 return -ETIMEDOUT; 1439} 1440 1441/* 1) use sw default 1442 * 2) Parse into various fb_info structs 1443 * 3) Allocate virtual framebuffer memory to back highest res mode 1444 * 1445 * Parses EDID into three places used by various parts of fbdev: 1446 * fb_var_screeninfo contains the timing of the monitor's preferred mode 1447 * fb_info.monspecs is full parsed EDID info, including monspecs.modedb 1448 * fb_info.modelist is a linked list of all monitor & VESA modes which work 1449 * 1450 * If EDID is not readable/valid, then modelist is all VESA modes, 1451 * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode 1452 * Returns 0 if successful */ 1453static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info, 1454 char *default_edid, size_t default_edid_size) 1455{ 1456 const struct fb_videomode *default_vmode = NULL; 1457 u8 *edid; 1458 int i, result = 0, tries = 3; 1459 1460 if (refcount_read(&info->count)) /* only use mutex if info has been registered */ 1461 mutex_lock(&info->lock); 1462 1463 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 1464 if (!edid) { 1465 result = -ENOMEM; 1466 goto error; 1467 } 1468 1469 fb_destroy_modelist(&info->modelist); 1470 memset(&info->monspecs, 0, sizeof(info->monspecs)); 1471 1472 /* Try to (re)read EDID from hardware first 1473 * EDID data may return, but not parse as valid 1474 * Try again a few times, in case of e.g. analog cable noise */ 1475 while (tries--) { 1476 i = ufx_read_edid(dev, edid, EDID_LENGTH); 1477 1478 if (i >= EDID_LENGTH) 1479 fb_edid_to_monspecs(edid, &info->monspecs); 1480 1481 if (info->monspecs.modedb_len > 0) { 1482 dev->edid = edid; 1483 dev->edid_size = i; 1484 break; 1485 } 1486 } 1487 1488 /* If that fails, use a previously returned EDID if available */ 1489 if (info->monspecs.modedb_len == 0) { 1490 pr_err("Unable to get valid EDID from device/display\n"); 1491 1492 if (dev->edid) { 1493 fb_edid_to_monspecs(dev->edid, &info->monspecs); 1494 if (info->monspecs.modedb_len > 0) 1495 pr_err("Using previously queried EDID\n"); 1496 } 1497 } 1498 1499 /* If that fails, use the default EDID we were handed */ 1500 if (info->monspecs.modedb_len == 0) { 1501 if (default_edid_size >= EDID_LENGTH) { 1502 fb_edid_to_monspecs(default_edid, &info->monspecs); 1503 if (info->monspecs.modedb_len > 0) { 1504 memcpy(edid, default_edid, default_edid_size); 1505 dev->edid = edid; 1506 dev->edid_size = default_edid_size; 1507 pr_err("Using default/backup EDID\n"); 1508 } 1509 } 1510 } 1511 1512 /* If we've got modes, let's pick a best default mode */ 1513 if (info->monspecs.modedb_len > 0) { 1514 1515 for (i = 0; i < info->monspecs.modedb_len; i++) { 1516 if (ufx_is_valid_mode(&info->monspecs.modedb[i], info)) 1517 fb_add_videomode(&info->monspecs.modedb[i], 1518 &info->modelist); 1519 else /* if we've removed top/best mode */ 1520 info->monspecs.misc &= ~FB_MISC_1ST_DETAIL; 1521 } 1522 1523 default_vmode = fb_find_best_display(&info->monspecs, 1524 &info->modelist); 1525 } 1526 1527 /* If everything else has failed, fall back to safe default mode */ 1528 if (default_vmode == NULL) { 1529 1530 struct fb_videomode fb_vmode = {0}; 1531 1532 /* Add the standard VESA modes to our modelist 1533 * Since we don't have EDID, there may be modes that 1534 * overspec monitor and/or are incorrect aspect ratio, etc. 1535 * But at least the user has a chance to choose 1536 */ 1537 for (i = 0; i < VESA_MODEDB_SIZE; i++) { 1538 if (ufx_is_valid_mode((struct fb_videomode *) 1539 &vesa_modes[i], info)) 1540 fb_add_videomode(&vesa_modes[i], 1541 &info->modelist); 1542 } 1543 1544 /* default to resolution safe for projectors 1545 * (since they are most common case without EDID) 1546 */ 1547 fb_vmode.xres = 800; 1548 fb_vmode.yres = 600; 1549 fb_vmode.refresh = 60; 1550 default_vmode = fb_find_nearest_mode(&fb_vmode, 1551 &info->modelist); 1552 } 1553 1554 /* If we have good mode and no active clients */ 1555 if ((default_vmode != NULL) && (dev->fb_count == 0)) { 1556 1557 fb_videomode_to_var(&info->var, default_vmode); 1558 ufx_var_color_format(&info->var); 1559 1560 /* with mode size info, we can now alloc our framebuffer */ 1561 memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix)); 1562 info->fix.line_length = info->var.xres * 1563 (info->var.bits_per_pixel / 8); 1564 1565 result = ufx_realloc_framebuffer(dev, info); 1566 1567 } else 1568 result = -EINVAL; 1569 1570error: 1571 if (edid && (dev->edid != edid)) 1572 kfree(edid); 1573 1574 if (refcount_read(&info->count)) 1575 mutex_unlock(&info->lock); 1576 1577 return result; 1578} 1579 1580static int ufx_usb_probe(struct usb_interface *interface, 1581 const struct usb_device_id *id) 1582{ 1583 struct usb_device *usbdev; 1584 struct ufx_data *dev; 1585 struct fb_info *info; 1586 int retval = -ENOMEM; 1587 u32 id_rev, fpga_rev; 1588 1589 /* usb initialization */ 1590 usbdev = interface_to_usbdev(interface); 1591 BUG_ON(!usbdev); 1592 1593 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1594 if (dev == NULL) { 1595 dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n"); 1596 return -ENOMEM; 1597 } 1598 1599 /* we need to wait for both usb and fbdev to spin down on disconnect */ 1600 kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */ 1601 kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */ 1602 1603 dev->udev = usbdev; 1604 dev->gdev = &usbdev->dev; /* our generic struct device * */ 1605 usb_set_intfdata(interface, dev); 1606 1607 dev_dbg(dev->gdev, "%s %s - serial #%s\n", 1608 usbdev->manufacturer, usbdev->product, usbdev->serial); 1609 dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n", 1610 le16_to_cpu(usbdev->descriptor.idVendor), 1611 le16_to_cpu(usbdev->descriptor.idProduct), 1612 le16_to_cpu(usbdev->descriptor.bcdDevice), dev); 1613 dev_dbg(dev->gdev, "console enable=%d\n", console); 1614 dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio); 1615 1616 if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) { 1617 dev_err(dev->gdev, "ufx_alloc_urb_list failed\n"); 1618 goto put_ref; 1619 } 1620 1621 /* We don't register a new USB class. Our client interface is fbdev */ 1622 1623 /* allocates framebuffer driver structure, not framebuffer memory */ 1624 info = framebuffer_alloc(0, &usbdev->dev); 1625 if (!info) { 1626 dev_err(dev->gdev, "framebuffer_alloc failed\n"); 1627 goto free_urb_list; 1628 } 1629 1630 dev->info = info; 1631 info->par = dev; 1632 info->pseudo_palette = dev->pseudo_palette; 1633 info->fbops = &ufx_ops; 1634 INIT_LIST_HEAD(&info->modelist); 1635 1636 retval = fb_alloc_cmap(&info->cmap, 256, 0); 1637 if (retval < 0) { 1638 dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval); 1639 goto destroy_modedb; 1640 } 1641 1642 retval = ufx_reg_read(dev, 0x3000, &id_rev); 1643 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval); 1644 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev); 1645 1646 retval = ufx_reg_read(dev, 0x3004, &fpga_rev); 1647 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval); 1648 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev); 1649 1650 dev_dbg(dev->gdev, "resetting device"); 1651 retval = ufx_lite_reset(dev); 1652 check_warn_goto_error(retval, "error %d resetting device", retval); 1653 1654 dev_dbg(dev->gdev, "configuring system clock"); 1655 retval = ufx_config_sys_clk(dev); 1656 check_warn_goto_error(retval, "error %d configuring system clock", retval); 1657 1658 dev_dbg(dev->gdev, "configuring DDR2 controller"); 1659 retval = ufx_config_ddr2(dev); 1660 check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval); 1661 1662 dev_dbg(dev->gdev, "configuring I2C controller"); 1663 retval = ufx_i2c_init(dev); 1664 check_warn_goto_error(retval, "error %d initialising I2C controller", retval); 1665 1666 dev_dbg(dev->gdev, "selecting display mode"); 1667 retval = ufx_setup_modes(dev, info, NULL, 0); 1668 check_warn_goto_error(retval, "unable to find common mode for display and adapter"); 1669 1670 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001); 1671 if (retval < 0) { 1672 dev_err(dev->gdev, "error %d enabling graphics engine", retval); 1673 goto setup_modes; 1674 } 1675 1676 /* ready to begin using device */ 1677 atomic_set(&dev->usb_active, 1); 1678 1679 dev_dbg(dev->gdev, "checking var"); 1680 retval = ufx_ops_check_var(&info->var, info); 1681 if (retval < 0) { 1682 dev_err(dev->gdev, "error %d ufx_ops_check_var", retval); 1683 goto reset_active; 1684 } 1685 1686 dev_dbg(dev->gdev, "setting par"); 1687 retval = ufx_ops_set_par(info); 1688 if (retval < 0) { 1689 dev_err(dev->gdev, "error %d ufx_ops_set_par", retval); 1690 goto reset_active; 1691 } 1692 1693 dev_dbg(dev->gdev, "registering framebuffer"); 1694 retval = register_framebuffer(info); 1695 if (retval < 0) { 1696 dev_err(dev->gdev, "error %d register_framebuffer", retval); 1697 goto reset_active; 1698 } 1699 1700 dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution." 1701 " Using %dK framebuffer memory\n", info->node, 1702 info->var.xres, info->var.yres, info->fix.smem_len >> 10); 1703 1704 return 0; 1705 1706reset_active: 1707 atomic_set(&dev->usb_active, 0); 1708setup_modes: 1709 fb_destroy_modedb(info->monspecs.modedb); 1710 vfree(info->screen_buffer); 1711 fb_destroy_modelist(&info->modelist); 1712error: 1713 fb_dealloc_cmap(&info->cmap); 1714destroy_modedb: 1715 framebuffer_release(info); 1716free_urb_list: 1717 if (dev->urbs.count > 0) 1718 ufx_free_urb_list(dev); 1719put_ref: 1720 kref_put(&dev->kref, ufx_free); /* ref for framebuffer */ 1721 kref_put(&dev->kref, ufx_free); /* last ref from kref_init */ 1722 return retval; 1723} 1724 1725static void ufx_usb_disconnect(struct usb_interface *interface) 1726{ 1727 struct ufx_data *dev; 1728 struct fb_info *info; 1729 1730 mutex_lock(&disconnect_mutex); 1731 1732 dev = usb_get_intfdata(interface); 1733 info = dev->info; 1734 1735 pr_debug("USB disconnect starting\n"); 1736 1737 /* we virtualize until all fb clients release. Then we free */ 1738 dev->virtualized = true; 1739 1740 /* When non-active we'll update virtual framebuffer, but no new urbs */ 1741 atomic_set(&dev->usb_active, 0); 1742 1743 usb_set_intfdata(interface, NULL); 1744 1745 /* if clients still have us open, will be freed on last close */ 1746 if (dev->fb_count == 0) 1747 ufx_free_framebuffer(dev); 1748 1749 /* this function will wait for all in-flight urbs to complete */ 1750 if (dev->urbs.count > 0) 1751 ufx_free_urb_list(dev); 1752 1753 pr_debug("freeing ufx_data %p", dev); 1754 1755 unregister_framebuffer(info); 1756 1757 mutex_unlock(&disconnect_mutex); 1758} 1759 1760static struct usb_driver ufx_driver = { 1761 .name = "smscufx", 1762 .probe = ufx_usb_probe, 1763 .disconnect = ufx_usb_disconnect, 1764 .id_table = id_table, 1765}; 1766 1767module_usb_driver(ufx_driver); 1768 1769static void ufx_urb_completion(struct urb *urb) 1770{ 1771 struct urb_node *unode = urb->context; 1772 struct ufx_data *dev = unode->dev; 1773 unsigned long flags; 1774 1775 /* sync/async unlink faults aren't errors */ 1776 if (urb->status) { 1777 if (!(urb->status == -ENOENT || 1778 urb->status == -ECONNRESET || 1779 urb->status == -ESHUTDOWN)) { 1780 pr_err("%s - nonzero write bulk status received: %d\n", 1781 __func__, urb->status); 1782 atomic_set(&dev->lost_pixels, 1); 1783 } 1784 } 1785 1786 urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */ 1787 1788 spin_lock_irqsave(&dev->urbs.lock, flags); 1789 list_add_tail(&unode->entry, &dev->urbs.list); 1790 dev->urbs.available++; 1791 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1792 1793 /* When using fb_defio, we deadlock if up() is called 1794 * while another is waiting. So queue to another process */ 1795 if (fb_defio) 1796 schedule_delayed_work(&unode->release_urb_work, 0); 1797 else 1798 up(&dev->urbs.limit_sem); 1799} 1800 1801static void ufx_free_urb_list(struct ufx_data *dev) 1802{ 1803 int count = dev->urbs.count; 1804 struct list_head *node; 1805 struct urb_node *unode; 1806 struct urb *urb; 1807 int ret; 1808 unsigned long flags; 1809 1810 pr_debug("Waiting for completes and freeing all render urbs\n"); 1811 1812 /* keep waiting and freeing, until we've got 'em all */ 1813 while (count--) { 1814 /* Getting interrupted means a leak, but ok at shutdown*/ 1815 ret = down_interruptible(&dev->urbs.limit_sem); 1816 if (ret) 1817 break; 1818 1819 spin_lock_irqsave(&dev->urbs.lock, flags); 1820 1821 node = dev->urbs.list.next; /* have reserved one with sem */ 1822 list_del_init(node); 1823 1824 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1825 1826 unode = list_entry(node, struct urb_node, entry); 1827 urb = unode->urb; 1828 1829 /* Free each separately allocated piece */ 1830 usb_free_coherent(urb->dev, dev->urbs.size, 1831 urb->transfer_buffer, urb->transfer_dma); 1832 usb_free_urb(urb); 1833 kfree(node); 1834 } 1835} 1836 1837static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size) 1838{ 1839 int i = 0; 1840 struct urb *urb; 1841 struct urb_node *unode; 1842 char *buf; 1843 1844 spin_lock_init(&dev->urbs.lock); 1845 1846 dev->urbs.size = size; 1847 INIT_LIST_HEAD(&dev->urbs.list); 1848 1849 while (i < count) { 1850 unode = kzalloc(sizeof(*unode), GFP_KERNEL); 1851 if (!unode) 1852 break; 1853 unode->dev = dev; 1854 1855 INIT_DELAYED_WORK(&unode->release_urb_work, 1856 ufx_release_urb_work); 1857 1858 urb = usb_alloc_urb(0, GFP_KERNEL); 1859 if (!urb) { 1860 kfree(unode); 1861 break; 1862 } 1863 unode->urb = urb; 1864 1865 buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL, 1866 &urb->transfer_dma); 1867 if (!buf) { 1868 kfree(unode); 1869 usb_free_urb(urb); 1870 break; 1871 } 1872 1873 /* urb->transfer_buffer_length set to actual before submit */ 1874 usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1), 1875 buf, size, ufx_urb_completion, unode); 1876 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; 1877 1878 list_add_tail(&unode->entry, &dev->urbs.list); 1879 1880 i++; 1881 } 1882 1883 sema_init(&dev->urbs.limit_sem, i); 1884 dev->urbs.count = i; 1885 dev->urbs.available = i; 1886 1887 pr_debug("allocated %d %d byte urbs\n", i, (int) size); 1888 1889 return i; 1890} 1891 1892static struct urb *ufx_get_urb(struct ufx_data *dev) 1893{ 1894 int ret = 0; 1895 struct list_head *entry; 1896 struct urb_node *unode; 1897 struct urb *urb = NULL; 1898 unsigned long flags; 1899 1900 /* Wait for an in-flight buffer to complete and get re-queued */ 1901 ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT); 1902 if (ret) { 1903 atomic_set(&dev->lost_pixels, 1); 1904 pr_warn("wait for urb interrupted: %x available: %d\n", 1905 ret, dev->urbs.available); 1906 goto error; 1907 } 1908 1909 spin_lock_irqsave(&dev->urbs.lock, flags); 1910 1911 BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */ 1912 entry = dev->urbs.list.next; 1913 list_del_init(entry); 1914 dev->urbs.available--; 1915 1916 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1917 1918 unode = list_entry(entry, struct urb_node, entry); 1919 urb = unode->urb; 1920 1921error: 1922 return urb; 1923} 1924 1925static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len) 1926{ 1927 int ret; 1928 1929 BUG_ON(len > dev->urbs.size); 1930 1931 urb->transfer_buffer_length = len; /* set to actual payload len */ 1932 ret = usb_submit_urb(urb, GFP_KERNEL); 1933 if (ret) { 1934 ufx_urb_completion(urb); /* because no one else will */ 1935 atomic_set(&dev->lost_pixels, 1); 1936 pr_err("usb_submit_urb error %x\n", ret); 1937 } 1938 return ret; 1939} 1940 1941module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1942MODULE_PARM_DESC(console, "Allow fbcon to be used on this display"); 1943 1944module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1945MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support"); 1946 1947MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); 1948MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver"); 1949MODULE_LICENSE("GPL"); 1950