1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2023 Advanced Micro Devices, Inc. */ 3 4#ifndef _CMDS_H_ 5#define _CMDS_H_ 6 7int pds_vfio_register_client_cmd(struct pds_vfio_pci_device *pds_vfio); 8void pds_vfio_unregister_client_cmd(struct pds_vfio_pci_device *pds_vfio); 9int pds_vfio_suspend_device_cmd(struct pds_vfio_pci_device *pds_vfio, u8 type); 10int pds_vfio_resume_device_cmd(struct pds_vfio_pci_device *pds_vfio, u8 type); 11int pds_vfio_get_lm_state_size_cmd(struct pds_vfio_pci_device *pds_vfio, u64 *size); 12int pds_vfio_get_lm_state_cmd(struct pds_vfio_pci_device *pds_vfio); 13int pds_vfio_set_lm_state_cmd(struct pds_vfio_pci_device *pds_vfio); 14void pds_vfio_send_host_vf_lm_status_cmd(struct pds_vfio_pci_device *pds_vfio, 15 enum pds_lm_host_vf_status vf_status); 16int pds_vfio_dirty_status_cmd(struct pds_vfio_pci_device *pds_vfio, 17 u64 regions_dma, u8 *max_regions, 18 u8 *num_regions); 19int pds_vfio_dirty_enable_cmd(struct pds_vfio_pci_device *pds_vfio, 20 u64 regions_dma, u8 num_regions); 21int pds_vfio_dirty_disable_cmd(struct pds_vfio_pci_device *pds_vfio); 22int pds_vfio_dirty_seq_ack_cmd(struct pds_vfio_pci_device *pds_vfio, 23 u64 sgl_dma, u16 num_sge, u32 offset, 24 u32 total_len, bool read_seq); 25#endif /* _CMDS_H_ */ 26