1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Driver for the NXP ISP1760 chip 4 * 5 * Copyright 2021 Linaro, Rui Miguel Silva 6 * Copyright 2014 Laurent Pinchart 7 * Copyright 2007 Sebastian Siewior 8 * 9 * Contacts: 10 * Sebastian Siewior <bigeasy@linutronix.de> 11 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 12 * Rui Miguel Silva <rui.silva@linaro.org> 13 */ 14 15#ifndef _ISP176x_REGS_H_ 16#define _ISP176x_REGS_H_ 17 18/* ----------------------------------------------------------------------------- 19 * Host Controller 20 */ 21 22/* ISP1760/31 */ 23/* EHCI capability registers */ 24#define ISP176x_HC_VERSION 0x002 25#define ISP176x_HC_HCSPARAMS 0x004 26#define ISP176x_HC_HCCPARAMS 0x008 27 28/* EHCI operational registers */ 29#define ISP176x_HC_USBCMD 0x020 30#define ISP176x_HC_USBSTS 0x024 31#define ISP176x_HC_FRINDEX 0x02c 32 33#define ISP176x_HC_CONFIGFLAG 0x060 34#define ISP176x_HC_PORTSC1 0x064 35 36#define ISP176x_HC_ISO_PTD_DONEMAP 0x130 37#define ISP176x_HC_ISO_PTD_SKIPMAP 0x134 38#define ISP176x_HC_ISO_PTD_LASTPTD 0x138 39#define ISP176x_HC_INT_PTD_DONEMAP 0x140 40#define ISP176x_HC_INT_PTD_SKIPMAP 0x144 41#define ISP176x_HC_INT_PTD_LASTPTD 0x148 42#define ISP176x_HC_ATL_PTD_DONEMAP 0x150 43#define ISP176x_HC_ATL_PTD_SKIPMAP 0x154 44#define ISP176x_HC_ATL_PTD_LASTPTD 0x158 45 46/* Configuration Register */ 47#define ISP176x_HC_HW_MODE_CTRL 0x300 48#define ISP176x_HC_CHIP_ID 0x304 49#define ISP176x_HC_SCRATCH 0x308 50#define ISP176x_HC_RESET 0x30c 51#define ISP176x_HC_BUFFER_STATUS 0x334 52#define ISP176x_HC_MEMORY 0x33c 53 54/* Interrupt Register */ 55#define ISP176x_HC_INTERRUPT 0x310 56#define ISP176x_HC_INTERRUPT_ENABLE 0x314 57#define ISP176x_HC_ISO_IRQ_MASK_OR 0x318 58#define ISP176x_HC_INT_IRQ_MASK_OR 0x31c 59#define ISP176x_HC_ATL_IRQ_MASK_OR 0x320 60#define ISP176x_HC_ISO_IRQ_MASK_AND 0x324 61#define ISP176x_HC_INT_IRQ_MASK_AND 0x328 62#define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c 63 64#define ISP176x_HC_OTG_CTRL 0x374 65#define ISP176x_HC_OTG_CTRL_SET 0x374 66#define ISP176x_HC_OTG_CTRL_CLEAR 0x376 67 68enum isp176x_host_controller_fields { 69 /* HC_PORTSC1 */ 70 PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, 71 PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, 72 /* HC_HCSPARAMS */ 73 HCS_PPC, HCS_N_PORTS, 74 /* HC_HCCPARAMS */ 75 HCC_ISOC_CACHE, HCC_ISOC_THRES, 76 /* HC_USBCMD */ 77 CMD_LRESET, CMD_RESET, CMD_RUN, 78 /* HC_USBSTS */ 79 STS_PCD, 80 /* HC_FRINDEX */ 81 HC_FRINDEX, 82 /* HC_CONFIGFLAG */ 83 FLAG_CF, 84 /* ISO/INT/ATL PTD */ 85 HC_ISO_PTD_DONEMAP, HC_ISO_PTD_SKIPMAP, HC_ISO_PTD_LASTPTD, 86 HC_INT_PTD_DONEMAP, HC_INT_PTD_SKIPMAP, HC_INT_PTD_LASTPTD, 87 HC_ATL_PTD_DONEMAP, HC_ATL_PTD_SKIPMAP, HC_ATL_PTD_LASTPTD, 88 /* HC_HW_MODE_CTRL */ 89 ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA, 90 HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT, 91 HW_INTF_LOCK, HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, 92 /* HC_CHIP_ID */ 93 HC_CHIP_ID_HIGH, HC_CHIP_ID_LOW, HC_CHIP_REV, 94 /* HC_SCRATCH */ 95 HC_SCRATCH, 96 /* HC_RESET */ 97 SW_RESET_RESET_ATX, SW_RESET_RESET_HC, SW_RESET_RESET_ALL, 98 /* HC_BUFFER_STATUS */ 99 ISO_BUF_FILL, INT_BUF_FILL, ATL_BUF_FILL, 100 /* HC_MEMORY */ 101 MEM_BANK_SEL, MEM_START_ADDR, 102 /* HC_DATA */ 103 HC_DATA, 104 /* HC_INTERRUPT */ 105 HC_INTERRUPT, 106 /* HC_INTERRUPT_ENABLE */ 107 HC_INT_IRQ_ENABLE, HC_ATL_IRQ_ENABLE, 108 /* INTERRUPT MASKS */ 109 HC_ISO_IRQ_MASK_OR, HC_INT_IRQ_MASK_OR, HC_ATL_IRQ_MASK_OR, 110 HC_ISO_IRQ_MASK_AND, HC_INT_IRQ_MASK_AND, HC_ATL_IRQ_MASK_AND, 111 /* HW_OTG_CTRL_SET */ 112 HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, 113 HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, HW_HC_2_DIS, 114 /* HW_OTG_CTRL_CLR */ 115 HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, 116 HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, 117 HW_DP_PULLUP_CLEAR, HW_HC_2_DIS_CLEAR, 118 /* Last element */ 119 HC_FIELD_MAX, 120}; 121 122/* ISP1763 */ 123/* EHCI operational registers */ 124#define ISP1763_HC_USBCMD 0x8c 125#define ISP1763_HC_USBSTS 0x90 126#define ISP1763_HC_FRINDEX 0x98 127 128#define ISP1763_HC_CONFIGFLAG 0x9c 129#define ISP1763_HC_PORTSC1 0xa0 130 131#define ISP1763_HC_ISO_PTD_DONEMAP 0xa4 132#define ISP1763_HC_ISO_PTD_SKIPMAP 0xa6 133#define ISP1763_HC_ISO_PTD_LASTPTD 0xa8 134#define ISP1763_HC_INT_PTD_DONEMAP 0xaa 135#define ISP1763_HC_INT_PTD_SKIPMAP 0xac 136#define ISP1763_HC_INT_PTD_LASTPTD 0xae 137#define ISP1763_HC_ATL_PTD_DONEMAP 0xb0 138#define ISP1763_HC_ATL_PTD_SKIPMAP 0xb2 139#define ISP1763_HC_ATL_PTD_LASTPTD 0xb4 140 141/* Configuration Register */ 142#define ISP1763_HC_HW_MODE_CTRL 0xb6 143#define ISP1763_HC_CHIP_REV 0x70 144#define ISP1763_HC_CHIP_ID 0x72 145#define ISP1763_HC_SCRATCH 0x78 146#define ISP1763_HC_RESET 0xb8 147#define ISP1763_HC_BUFFER_STATUS 0xba 148#define ISP1763_HC_MEMORY 0xc4 149#define ISP1763_HC_DATA 0xc6 150 151/* Interrupt Register */ 152#define ISP1763_HC_INTERRUPT 0xd4 153#define ISP1763_HC_INTERRUPT_ENABLE 0xd6 154#define ISP1763_HC_ISO_IRQ_MASK_OR 0xd8 155#define ISP1763_HC_INT_IRQ_MASK_OR 0xda 156#define ISP1763_HC_ATL_IRQ_MASK_OR 0xdc 157#define ISP1763_HC_ISO_IRQ_MASK_AND 0xde 158#define ISP1763_HC_INT_IRQ_MASK_AND 0xe0 159#define ISP1763_HC_ATL_IRQ_MASK_AND 0xe2 160 161#define ISP1763_HC_OTG_CTRL_SET 0xe4 162#define ISP1763_HC_OTG_CTRL_CLEAR 0xe6 163 164/* ----------------------------------------------------------------------------- 165 * Peripheral Controller 166 */ 167 168#define DC_IEPTX(n) (1 << (11 + 2 * (n))) 169#define DC_IEPRX(n) (1 << (10 + 2 * (n))) 170#define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) 171 172#define ISP176x_DC_CDBGMOD_ACK BIT(6) 173#define ISP176x_DC_DDBGMODIN_ACK BIT(4) 174#define ISP176x_DC_DDBGMODOUT_ACK BIT(2) 175 176#define ISP176x_DC_IEP0SETUP BIT(8) 177#define ISP176x_DC_IEVBUS BIT(7) 178#define ISP176x_DC_IEHS_STA BIT(5) 179#define ISP176x_DC_IERESM BIT(4) 180#define ISP176x_DC_IESUSP BIT(3) 181#define ISP176x_DC_IEBRST BIT(0) 182 183#define ISP176x_HW_OTG_DISABLE_CLEAR BIT(26) 184#define ISP176x_HW_SW_SEL_HC_DC_CLEAR BIT(23) 185#define ISP176x_HW_VBUS_DRV_CLEAR BIT(20) 186#define ISP176x_HW_SEL_CP_EXT_CLEAR BIT(19) 187#define ISP176x_HW_DM_PULLDOWN_CLEAR BIT(18) 188#define ISP176x_HW_DP_PULLDOWN_CLEAR BIT(17) 189#define ISP176x_HW_DP_PULLUP_CLEAR BIT(16) 190#define ISP176x_HW_OTG_DISABLE BIT(10) 191#define ISP176x_HW_SW_SEL_HC_DC BIT(7) 192#define ISP176x_HW_VBUS_DRV BIT(4) 193#define ISP176x_HW_SEL_CP_EXT BIT(3) 194#define ISP176x_HW_DM_PULLDOWN BIT(2) 195#define ISP176x_HW_DP_PULLDOWN BIT(1) 196#define ISP176x_HW_DP_PULLUP BIT(0) 197 198#define ISP176x_DC_ENDPTYP_ISOC 0x01 199#define ISP176x_DC_ENDPTYP_BULK 0x02 200#define ISP176x_DC_ENDPTYP_INTERRUPT 0x03 201 202/* Initialization Registers */ 203#define ISP176x_DC_ADDRESS 0x0200 204#define ISP176x_DC_MODE 0x020c 205#define ISP176x_DC_INTCONF 0x0210 206#define ISP176x_DC_DEBUG 0x0212 207#define ISP176x_DC_INTENABLE 0x0214 208 209/* Data Flow Registers */ 210#define ISP176x_DC_EPMAXPKTSZ 0x0204 211#define ISP176x_DC_EPTYPE 0x0208 212 213#define ISP176x_DC_BUFLEN 0x021c 214#define ISP176x_DC_BUFSTAT 0x021e 215#define ISP176x_DC_DATAPORT 0x0220 216 217#define ISP176x_DC_CTRLFUNC 0x0228 218#define ISP176x_DC_EPINDEX 0x022c 219 220/* DMA Registers */ 221#define ISP176x_DC_DMACMD 0x0230 222#define ISP176x_DC_DMATXCOUNT 0x0234 223#define ISP176x_DC_DMACONF 0x0238 224#define ISP176x_DC_DMAHW 0x023c 225#define ISP176x_DC_DMAINTREASON 0x0250 226#define ISP176x_DC_DMAINTEN 0x0254 227#define ISP176x_DC_DMAEP 0x0258 228#define ISP176x_DC_DMABURSTCOUNT 0x0264 229 230/* General Registers */ 231#define ISP176x_DC_INTERRUPT 0x0218 232#define ISP176x_DC_CHIPID 0x0270 233#define ISP176x_DC_FRAMENUM 0x0274 234#define ISP176x_DC_SCRATCH 0x0278 235#define ISP176x_DC_UNLOCKDEV 0x027c 236#define ISP176x_DC_INTPULSEWIDTH 0x0280 237#define ISP176x_DC_TESTMODE 0x0284 238 239enum isp176x_device_controller_fields { 240 /* DC_ADDRESS */ 241 DC_DEVEN, DC_DEVADDR, 242 /* DC_MODE */ 243 DC_VBUSSTAT, DC_SFRESET, DC_GLINTENA, 244 /* DC_INTCONF */ 245 DC_CDBGMOD_ACK, DC_DDBGMODIN_ACK, DC_DDBGMODOUT_ACK, DC_INTPOL, 246 /* DC_INTENABLE */ 247 DC_IEPRXTX_7, DC_IEPRXTX_6, DC_IEPRXTX_5, DC_IEPRXTX_4, DC_IEPRXTX_3, 248 DC_IEPRXTX_2, DC_IEPRXTX_1, DC_IEPRXTX_0, 249 DC_IEP0SETUP, DC_IEVBUS, DC_IEHS_STA, DC_IERESM, DC_IESUSP, DC_IEBRST, 250 /* DC_EPINDEX */ 251 DC_EP0SETUP, DC_ENDPIDX, DC_EPDIR, 252 /* DC_CTRLFUNC */ 253 DC_CLBUF, DC_VENDP, DC_DSEN, DC_STATUS, DC_STALL, 254 /* DC_BUFLEN */ 255 DC_BUFLEN, 256 /* DC_EPMAXPKTSZ */ 257 DC_FFOSZ, 258 /* DC_EPTYPE */ 259 DC_EPENABLE, DC_ENDPTYP, 260 /* DC_FRAMENUM */ 261 DC_FRAMENUM, DC_UFRAMENUM, 262 /* DC_CHIP_ID */ 263 DC_CHIP_ID_HIGH, DC_CHIP_ID_LOW, 264 /* DC_SCRATCH */ 265 DC_SCRATCH, 266 /* Last element */ 267 DC_FIELD_MAX, 268}; 269 270/* ISP1763 */ 271/* Initialization Registers */ 272#define ISP1763_DC_ADDRESS 0x00 273#define ISP1763_DC_MODE 0x0c 274#define ISP1763_DC_INTCONF 0x10 275#define ISP1763_DC_INTENABLE 0x14 276 277/* Data Flow Registers */ 278#define ISP1763_DC_EPMAXPKTSZ 0x04 279#define ISP1763_DC_EPTYPE 0x08 280 281#define ISP1763_DC_BUFLEN 0x1c 282#define ISP1763_DC_BUFSTAT 0x1e 283#define ISP1763_DC_DATAPORT 0x20 284 285#define ISP1763_DC_CTRLFUNC 0x28 286#define ISP1763_DC_EPINDEX 0x2c 287 288/* DMA Registers */ 289#define ISP1763_DC_DMACMD 0x30 290#define ISP1763_DC_DMATXCOUNT 0x34 291#define ISP1763_DC_DMACONF 0x38 292#define ISP1763_DC_DMAHW 0x3c 293#define ISP1763_DC_DMAINTREASON 0x50 294#define ISP1763_DC_DMAINTEN 0x54 295#define ISP1763_DC_DMAEP 0x58 296#define ISP1763_DC_DMABURSTCOUNT 0x64 297 298/* General Registers */ 299#define ISP1763_DC_INTERRUPT 0x18 300#define ISP1763_DC_CHIPID_LOW 0x70 301#define ISP1763_DC_CHIPID_HIGH 0x72 302#define ISP1763_DC_FRAMENUM 0x74 303#define ISP1763_DC_SCRATCH 0x78 304#define ISP1763_DC_UNLOCKDEV 0x7c 305#define ISP1763_DC_INTPULSEWIDTH 0x80 306#define ISP1763_DC_TESTMODE 0x84 307 308#endif 309