1// SPDX-License-Identifier: GPL-2.0 2/* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11#include <linux/pci.h> 12#include <linux/slab.h> 13#include <linux/module.h> 14#include <linux/acpi.h> 15#include <linux/reset.h> 16#include <linux/suspend.h> 17 18#include "xhci.h" 19#include "xhci-trace.h" 20#include "xhci-pci.h" 21 22#define SSIC_PORT_NUM 2 23#define SSIC_PORT_CFG2 0x880c 24#define SSIC_PORT_CFG2_OFFSET 0x30 25#define PROG_DONE (1 << 30) 26#define SSIC_PORT_UNUSED (1 << 31) 27#define SPARSE_DISABLE_BIT 17 28#define SPARSE_CNTL_ENABLE 0xC12C 29 30/* Device for a quirk */ 31#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37#define PCI_VENDOR_ID_ETRON 0x1b6f 38#define PCI_DEVICE_ID_EJ168 0x7023 39 40#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 41#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 42#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 43#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 44#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 45#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 46#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 47#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 48#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 49#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 50#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 51#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 52#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 53#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 54#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 55#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 56#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 57#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 58#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 59#define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 60#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 61#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 62#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 63#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 64 65#define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 66#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 67#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 68#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 69#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 70 71#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 72#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 73#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 74#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 75#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 76 77static const char hcd_name[] = "xhci_hcd"; 78 79static struct hc_driver __read_mostly xhci_pci_hc_driver; 80 81static int xhci_pci_setup(struct usb_hcd *hcd); 82static int xhci_pci_run(struct usb_hcd *hcd); 83static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 84 struct usb_tt *tt, gfp_t mem_flags); 85 86static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 87 .reset = xhci_pci_setup, 88 .start = xhci_pci_run, 89 .update_hub_device = xhci_pci_update_hub_device, 90}; 91 92static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 93{ 94 struct usb_hcd *hcd = xhci_to_hcd(xhci); 95 96 if (hcd->msix_enabled) { 97 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 98 99 /* for now, the driver only supports one primary interrupter */ 100 synchronize_irq(pci_irq_vector(pdev, 0)); 101 } 102} 103 104/* Free any IRQs and disable MSI-X */ 105static void xhci_cleanup_msix(struct xhci_hcd *xhci) 106{ 107 struct usb_hcd *hcd = xhci_to_hcd(xhci); 108 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 109 110 /* return if using legacy interrupt */ 111 if (hcd->irq > 0) 112 return; 113 114 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 115 pci_free_irq_vectors(pdev); 116 hcd->msix_enabled = 0; 117} 118 119/* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 120static int xhci_try_enable_msi(struct usb_hcd *hcd) 121{ 122 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 123 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 124 int ret; 125 126 /* 127 * Some Fresco Logic host controllers advertise MSI, but fail to 128 * generate interrupts. Don't even try to enable MSI. 129 */ 130 if (xhci->quirks & XHCI_BROKEN_MSI) 131 goto legacy_irq; 132 133 /* unregister the legacy interrupt */ 134 if (hcd->irq) 135 free_irq(hcd->irq, hcd); 136 hcd->irq = 0; 137 138 /* 139 * calculate number of MSI-X vectors supported. 140 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 141 * with max number of interrupters based on the xhci HCSPARAMS1. 142 * - num_online_cpus: maximum MSI-X vectors per CPUs core. 143 * Add additional 1 vector to ensure always available interrupt. 144 */ 145 xhci->nvecs = min(num_online_cpus() + 1, 146 HCS_MAX_INTRS(xhci->hcs_params1)); 147 148 /* TODO: Check with MSI Soc for sysdev */ 149 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 150 PCI_IRQ_MSIX | PCI_IRQ_MSI); 151 if (xhci->nvecs < 0) { 152 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 153 "failed to allocate IRQ vectors"); 154 goto legacy_irq; 155 } 156 157 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 158 xhci_to_hcd(xhci)); 159 if (ret) 160 goto free_irq_vectors; 161 162 hcd->msi_enabled = 1; 163 hcd->msix_enabled = pdev->msix_enabled; 164 return 0; 165 166free_irq_vectors: 167 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 168 pdev->msix_enabled ? "MSI-X" : "MSI"); 169 pci_free_irq_vectors(pdev); 170 171legacy_irq: 172 if (!pdev->irq) { 173 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 174 return -EINVAL; 175 } 176 177 if (!strlen(hcd->irq_descr)) 178 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 179 hcd->driver->description, hcd->self.busnum); 180 181 /* fall back to legacy interrupt */ 182 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 183 if (ret) { 184 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 185 return ret; 186 } 187 hcd->irq = pdev->irq; 188 return 0; 189} 190 191static int xhci_pci_run(struct usb_hcd *hcd) 192{ 193 int ret; 194 195 if (usb_hcd_is_primary_hcd(hcd)) { 196 ret = xhci_try_enable_msi(hcd); 197 if (ret) 198 return ret; 199 } 200 201 return xhci_run(hcd); 202} 203 204static void xhci_pci_stop(struct usb_hcd *hcd) 205{ 206 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 207 208 xhci_stop(hcd); 209 210 if (usb_hcd_is_primary_hcd(hcd)) 211 xhci_cleanup_msix(xhci); 212} 213 214/* called after powerup, by probe or system-pm "wakeup" */ 215static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 216{ 217 /* 218 * TODO: Implement finding debug ports later. 219 * TODO: see if there are any quirks that need to be added to handle 220 * new extended capabilities. 221 */ 222 223 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 224 if (!pci_set_mwi(pdev)) 225 xhci_dbg(xhci, "MWI active\n"); 226 227 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 228 return 0; 229} 230 231static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 232{ 233 struct pci_dev *pdev = to_pci_dev(dev); 234 struct xhci_driver_data *driver_data; 235 const struct pci_device_id *id; 236 237 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 238 239 if (id && id->driver_data) { 240 driver_data = (struct xhci_driver_data *)id->driver_data; 241 xhci->quirks |= driver_data->quirks; 242 } 243 244 /* Look for vendor-specific quirks */ 245 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 246 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 247 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 248 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 249 pdev->revision == 0x0) { 250 xhci->quirks |= XHCI_RESET_EP_QUIRK; 251 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 252 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 253 } 254 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 255 pdev->revision == 0x4) { 256 xhci->quirks |= XHCI_SLOW_SUSPEND; 257 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 258 "QUIRK: Fresco Logic xHC revision %u" 259 "must be suspended extra slowly", 260 pdev->revision); 261 } 262 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 263 xhci->quirks |= XHCI_BROKEN_STREAMS; 264 /* Fresco Logic confirms: all revisions of this chip do not 265 * support MSI, even though some of them claim to in their PCI 266 * capabilities. 267 */ 268 xhci->quirks |= XHCI_BROKEN_MSI; 269 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 270 "QUIRK: Fresco Logic revision %u " 271 "has broken MSI implementation", 272 pdev->revision); 273 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 274 } 275 276 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 277 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 278 xhci->quirks |= XHCI_BROKEN_STREAMS; 279 280 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 281 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 282 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 283 284 if (pdev->vendor == PCI_VENDOR_ID_NEC) 285 xhci->quirks |= XHCI_NEC_HOST; 286 287 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 288 xhci->quirks |= XHCI_AMD_0x96_HOST; 289 290 /* AMD PLL quirk */ 291 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 292 xhci->quirks |= XHCI_AMD_PLL_FIX; 293 294 if (pdev->vendor == PCI_VENDOR_ID_AMD && 295 (pdev->device == 0x145c || 296 pdev->device == 0x15e0 || 297 pdev->device == 0x15e1 || 298 pdev->device == 0x43bb)) 299 xhci->quirks |= XHCI_SUSPEND_DELAY; 300 301 if (pdev->vendor == PCI_VENDOR_ID_AMD && 302 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 303 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 304 305 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 306 xhci->quirks |= XHCI_DISABLE_SPARSE; 307 xhci->quirks |= XHCI_RESET_ON_RESUME; 308 } 309 310 if (pdev->vendor == PCI_VENDOR_ID_AMD) { 311 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 312 if (pdev->device == 0x43f7) 313 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 314 } 315 316 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 317 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 318 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 319 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 320 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 321 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 322 323 if (pdev->vendor == PCI_VENDOR_ID_AMD && 324 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 325 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 326 327 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 328 xhci->quirks |= XHCI_LPM_SUPPORT; 329 xhci->quirks |= XHCI_INTEL_HOST; 330 xhci->quirks |= XHCI_AVOID_BEI; 331 } 332 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 333 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 334 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 335 xhci->limit_active_eps = 64; 336 xhci->quirks |= XHCI_SW_BW_CHECKING; 337 /* 338 * PPT desktop boards DH77EB and DH77DF will power back on after 339 * a few seconds of being shutdown. The fix for this is to 340 * switch the ports from xHCI to EHCI on shutdown. We can't use 341 * DMI information to find those particular boards (since each 342 * vendor will change the board name), so we have to key off all 343 * PPT chipsets. 344 */ 345 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 346 } 347 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 348 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 349 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 350 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 351 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 352 } 353 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 354 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 355 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 356 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 357 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 358 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 359 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 360 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 361 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 362 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 363 } 364 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 365 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 366 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 367 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 368 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 369 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 370 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 371 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 372 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 373 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 374 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 375 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 376 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 377 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 378 xhci->quirks |= XHCI_MISSING_CAS; 379 380 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 381 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 382 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 383 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 384 385 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 386 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 387 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 388 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 389 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 390 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 391 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 392 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 393 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 394 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 395 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 396 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 397 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 398 399 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 400 pdev->device == PCI_DEVICE_ID_EJ168) { 401 xhci->quirks |= XHCI_RESET_ON_RESUME; 402 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 403 xhci->quirks |= XHCI_BROKEN_STREAMS; 404 } 405 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 406 pdev->device == 0x0014) { 407 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 408 xhci->quirks |= XHCI_ZERO_64B_REGS; 409 } 410 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 411 pdev->device == 0x0015) { 412 xhci->quirks |= XHCI_RESET_ON_RESUME; 413 xhci->quirks |= XHCI_ZERO_64B_REGS; 414 } 415 if (pdev->vendor == PCI_VENDOR_ID_VIA) 416 xhci->quirks |= XHCI_RESET_ON_RESUME; 417 418 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 419 if (pdev->vendor == PCI_VENDOR_ID_VIA && 420 pdev->device == 0x3432) 421 xhci->quirks |= XHCI_BROKEN_STREAMS; 422 423 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 424 xhci->quirks |= XHCI_LPM_SUPPORT; 425 426 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 427 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 428 /* 429 * try to tame the ASMedia 1042 controller which reports 0.96 430 * but appears to behave more like 1.0 431 */ 432 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 433 xhci->quirks |= XHCI_BROKEN_STREAMS; 434 } 435 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 436 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 437 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 438 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 439 } 440 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 441 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 442 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 443 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 444 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 445 446 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 447 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 448 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 449 450 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 451 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 452 453 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 454 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 455 pdev->device == 0x9026) 456 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 457 458 if (pdev->vendor == PCI_VENDOR_ID_AMD && 459 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 460 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 461 xhci->quirks |= XHCI_NO_SOFT_RETRY; 462 463 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 464 xhci->quirks |= XHCI_ZHAOXIN_HOST; 465 xhci->quirks |= XHCI_LPM_SUPPORT; 466 467 if (pdev->device == 0x9202) { 468 xhci->quirks |= XHCI_RESET_ON_RESUME; 469 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 470 } 471 472 if (pdev->device == 0x9203) 473 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 474 } 475 476 /* xHC spec requires PCI devices to support D3hot and D3cold */ 477 if (xhci->hci_version >= 0x120) 478 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 479 480 if (xhci->quirks & XHCI_RESET_ON_RESUME) 481 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 482 "QUIRK: Resetting on resume"); 483} 484 485#ifdef CONFIG_ACPI 486static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 487{ 488 static const guid_t intel_dsm_guid = 489 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 490 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 491 union acpi_object *obj; 492 493 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 494 NULL); 495 ACPI_FREE(obj); 496} 497 498static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 499{ 500 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 501 struct xhci_hub *rhub = &xhci->usb3_rhub; 502 int ret; 503 int i; 504 505 /* This is not the usb3 roothub we are looking for */ 506 if (hcd != rhub->hcd) 507 return; 508 509 if (hdev->maxchild > rhub->num_ports) { 510 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 511 return; 512 } 513 514 for (i = 0; i < hdev->maxchild; i++) { 515 ret = usb_acpi_port_lpm_incapable(hdev, i); 516 517 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 518 519 if (ret >= 0) { 520 rhub->ports[i]->lpm_incapable = ret; 521 continue; 522 } 523 } 524} 525 526#else 527static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 528static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 529#endif /* CONFIG_ACPI */ 530 531/* called during probe() after chip reset completes */ 532static int xhci_pci_setup(struct usb_hcd *hcd) 533{ 534 struct xhci_hcd *xhci; 535 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 536 int retval; 537 538 xhci = hcd_to_xhci(hcd); 539 if (!xhci->sbrn) 540 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 541 542 /* imod_interval is the interrupt moderation value in nanoseconds. */ 543 xhci->imod_interval = 40000; 544 545 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 546 if (retval) 547 return retval; 548 549 if (!usb_hcd_is_primary_hcd(hcd)) 550 return 0; 551 552 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 553 xhci_pme_acpi_rtd3_enable(pdev); 554 555 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 556 557 /* Find any debug ports */ 558 return xhci_pci_reinit(xhci, pdev); 559} 560 561static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 562 struct usb_tt *tt, gfp_t mem_flags) 563{ 564 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 565 if (!hdev->parent) 566 xhci_find_lpm_incapable_ports(hcd, hdev); 567 568 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 569} 570 571/* 572 * We need to register our own PCI probe function (instead of the USB core's 573 * function) in order to create a second roothub under xHCI. 574 */ 575static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 576{ 577 int retval; 578 struct xhci_hcd *xhci; 579 struct usb_hcd *hcd; 580 struct xhci_driver_data *driver_data; 581 struct reset_control *reset; 582 583 driver_data = (struct xhci_driver_data *)id->driver_data; 584 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 585 retval = renesas_xhci_check_request_fw(dev, id); 586 if (retval) 587 return retval; 588 } 589 590 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 591 if (IS_ERR(reset)) 592 return PTR_ERR(reset); 593 reset_control_reset(reset); 594 595 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 596 pm_runtime_get_noresume(&dev->dev); 597 598 /* Register the USB 2.0 roothub. 599 * FIXME: USB core must know to register the USB 2.0 roothub first. 600 * This is sort of silly, because we could just set the HCD driver flags 601 * to say USB 2.0, but I'm not sure what the implications would be in 602 * the other parts of the HCD code. 603 */ 604 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 605 606 if (retval) 607 goto put_runtime_pm; 608 609 /* USB 2.0 roothub is stored in the PCI device now. */ 610 hcd = dev_get_drvdata(&dev->dev); 611 xhci = hcd_to_xhci(hcd); 612 xhci->reset = reset; 613 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 614 pci_name(dev), hcd); 615 if (!xhci->shared_hcd) { 616 retval = -ENOMEM; 617 goto dealloc_usb2_hcd; 618 } 619 620 retval = xhci_ext_cap_init(xhci); 621 if (retval) 622 goto put_usb3_hcd; 623 624 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 625 IRQF_SHARED); 626 if (retval) 627 goto put_usb3_hcd; 628 /* Roothub already marked as USB 3.0 speed */ 629 630 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 631 HCC_MAX_PSA(xhci->hcc_params) >= 4) 632 xhci->shared_hcd->can_do_streams = 1; 633 634 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 635 pm_runtime_put_noidle(&dev->dev); 636 637 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 638 pm_runtime_forbid(&dev->dev); 639 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 640 pm_runtime_allow(&dev->dev); 641 642 dma_set_max_seg_size(&dev->dev, UINT_MAX); 643 644 return 0; 645 646put_usb3_hcd: 647 usb_put_hcd(xhci->shared_hcd); 648dealloc_usb2_hcd: 649 usb_hcd_pci_remove(dev); 650put_runtime_pm: 651 pm_runtime_put_noidle(&dev->dev); 652 return retval; 653} 654 655static void xhci_pci_remove(struct pci_dev *dev) 656{ 657 struct xhci_hcd *xhci; 658 659 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 660 661 xhci->xhc_state |= XHCI_STATE_REMOVING; 662 663 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 664 pm_runtime_forbid(&dev->dev); 665 666 if (xhci->shared_hcd) { 667 usb_remove_hcd(xhci->shared_hcd); 668 usb_put_hcd(xhci->shared_hcd); 669 xhci->shared_hcd = NULL; 670 } 671 672 /* Workaround for spurious wakeups at shutdown with HSW */ 673 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 674 pci_set_power_state(dev, PCI_D3hot); 675 676 usb_hcd_pci_remove(dev); 677} 678 679/* 680 * In some Intel xHCI controllers, in order to get D3 working, 681 * through a vendor specific SSIC CONFIG register at offset 0x883c, 682 * SSIC PORT need to be marked as "unused" before putting xHCI 683 * into D3. After D3 exit, the SSIC port need to be marked as "used". 684 * Without this change, xHCI might not enter D3 state. 685 */ 686static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 687{ 688 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 689 u32 val; 690 void __iomem *reg; 691 int i; 692 693 for (i = 0; i < SSIC_PORT_NUM; i++) { 694 reg = (void __iomem *) xhci->cap_regs + 695 SSIC_PORT_CFG2 + 696 i * SSIC_PORT_CFG2_OFFSET; 697 698 /* Notify SSIC that SSIC profile programming is not done. */ 699 val = readl(reg) & ~PROG_DONE; 700 writel(val, reg); 701 702 /* Mark SSIC port as unused(suspend) or used(resume) */ 703 val = readl(reg); 704 if (suspend) 705 val |= SSIC_PORT_UNUSED; 706 else 707 val &= ~SSIC_PORT_UNUSED; 708 writel(val, reg); 709 710 /* Notify SSIC that SSIC profile programming is done */ 711 val = readl(reg) | PROG_DONE; 712 writel(val, reg); 713 readl(reg); 714 } 715} 716 717/* 718 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 719 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 720 */ 721static void xhci_pme_quirk(struct usb_hcd *hcd) 722{ 723 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 724 void __iomem *reg; 725 u32 val; 726 727 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 728 val = readl(reg); 729 writel(val | BIT(28), reg); 730 readl(reg); 731} 732 733static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 734{ 735 u32 reg; 736 737 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 738 reg &= ~BIT(SPARSE_DISABLE_BIT); 739 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 740} 741 742static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 743{ 744 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 745 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 746 int ret; 747 748 /* 749 * Systems with the TI redriver that loses port status change events 750 * need to have the registers polled during D3, so avoid D3cold. 751 */ 752 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 753 pci_d3cold_disable(pdev); 754 755#ifdef CONFIG_SUSPEND 756 /* d3cold is broken, but only when s2idle is used */ 757 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 758 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 759 pci_d3cold_disable(pdev); 760#endif 761 762 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 763 xhci_pme_quirk(hcd); 764 765 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 766 xhci_ssic_port_unused_quirk(hcd, true); 767 768 if (xhci->quirks & XHCI_DISABLE_SPARSE) 769 xhci_sparse_control_quirk(hcd); 770 771 ret = xhci_suspend(xhci, do_wakeup); 772 773 /* synchronize irq when using MSI-X */ 774 xhci_msix_sync_irqs(xhci); 775 776 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 777 xhci_ssic_port_unused_quirk(hcd, false); 778 779 return ret; 780} 781 782static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 783{ 784 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 785 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 786 int retval = 0; 787 788 reset_control_reset(xhci->reset); 789 790 /* The BIOS on systems with the Intel Panther Point chipset may or may 791 * not support xHCI natively. That means that during system resume, it 792 * may switch the ports back to EHCI so that users can use their 793 * keyboard to select a kernel from GRUB after resume from hibernate. 794 * 795 * The BIOS is supposed to remember whether the OS had xHCI ports 796 * enabled before resume, and switch the ports back to xHCI when the 797 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 798 * writers. 799 * 800 * Unconditionally switch the ports back to xHCI after a system resume. 801 * It should not matter whether the EHCI or xHCI controller is 802 * resumed first. It's enough to do the switchover in xHCI because 803 * USB core won't notice anything as the hub driver doesn't start 804 * running again until after all the devices (including both EHCI and 805 * xHCI host controllers) have been resumed. 806 */ 807 808 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 809 usb_enable_intel_xhci_ports(pdev); 810 811 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 812 xhci_ssic_port_unused_quirk(hcd, false); 813 814 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 815 xhci_pme_quirk(hcd); 816 817 retval = xhci_resume(xhci, msg); 818 return retval; 819} 820 821static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 822{ 823 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 824 struct xhci_port *port; 825 struct usb_device *udev; 826 u32 portsc; 827 int i; 828 829 /* 830 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 831 * cause significant boot delay if usb ports are in suspended U3 state 832 * during boot. Some USB devices survive in U3 state over S4 hibernate 833 * 834 * Disable ports that are in U3 if remote wake is not enabled for either 835 * host controller or connected device 836 */ 837 838 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 839 return 0; 840 841 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 842 port = &xhci->hw_ports[i]; 843 portsc = readl(port->addr); 844 845 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 846 continue; 847 848 if (!port->slot_id || !xhci->devs[port->slot_id]) { 849 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 850 port->slot_id, port->rhub->hcd->self.busnum, 851 port->hcd_portnum + 1); 852 continue; 853 } 854 855 udev = xhci->devs[port->slot_id]->udev; 856 857 /* if wakeup is enabled then don't disable the port */ 858 if (udev->do_remote_wakeup && do_wakeup) 859 continue; 860 861 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 862 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 863 portsc = xhci_port_state_to_neutral(portsc); 864 writel(portsc | PORT_PE, port->addr); 865 } 866 867 return 0; 868} 869 870static void xhci_pci_shutdown(struct usb_hcd *hcd) 871{ 872 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 873 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 874 875 xhci_shutdown(hcd); 876 xhci_cleanup_msix(xhci); 877 878 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 879 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 880 pci_set_power_state(pdev, PCI_D3hot); 881} 882 883/*-------------------------------------------------------------------------*/ 884 885static const struct xhci_driver_data reneses_data = { 886 .quirks = XHCI_RENESAS_FW_QUIRK, 887 .firmware = "renesas_usb_fw.mem", 888}; 889 890/* PCI driver selection metadata; PCI hotplugging uses this */ 891static const struct pci_device_id pci_ids[] = { 892 { PCI_DEVICE(0x1912, 0x0014), 893 .driver_data = (unsigned long)&reneses_data, 894 }, 895 { PCI_DEVICE(0x1912, 0x0015), 896 .driver_data = (unsigned long)&reneses_data, 897 }, 898 /* handle any USB 3.0 xHCI controller */ 899 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 900 }, 901 { /* end: all zeroes */ } 902}; 903MODULE_DEVICE_TABLE(pci, pci_ids); 904 905/* 906 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 907 * load firmware, so don't encumber the xhci-pci driver with it. 908 */ 909#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 910MODULE_FIRMWARE("renesas_usb_fw.mem"); 911#endif 912 913/* pci driver glue; this is a "new style" PCI driver module */ 914static struct pci_driver xhci_pci_driver = { 915 .name = hcd_name, 916 .id_table = pci_ids, 917 918 .probe = xhci_pci_probe, 919 .remove = xhci_pci_remove, 920 /* suspend and resume implemented later */ 921 922 .shutdown = usb_hcd_pci_shutdown, 923 .driver = { 924 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 925 }, 926}; 927 928static int __init xhci_pci_init(void) 929{ 930 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 931 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 932 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 933 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 934 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 935 xhci_pci_hc_driver.stop = xhci_pci_stop; 936 return pci_register_driver(&xhci_pci_driver); 937} 938module_init(xhci_pci_init); 939 940static void __exit xhci_pci_exit(void) 941{ 942 pci_unregister_driver(&xhci_pci_driver); 943} 944module_exit(xhci_pci_exit); 945 946MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 947MODULE_LICENSE("GPL"); 948