1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2004,2012 Freescale Semiconductor, Inc 4 * All rights reserved. 5 * 6 * Freescale USB device/endpoint management registers 7 */ 8#ifndef __FSL_USB2_UDC_H 9#define __FSL_USB2_UDC_H 10 11#include <linux/usb/ch9.h> 12#include <linux/usb/gadget.h> 13 14/* ### define USB registers here 15 */ 16#define USB_MAX_CTRL_PAYLOAD 64 17#define USB_DR_SYS_OFFSET 0x400 18 19 /* USB DR device mode registers (Little Endian) */ 20struct usb_dr_device { 21 /* Capability register */ 22 u8 res1[256]; 23 u16 caplength; /* Capability Register Length */ 24 u16 hciversion; /* Host Controller Interface Version */ 25 u32 hcsparams; /* Host Controller Structural Parameters */ 26 u32 hccparams; /* Host Controller Capability Parameters */ 27 u8 res2[20]; 28 u32 dciversion; /* Device Controller Interface Version */ 29 u32 dccparams; /* Device Controller Capability Parameters */ 30 u8 res3[24]; 31 /* Operation register */ 32 u32 usbcmd; /* USB Command Register */ 33 u32 usbsts; /* USB Status Register */ 34 u32 usbintr; /* USB Interrupt Enable Register */ 35 u32 frindex; /* Frame Index Register */ 36 u8 res4[4]; 37 u32 deviceaddr; /* Device Address */ 38 u32 endpointlistaddr; /* Endpoint List Address Register */ 39 u8 res5[4]; 40 u32 burstsize; /* Master Interface Data Burst Size Register */ 41 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ 42 u8 res6[24]; 43 u32 configflag; /* Configure Flag Register */ 44 u32 portsc1; /* Port 1 Status and Control Register */ 45 u8 res7[28]; 46 u32 otgsc; /* On-The-Go Status and Control */ 47 u32 usbmode; /* USB Mode Register */ 48 u32 endptsetupstat; /* Endpoint Setup Status Register */ 49 u32 endpointprime; /* Endpoint Initialization Register */ 50 u32 endptflush; /* Endpoint Flush Register */ 51 u32 endptstatus; /* Endpoint Status Register */ 52 u32 endptcomplete; /* Endpoint Complete Register */ 53 u32 endptctrl[6]; /* Endpoint Control Registers */ 54}; 55 56 /* USB DR host mode registers (Little Endian) */ 57struct usb_dr_host { 58 /* Capability register */ 59 u8 res1[256]; 60 u16 caplength; /* Capability Register Length */ 61 u16 hciversion; /* Host Controller Interface Version */ 62 u32 hcsparams; /* Host Controller Structural Parameters */ 63 u32 hccparams; /* Host Controller Capability Parameters */ 64 u8 res2[20]; 65 u32 dciversion; /* Device Controller Interface Version */ 66 u32 dccparams; /* Device Controller Capability Parameters */ 67 u8 res3[24]; 68 /* Operation register */ 69 u32 usbcmd; /* USB Command Register */ 70 u32 usbsts; /* USB Status Register */ 71 u32 usbintr; /* USB Interrupt Enable Register */ 72 u32 frindex; /* Frame Index Register */ 73 u8 res4[4]; 74 u32 periodiclistbase; /* Periodic Frame List Base Address Register */ 75 u32 asynclistaddr; /* Current Asynchronous List Address Register */ 76 u8 res5[4]; 77 u32 burstsize; /* Master Interface Data Burst Size Register */ 78 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ 79 u8 res6[24]; 80 u32 configflag; /* Configure Flag Register */ 81 u32 portsc1; /* Port 1 Status and Control Register */ 82 u8 res7[28]; 83 u32 otgsc; /* On-The-Go Status and Control */ 84 u32 usbmode; /* USB Mode Register */ 85 u32 endptsetupstat; /* Endpoint Setup Status Register */ 86 u32 endpointprime; /* Endpoint Initialization Register */ 87 u32 endptflush; /* Endpoint Flush Register */ 88 u32 endptstatus; /* Endpoint Status Register */ 89 u32 endptcomplete; /* Endpoint Complete Register */ 90 u32 endptctrl[6]; /* Endpoint Control Registers */ 91}; 92 93 /* non-EHCI USB system interface registers (Big Endian) */ 94struct usb_sys_interface { 95 u32 snoop1; 96 u32 snoop2; 97 u32 age_cnt_thresh; /* Age Count Threshold Register */ 98 u32 pri_ctrl; /* Priority Control Register */ 99 u32 si_ctrl; /* System Interface Control Register */ 100 u8 res[236]; 101 u32 control; /* General Purpose Control Register */ 102}; 103 104/* ep0 transfer state */ 105#define WAIT_FOR_SETUP 0 106#define DATA_STATE_XMIT 1 107#define DATA_STATE_NEED_ZLP 2 108#define WAIT_FOR_OUT_STATUS 3 109#define DATA_STATE_RECV 4 110 111/* Device Controller Capability Parameter register */ 112#define DCCPARAMS_DC 0x00000080 113#define DCCPARAMS_DEN_MASK 0x0000001f 114 115/* Frame Index Register Bit Masks */ 116#define USB_FRINDEX_MASKS 0x3fff 117/* USB CMD Register Bit Masks */ 118#define USB_CMD_RUN_STOP 0x00000001 119#define USB_CMD_CTRL_RESET 0x00000002 120#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010 121#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020 122#define USB_CMD_INT_AA_DOORBELL 0x00000040 123#define USB_CMD_ASP 0x00000300 124#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800 125#define USB_CMD_SUTW 0x00002000 126#define USB_CMD_ATDTW 0x00004000 127#define USB_CMD_ITC 0x00FF0000 128 129/* bit 15,3,2 are frame list size */ 130#define USB_CMD_FRAME_SIZE_1024 0x00000000 131#define USB_CMD_FRAME_SIZE_512 0x00000004 132#define USB_CMD_FRAME_SIZE_256 0x00000008 133#define USB_CMD_FRAME_SIZE_128 0x0000000C 134#define USB_CMD_FRAME_SIZE_64 0x00008000 135#define USB_CMD_FRAME_SIZE_32 0x00008004 136#define USB_CMD_FRAME_SIZE_16 0x00008008 137#define USB_CMD_FRAME_SIZE_8 0x0000800C 138 139/* bit 9-8 are async schedule park mode count */ 140#define USB_CMD_ASP_00 0x00000000 141#define USB_CMD_ASP_01 0x00000100 142#define USB_CMD_ASP_10 0x00000200 143#define USB_CMD_ASP_11 0x00000300 144#define USB_CMD_ASP_BIT_POS 8 145 146/* bit 23-16 are interrupt threshold control */ 147#define USB_CMD_ITC_NO_THRESHOLD 0x00000000 148#define USB_CMD_ITC_1_MICRO_FRM 0x00010000 149#define USB_CMD_ITC_2_MICRO_FRM 0x00020000 150#define USB_CMD_ITC_4_MICRO_FRM 0x00040000 151#define USB_CMD_ITC_8_MICRO_FRM 0x00080000 152#define USB_CMD_ITC_16_MICRO_FRM 0x00100000 153#define USB_CMD_ITC_32_MICRO_FRM 0x00200000 154#define USB_CMD_ITC_64_MICRO_FRM 0x00400000 155#define USB_CMD_ITC_BIT_POS 16 156 157/* USB STS Register Bit Masks */ 158#define USB_STS_INT 0x00000001 159#define USB_STS_ERR 0x00000002 160#define USB_STS_PORT_CHANGE 0x00000004 161#define USB_STS_FRM_LST_ROLL 0x00000008 162#define USB_STS_SYS_ERR 0x00000010 163#define USB_STS_IAA 0x00000020 164#define USB_STS_RESET 0x00000040 165#define USB_STS_SOF 0x00000080 166#define USB_STS_SUSPEND 0x00000100 167#define USB_STS_HC_HALTED 0x00001000 168#define USB_STS_RCL 0x00002000 169#define USB_STS_PERIODIC_SCHEDULE 0x00004000 170#define USB_STS_ASYNC_SCHEDULE 0x00008000 171 172/* USB INTR Register Bit Masks */ 173#define USB_INTR_INT_EN 0x00000001 174#define USB_INTR_ERR_INT_EN 0x00000002 175#define USB_INTR_PTC_DETECT_EN 0x00000004 176#define USB_INTR_FRM_LST_ROLL_EN 0x00000008 177#define USB_INTR_SYS_ERR_EN 0x00000010 178#define USB_INTR_ASYN_ADV_EN 0x00000020 179#define USB_INTR_RESET_EN 0x00000040 180#define USB_INTR_SOF_EN 0x00000080 181#define USB_INTR_DEVICE_SUSPEND 0x00000100 182 183/* Device Address bit masks */ 184#define USB_DEVICE_ADDRESS_MASK 0xFE000000 185#define USB_DEVICE_ADDRESS_BIT_POS 25 186 187/* endpoint list address bit masks */ 188#define USB_EP_LIST_ADDRESS_MASK 0xfffff800 189 190/* PORTSCX Register Bit Masks */ 191#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001 192#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002 193#define PORTSCX_PORT_ENABLE 0x00000004 194#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008 195#define PORTSCX_OVER_CURRENT_ACT 0x00000010 196#define PORTSCX_OVER_CURRENT_CHG 0x00000020 197#define PORTSCX_PORT_FORCE_RESUME 0x00000040 198#define PORTSCX_PORT_SUSPEND 0x00000080 199#define PORTSCX_PORT_RESET 0x00000100 200#define PORTSCX_LINE_STATUS_BITS 0x00000C00 201#define PORTSCX_PORT_POWER 0x00001000 202#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000 203#define PORTSCX_PORT_TEST_CTRL 0x000F0000 204#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000 205#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000 206#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000 207#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000 208#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000 209#define PORTSCX_PORT_SPEED_MASK 0x0C000000 210#define PORTSCX_PORT_WIDTH 0x10000000 211#define PORTSCX_PHY_TYPE_SEL 0xC0000000 212 213/* bit 11-10 are line status */ 214#define PORTSCX_LINE_STATUS_SE0 0x00000000 215#define PORTSCX_LINE_STATUS_JSTATE 0x00000400 216#define PORTSCX_LINE_STATUS_KSTATE 0x00000800 217#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00 218#define PORTSCX_LINE_STATUS_BIT_POS 10 219 220/* bit 15-14 are port indicator control */ 221#define PORTSCX_PIC_OFF 0x00000000 222#define PORTSCX_PIC_AMBER 0x00004000 223#define PORTSCX_PIC_GREEN 0x00008000 224#define PORTSCX_PIC_UNDEF 0x0000C000 225#define PORTSCX_PIC_BIT_POS 14 226 227/* bit 19-16 are port test control */ 228#define PORTSCX_PTC_DISABLE 0x00000000 229#define PORTSCX_PTC_JSTATE 0x00010000 230#define PORTSCX_PTC_KSTATE 0x00020000 231#define PORTSCX_PTC_SEQNAK 0x00030000 232#define PORTSCX_PTC_PACKET 0x00040000 233#define PORTSCX_PTC_FORCE_EN 0x00050000 234#define PORTSCX_PTC_BIT_POS 16 235 236/* bit 27-26 are port speed */ 237#define PORTSCX_PORT_SPEED_FULL 0x00000000 238#define PORTSCX_PORT_SPEED_LOW 0x04000000 239#define PORTSCX_PORT_SPEED_HIGH 0x08000000 240#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000 241#define PORTSCX_SPEED_BIT_POS 26 242 243/* bit 28 is parallel transceiver width for UTMI interface */ 244#define PORTSCX_PTW 0x10000000 245#define PORTSCX_PTW_8BIT 0x00000000 246#define PORTSCX_PTW_16BIT 0x10000000 247 248/* bit 31-30 are port transceiver select */ 249#define PORTSCX_PTS_UTMI 0x00000000 250#define PORTSCX_PTS_ULPI 0x80000000 251#define PORTSCX_PTS_FSLS 0xC0000000 252#define PORTSCX_PTS_BIT_POS 30 253 254/* otgsc Register Bit Masks */ 255#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 256#define OTGSC_CTRL_VUSB_CHARGE 0x00000002 257#define OTGSC_CTRL_OTG_TERM 0x00000008 258#define OTGSC_CTRL_DATA_PULSING 0x00000010 259#define OTGSC_STS_USB_ID 0x00000100 260#define OTGSC_STS_A_VBUS_VALID 0x00000200 261#define OTGSC_STS_A_SESSION_VALID 0x00000400 262#define OTGSC_STS_B_SESSION_VALID 0x00000800 263#define OTGSC_STS_B_SESSION_END 0x00001000 264#define OTGSC_STS_1MS_TOGGLE 0x00002000 265#define OTGSC_STS_DATA_PULSING 0x00004000 266#define OTGSC_INTSTS_USB_ID 0x00010000 267#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 268#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 269#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 270#define OTGSC_INTSTS_B_SESSION_END 0x00100000 271#define OTGSC_INTSTS_1MS 0x00200000 272#define OTGSC_INTSTS_DATA_PULSING 0x00400000 273#define OTGSC_INTR_USB_ID 0x01000000 274#define OTGSC_INTR_A_VBUS_VALID 0x02000000 275#define OTGSC_INTR_A_SESSION_VALID 0x04000000 276#define OTGSC_INTR_B_SESSION_VALID 0x08000000 277#define OTGSC_INTR_B_SESSION_END 0x10000000 278#define OTGSC_INTR_1MS_TIMER 0x20000000 279#define OTGSC_INTR_DATA_PULSING 0x40000000 280 281/* USB MODE Register Bit Masks */ 282#define USB_MODE_CTRL_MODE_IDLE 0x00000000 283#define USB_MODE_CTRL_MODE_DEVICE 0x00000002 284#define USB_MODE_CTRL_MODE_HOST 0x00000003 285#define USB_MODE_CTRL_MODE_MASK 0x00000003 286#define USB_MODE_CTRL_MODE_RSV 0x00000001 287#define USB_MODE_ES 0x00000004 /* Endian Select */ 288#define USB_MODE_SETUP_LOCK_OFF 0x00000008 289#define USB_MODE_STREAM_DISABLE 0x00000010 290/* Endpoint Flush Register */ 291#define EPFLUSH_TX_OFFSET 0x00010000 292#define EPFLUSH_RX_OFFSET 0x00000000 293 294/* Endpoint Setup Status bit masks */ 295#define EP_SETUP_STATUS_MASK 0x0000003F 296#define EP_SETUP_STATUS_EP0 0x00000001 297 298/* ENDPOINTCTRLx Register Bit Masks */ 299#define EPCTRL_TX_ENABLE 0x00800000 300#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */ 301#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */ 302#define EPCTRL_TX_TYPE 0x000C0000 303#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */ 304#define EPCTRL_TX_EP_STALL 0x00010000 305#define EPCTRL_RX_ENABLE 0x00000080 306#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */ 307#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */ 308#define EPCTRL_RX_TYPE 0x0000000C 309#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */ 310#define EPCTRL_RX_EP_STALL 0x00000001 311 312/* bit 19-18 and 3-2 are endpoint type */ 313#define EPCTRL_EP_TYPE_CONTROL 0 314#define EPCTRL_EP_TYPE_ISO 1 315#define EPCTRL_EP_TYPE_BULK 2 316#define EPCTRL_EP_TYPE_INTERRUPT 3 317#define EPCTRL_TX_EP_TYPE_SHIFT 18 318#define EPCTRL_RX_EP_TYPE_SHIFT 2 319 320/* SNOOPn Register Bit Masks */ 321#define SNOOP_ADDRESS_MASK 0xFFFFF000 322#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */ 323#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */ 324#define SNOOP_SIZE_8KB 0x0C 325#define SNOOP_SIZE_16KB 0x0D 326#define SNOOP_SIZE_32KB 0x0E 327#define SNOOP_SIZE_64KB 0x0F 328#define SNOOP_SIZE_128KB 0x10 329#define SNOOP_SIZE_256KB 0x11 330#define SNOOP_SIZE_512KB 0x12 331#define SNOOP_SIZE_1MB 0x13 332#define SNOOP_SIZE_2MB 0x14 333#define SNOOP_SIZE_4MB 0x15 334#define SNOOP_SIZE_8MB 0x16 335#define SNOOP_SIZE_16MB 0x17 336#define SNOOP_SIZE_32MB 0x18 337#define SNOOP_SIZE_64MB 0x19 338#define SNOOP_SIZE_128MB 0x1A 339#define SNOOP_SIZE_256MB 0x1B 340#define SNOOP_SIZE_512MB 0x1C 341#define SNOOP_SIZE_1GB 0x1D 342#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */ 343 344/* pri_ctrl Register Bit Masks */ 345#define PRI_CTRL_PRI_LVL1 0x0000000C 346#define PRI_CTRL_PRI_LVL0 0x00000003 347 348/* si_ctrl Register Bit Masks */ 349#define SI_CTRL_ERR_DISABLE 0x00000010 350#define SI_CTRL_IDRC_DISABLE 0x00000008 351#define SI_CTRL_RD_SAFE_EN 0x00000004 352#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002 353#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001 354 355/* control Register Bit Masks */ 356#define USB_CTRL_IOENB 0x00000004 357#define USB_CTRL_ULPI_INT0EN 0x00000001 358#define USB_CTRL_UTMI_PHY_EN 0x00000200 359#define USB_CTRL_USB_EN 0x00000004 360#define USB_CTRL_ULPI_PHY_CLK_SEL 0x00000400 361 362/* Endpoint Queue Head data struct 363 * Rem: all the variables of qh are LittleEndian Mode 364 * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr 365 */ 366struct ep_queue_head { 367 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len 368 and IOS(15) */ 369 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */ 370 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */ 371 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15), 372 MultO(11-10), STS (7-0) */ 373 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */ 374 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */ 375 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */ 376 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */ 377 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */ 378 u32 res1; 379 u8 setup_buffer[8]; /* Setup data 8 bytes */ 380 u32 res2[4]; 381}; 382 383/* Endpoint Queue Head Bit Masks */ 384#define EP_QUEUE_HEAD_MULT_POS 30 385#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000 386#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16 387#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) 388#define EP_QUEUE_HEAD_IOS 0x00008000 389#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001 390#define EP_QUEUE_HEAD_IOC 0x00008000 391#define EP_QUEUE_HEAD_MULTO 0x00000C00 392#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040 393#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080 394#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF 395#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 396#define EP_QUEUE_FRINDEX_MASK 0x000007FF 397#define EP_MAX_LENGTH_TRANSFER 0x4000 398 399/* Endpoint Transfer Descriptor data struct */ 400/* Rem: all the variables of td are LittleEndian Mode */ 401struct ep_td_struct { 402 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set 403 indicate invalid */ 404 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15), 405 MultO(11-10), STS (7-0) */ 406 u32 buff_ptr0; /* Buffer pointer Page 0 */ 407 u32 buff_ptr1; /* Buffer pointer Page 1 */ 408 u32 buff_ptr2; /* Buffer pointer Page 2 */ 409 u32 buff_ptr3; /* Buffer pointer Page 3 */ 410 u32 buff_ptr4; /* Buffer pointer Page 4 */ 411 u32 res; 412 /* 32 bytes */ 413 dma_addr_t td_dma; /* dma address for this td */ 414 /* virtual address of next td specified in next_td_ptr */ 415 struct ep_td_struct *next_td_virt; 416}; 417 418/* Endpoint Transfer Descriptor bit Masks */ 419#define DTD_NEXT_TERMINATE 0x00000001 420#define DTD_IOC 0x00008000 421#define DTD_STATUS_ACTIVE 0x00000080 422#define DTD_STATUS_HALTED 0x00000040 423#define DTD_STATUS_DATA_BUFF_ERR 0x00000020 424#define DTD_STATUS_TRANSACTION_ERR 0x00000008 425#define DTD_RESERVED_FIELDS 0x80007300 426#define DTD_ADDR_MASK 0xFFFFFFE0 427#define DTD_PACKET_SIZE 0x7FFF0000 428#define DTD_LENGTH_BIT_POS 16 429#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ 430 DTD_STATUS_DATA_BUFF_ERR | \ 431 DTD_STATUS_TRANSACTION_ERR) 432/* Alignment requirements; must be a power of two */ 433#define DTD_ALIGNMENT 0x20 434#define QH_ALIGNMENT 2048 435 436/* Controller dma boundary */ 437#define UDC_DMA_BOUNDARY 0x1000 438 439/*-------------------------------------------------------------------------*/ 440 441/* ### driver private data 442 */ 443struct fsl_req { 444 struct usb_request req; 445 struct list_head queue; 446 /* ep_queue() func will add 447 a request->queue into a udc_ep->queue 'd tail */ 448 struct fsl_ep *ep; 449 unsigned mapped:1; 450 451 struct ep_td_struct *head, *tail; /* For dTD List 452 cpu endian Virtual addr */ 453 unsigned int dtd_count; 454}; 455 456#define REQ_UNCOMPLETE 1 457 458struct fsl_ep { 459 struct usb_ep ep; 460 struct list_head queue; 461 struct fsl_udc *udc; 462 struct ep_queue_head *qh; 463 struct usb_gadget *gadget; 464 465 char name[14]; 466 unsigned stopped:1; 467}; 468 469#define EP_DIR_IN 1 470#define EP_DIR_OUT 0 471 472struct fsl_udc { 473 struct usb_gadget gadget; 474 struct usb_gadget_driver *driver; 475 struct fsl_usb2_platform_data *pdata; 476 struct completion *done; /* to make sure release() is done */ 477 struct fsl_ep *eps; 478 unsigned int max_ep; 479 unsigned int irq; 480 481 struct usb_ctrlrequest local_setup_buff; 482 spinlock_t lock; 483 struct usb_phy *transceiver; 484 unsigned softconnect:1; 485 unsigned vbus_active:1; 486 unsigned stopped:1; 487 unsigned remote_wakeup:1; 488 unsigned already_stopped:1; 489 unsigned big_endian_desc:1; 490 491 struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ 492 struct fsl_req *status_req; /* ep0 status request */ 493 struct dma_pool *td_pool; /* dma pool for DTD */ 494 enum fsl_usb2_phy_modes phy_mode; 495 496 size_t ep_qh_size; /* size after alignment adjustment*/ 497 dma_addr_t ep_qh_dma; /* dma address of QH */ 498 499 u32 max_pipes; /* Device max pipes */ 500 u32 bus_reset; /* Device is bus resetting */ 501 u32 resume_state; /* USB state to resume */ 502 u32 usb_state; /* USB current state */ 503 u32 ep0_state; /* Endpoint zero state */ 504 u32 ep0_dir; /* Endpoint zero direction: can be 505 USB_DIR_IN or USB_DIR_OUT */ 506 u8 device_address; /* Device USB address */ 507}; 508 509/*-------------------------------------------------------------------------*/ 510 511/* ### Add board specific defines here 512 */ 513 514/* 515 * ### pipe direction macro from device view 516 */ 517#define USB_RECV 0 /* OUT EP */ 518#define USB_SEND 1 /* IN EP */ 519 520/* 521 * ### internal used help routines. 522 */ 523#define ep_index(EP) ((EP)->ep.desc->bEndpointAddress&0xF) 524#define ep_maxpacket(EP) ((EP)->ep.maxpacket) 525#define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ 526 USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \ 527 & USB_DIR_IN)==USB_DIR_IN) 528#define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \ 529 &udc->eps[pipe]) 530#define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \ 531 * 2 + ((windex & USB_DIR_IN) ? 1 : 0)) 532#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP)) 533 534static inline struct ep_queue_head *get_qh_by_ep(struct fsl_ep *ep) 535{ 536 /* we only have one ep0 structure but two queue heads */ 537 if (ep_index(ep) != 0) 538 return ep->qh; 539 else 540 return &ep->udc->ep_qh[(ep->udc->ep0_dir == 541 USB_DIR_IN) ? 1 : 0]; 542} 543 544#endif 545